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15 May 2020 04:48:29 -0700 Received: from andy by smile with local (Exim 4.93) (envelope-from ) id 1jZYpL-006qm5-Iq; Fri, 15 May 2020 14:48:31 +0300 Date: Fri, 15 May 2020 14:48:31 +0300 From: Andy Shevchenko To: "Ramuthevar, Vadivel MuruganX" Subject: Re: [PATCH v7 2/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC Message-ID: <20200515114831.GS185537@smile.fi.intel.com> References: <20200515105537.4876-1-vadivel.muruganx.ramuthevar@linux.intel.com> <20200515105537.4876-3-vadivel.muruganx.ramuthevar@linux.intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200515105537.4876-3-vadivel.muruganx.ramuthevar@linux.intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200515_044834_328807_B26313E6 X-CRM114-Status: GOOD ( 11.86 ) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cheol.yong.kim@intel.com, devicetree@vger.kernel.org, qi-ming.wu@intel.com, anders.roxell@linaro.org, vigneshr@ti.com, arnd@arndb.de, hauke.mehrtens@intel.com, richard@nod.at, brendanhiggins@google.com, linux-kernel@vger.kernel.org, robh+dt@kernel.org, linux-mips@vger.kernel.org, boris.brezillon@collabora.com, linux-mtd@lists.infradead.org, miquel.raynal@bootlin.com, tglx@linutronix.de, masonccyang@mxic.com.tw Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org On Fri, May 15, 2020 at 06:55:37PM +0800, Ramuthevar,Vadivel MuruganX wrote: > From: Ramuthevar Vadivel Murugan > > This patch adds the new IP of Nand Flash Controller(NFC) support > on Intel's Lightning Mountain(LGM) SoC. > > DMA is used for burst data transfer operation, also DMA HW supports > aligned 32bit memory address and aligned data access by default. > DMA burst of 8 supported. Data register used to support the read/write > operation from/to device. > > NAND controller driver implements ->exec_op() to replace legacy hooks, > these specific call-back method to execute NAND operations. ... > + ebu_host->dma_tx = dma_request_chan(dev, "tx"); > + if (IS_ERR(ebu_host->dma_tx)) { > + ret = PTR_ERR(ebu_host->dma_tx); > + dev_err(dev, "DMA tx channel request fail!.\n"); > + goto err_cleanup_dma; > + } > + > + ebu_host->dma_rx = dma_request_chan(dev, "rx"); > + if (IS_ERR(ebu_host->dma_rx)) { > + ret = PTR_ERR(ebu_host->dma_rx); > + dev_err(dev, "DMA tx channel request fail!.\n"); rx ? > + goto err_cleanup_dma; > + } ... > +static int ebu_nand_remove(struct platform_device *pdev) > +{ > + struct ebu_nand_controller *ebu_host = platform_get_drvdata(pdev); > + > + if (ebu_host) { I dunno why you need this check? Maybe I forgot your answer to my comment? > + mtd_device_unregister(nand_to_mtd(&ebu_host->chip)); > + nand_cleanup(&ebu_host->chip); > + ebu_nand_disable(&ebu_host->chip); > + ebu_dma_cleanup(ebu_host); > + clk_disable_unprepare(ebu_host->clk); > + } > + > + return 0; > +} -- With Best Regards, Andy Shevchenko ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/