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Mon, 15 Jun 2020 05:53:25 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Mon, 15 Jun 2020 05:53:24 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Mon, 15 Jun 2020 05:53:24 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 05FArNZB101156; Mon, 15 Jun 2020 05:53:24 -0500 Date: Mon, 15 Jun 2020 16:23:23 +0530 From: Pratyush Yadav To: Yicong Yang Subject: Re: [RFC PATCH v2 1/2] mtd: spi-nor: Add capability to disable flash quad mode Message-ID: <20200615105321.d2pjwjmm3wch4qtx@ti.com> References: <1589282819-42358-1-git-send-email-yangyicong@hisilicon.com> <1589282819-42358-2-git-send-email-yangyicong@hisilicon.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1589282819-42358-2-git-send-email-yangyicong@hisilicon.com> User-Agent: NeoMutt/20171215 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200615_035340_598721_25582CD4 X-CRM114-Status: GOOD ( 19.93 ) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: vigneshr@ti.com, sergei.shtylyov@cogentembedded.com, tudor.ambarus@microchip.com, richard@nod.at, me@yadavpratyush.com, john.garry@huawei.com, linuxarm@huawei.com, linux-mtd@lists.infradead.org, miquel.raynal@bootlin.com, alexander.sverdlin@nokia.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org Hi Yicong, You generally shouldn't mark a series as "RFC" if you intend it to get merged in. On 12/05/20 07:26PM, Yicong Yang wrote: > Previous we didn't provide a way to disable the flash's quad mode. > Which means we cannot do some cleanup works when to remove or > poweroff the flash, like what set 4-byte address mode does in > spi_nor_restore(). > > Add the capability to disable the flash quad mode, by introducing > an enable flag in the flash parameters quad_enable() hooks and > related functions. > > Signed-off-by: Yicong Yang > --- > drivers/mtd/spi-nor/core.c | 53 ++++++++++++++++++++++++++++++++-------------- > drivers/mtd/spi-nor/core.h | 8 +++---- > 2 files changed, 41 insertions(+), 20 deletions(-) Reviewed-by: Pratyush Yadav Nits below. > diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c > index cc68ea8..72e8d8b 100644 > --- a/drivers/mtd/spi-nor/core.c > +++ b/drivers/mtd/spi-nor/core.c > @@ -1907,15 +1907,17 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len) > } > > /** > - * spi_nor_sr1_bit6_quad_enable() - Set the Quad Enable BIT(6) in the Status > + * spi_nor_sr1_bit6_quad_enable() - Set/Unset the Quad Enable BIT(6) in the > + * Status > * Register 1. The "Register 1" should be on the same line as the "Status above". > * @nor: pointer to a 'struct spi_nor' > + * @enable: true to enter quad mode. false to leave quad mode. > * > * Bit 6 of the Status Register 1 is the QE bit for Macronix like QSPI memories. > * > * Return: 0 on success, -errno otherwise. > */ > -int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor) > +int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor, bool enable) > { > int ret; > > @@ -1923,45 +1925,59 @@ int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor) > if (ret) > return ret; > > - if (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6) > + if ((enable && (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6)) || > + !(enable || (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6))) I still think writing it as: (!enable && !(nor->bouncebuf[0] & SR1_QUAD_EN_BIT6)) is slightly more readable. But maybe it's just me so this is OK I guess. > return 0; > > - nor->bouncebuf[0] |= SR1_QUAD_EN_BIT6; > + if (enable) > + nor->bouncebuf[0] |= SR1_QUAD_EN_BIT6; > + else > + nor->bouncebuf[0] &= ~SR1_QUAD_EN_BIT6; > > return spi_nor_write_sr1_and_check(nor, nor->bouncebuf[0]); > } > > /** > - * spi_nor_sr2_bit1_quad_enable() - set the Quad Enable BIT(1) in the Status > + * spi_nor_sr2_bit1_quad_enable() - set/unset the Quad Enable BIT(1) in the > + * Status > * Register 2. The "Register 2" should be on the same line as the "Status above". > * @nor: pointer to a 'struct spi_nor'. > + * @enable: true to enter quad mode. false to leave quad mode. > * > * Bit 1 of the Status Register 2 is the QE bit for Spansion like QSPI memories. > * > * Return: 0 on success, -errno otherwise. > */ > -int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor) > +int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor, bool enable) > { > int ret; [...] > diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h > index 6f2f6b2..719a31d 100644 > --- a/drivers/mtd/spi-nor/core.h > +++ b/drivers/mtd/spi-nor/core.h > @@ -219,7 +219,7 @@ struct spi_nor_flash_parameter { > > struct spi_nor_erase_map erase_map; > > - int (*quad_enable)(struct spi_nor *nor); > + int (*quad_enable)(struct spi_nor *nor, bool enable); Update the comment above reflecting that @quad_enable "enables/disables SPI NOR quad mode". > int (*set_4byte_addr_mode)(struct spi_nor *nor, bool enable); > u32 (*convert_addr)(struct spi_nor *nor, u32 addr); > int (*setup)(struct spi_nor *nor, const struct spi_nor_hwcaps *hwcaps); -- Regards, Pratyush Yadav Texas Instruments India ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/