From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Praveenkumar I <ipkumar@codeaurora.org>
Cc: kathirav@codeaurora.org, vigneshr@ti.com, richard@nod.at,
linux-kernel@vger.kernel.org, stable@vger.kernel.org,
peter.ujfalusi@ti.com, boris.brezillon@collabora.com,
linux-mtd@lists.infradead.org, sivaprak@codeaurora.org
Subject: Re: [PATCH] mtd: rawnand: qcom: Fix DMA sync on FLASH_STATUS register read
Date: Wed, 28 Oct 2020 15:23:02 +0100 [thread overview]
Message-ID: <20201028152302.2f830077@xps13> (raw)
In-Reply-To: <24a781a3-488c-b638-1b92-0f279807446f@codeaurora.org>
Hello,
Praveenkumar I <ipkumar@codeaurora.org> wrote on Wed, 28 Oct 2020
19:48:34 +0530:
> Hi Miquel,
>
> Please find the inline reply.
>
> Thanks,
> Praveenkumar I
>
>
> On 10/28/2020 3:38 PM, Miquel Raynal wrote:
> > Hello,
> >
> > Praveenkumar I <ipkumar@codeaurora.org> wrote on Fri, 9 Oct 2020
> > 13:37:52 +0530:
> >
> >> After each codeword NAND_FLASH_STATUS is read for possible operational
> >> failures. But there is no DMA sync for CPU operation before reading it
> >> and this leads to incorrect or older copy of DMA buffer in reg_read_buf.
> >>
> >> This patch adds the DMA sync on reg_read_buf for CPU before reading it.
> >>
> >> Fixes: 5bc36b2bf6e2 ("mtd: rawnand: qcom: check for operation errors in case of raw read")
> > I guess this deserves a proper Cc: stable tag?
> > >> Yes. I will send a V2 Patch with stable tag in Cc
That's fine for this one, I'll add it myself.
> >> Signed-off-by: Praveenkumar I <ipkumar@codeaurora.org>
> > I think your full name is required in the SoB line (should match the
> > authorship).
> > >> "Praveenkumar I" is my full name and it is same as the authorship.
Ok, sorry for the confusion.
> > Otherwise looks good to me.
> >
> >> ---
> >> drivers/mtd/nand/raw/qcom_nandc.c | 2 ++
> >> 1 file changed, 2 insertions(+)
> >>
> >> diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
> >> index bd7a7251429b..5bb85f1ba84c 100644
> >> --- a/drivers/mtd/nand/raw/qcom_nandc.c
> >> +++ b/drivers/mtd/nand/raw/qcom_nandc.c
> >> @@ -1570,6 +1570,8 @@ static int check_flash_errors(struct qcom_nand_host *host, int cw_cnt)
> >> struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
> >> int i;
> >> >> + nandc_read_buffer_sync(nandc, true);
> >> +
> >> for (i = 0; i < cw_cnt; i++) {
> >> u32 flash = le32_to_cpu(nandc->reg_read_buf[i]);
> >> > Thanks,
> > Miquèl
>
Cheers,
Miquèl
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next prev parent reply other threads:[~2020-10-28 14:24 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-09 8:07 [PATCH] mtd: rawnand: qcom: Fix DMA sync on FLASH_STATUS register read Praveenkumar I
2020-10-28 10:08 ` Miquel Raynal
[not found] ` <24a781a3-488c-b638-1b92-0f279807446f@codeaurora.org>
2020-10-28 14:23 ` Miquel Raynal [this message]
2020-10-30 17:27 ` Miquel Raynal
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