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From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Richard Weinberger <richard@nod.at>,
	Vignesh Raghavendra <vigneshr@ti.com>,
	Tudor Ambarus <Tudor.Ambarus@microchip.com>,
	<linux-mtd@lists.infradead.org>
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
	Michal Simek <monstr@monstr.eu>,
	Naga Sureshkumar Relli <nagasure@xilinx.com>,
	Amit Kumar Mahapatra <akumarma@xilinx.com>,
	Miquel Raynal <miquel.raynal@bootlin.com>
Subject: [PATCH 06/22] mtd: rawnand: Use more recent ONFI specification wording
Date: Wed,  5 May 2021 23:37:34 +0200	[thread overview]
Message-ID: <20210505213750.257417-7-miquel.raynal@bootlin.com> (raw)
In-Reply-To: <20210505213750.257417-1-miquel.raynal@bootlin.com>

In particular, first ONFI specifications referred to SDR modes as
asynchronous modes, which is not the term we usually have in mind. The
spec has then been updated, so do the same here in the NAND subsystem to
avoid any possible confusion.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
 drivers/mtd/nand/raw/cadence-nand-controller.c | 6 +++---
 drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.h     | 2 +-
 drivers/mtd/nand/raw/nand_base.c               | 2 +-
 drivers/mtd/nand/raw/nand_onfi.c               | 2 +-
 include/linux/mtd/onfi.h                       | 6 +++---
 5 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/mtd/nand/raw/cadence-nand-controller.c b/drivers/mtd/nand/raw/cadence-nand-controller.c
index b46786cd53e0..7eec60ea9056 100644
--- a/drivers/mtd/nand/raw/cadence-nand-controller.c
+++ b/drivers/mtd/nand/raw/cadence-nand-controller.c
@@ -2348,9 +2348,9 @@ cadence_nand_setup_interface(struct nand_chip *chip, int chipnr,
 	 * for tRP and tRH timings. If it is NOT possible to sample data
 	 * with optimal tRP/tRH settings, the parameters will be extended.
 	 * If clk_period is 50ns (the lowest value) this condition is met
-	 * for asynchronous timing modes 1, 2, 3, 4 and 5.
-	 * If clk_period is 20ns the condition is met only
-	 * for asynchronous timing mode 5.
+	 * for SDR timing modes 1, 2, 3, 4 and 5.
+	 * If clk_period is 20ns the condition is met only for SDR timing
+	 * mode 5.
 	 */
 	if (sdr->tRC_min <= clk_period &&
 	    sdr->tRP_min <= (clk_period / 2) &&
diff --git a/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.h b/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.h
index fdc5ed7de083..5e1c3ddae5f8 100644
--- a/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.h
+++ b/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.h
@@ -79,7 +79,7 @@ enum gpmi_type {
 struct gpmi_devdata {
 	enum gpmi_type type;
 	int bch_max_ecc_strength;
-	int max_chain_delay; /* See the async EDO mode */
+	int max_chain_delay; /* See the SDR EDO mode */
 	const char * const *clks;
 	const int clks_count;
 };
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index fb072c444495..366327ceefd9 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -935,7 +935,7 @@ int nand_choose_best_sdr_timings(struct nand_chip *chip,
 		/* Fallback to slower modes */
 		best_mode = iface->timings.mode;
 	} else if (chip->parameters.onfi) {
-		best_mode = fls(chip->parameters.onfi->async_timing_mode) - 1;
+		best_mode = fls(chip->parameters.onfi->sdr_timing_modes) - 1;
 	}
 
 	for (mode = best_mode; mode >= 0; mode--) {
diff --git a/drivers/mtd/nand/raw/nand_onfi.c b/drivers/mtd/nand/raw/nand_onfi.c
index 45649e03797d..02303455c34f 100644
--- a/drivers/mtd/nand/raw/nand_onfi.c
+++ b/drivers/mtd/nand/raw/nand_onfi.c
@@ -315,7 +315,7 @@ int nand_onfi_detect(struct nand_chip *chip)
 	onfi->tBERS = le16_to_cpu(p->t_bers);
 	onfi->tR = le16_to_cpu(p->t_r);
 	onfi->tCCS = le16_to_cpu(p->t_ccs);
-	onfi->async_timing_mode = le16_to_cpu(p->async_timing_mode);
+	onfi->sdr_timing_modes = le16_to_cpu(p->sdr_timing_modes);
 	onfi->vendor_revision = le16_to_cpu(p->vendor_revision);
 	memcpy(onfi->vendor, p->vendor, sizeof(p->vendor));
 	chip->parameters.onfi = onfi;
diff --git a/include/linux/mtd/onfi.h b/include/linux/mtd/onfi.h
index cf14474bc454..2ade5632dc5b 100644
--- a/include/linux/mtd/onfi.h
+++ b/include/linux/mtd/onfi.h
@@ -93,7 +93,7 @@ struct nand_onfi_params {
 
 	/* electrical parameter block */
 	u8 io_pin_capacitance_max;
-	__le16 async_timing_mode;
+	__le16 sdr_timing_modes;
 	__le16 program_cache_timing_mode;
 	__le16 t_prog;
 	__le16 t_bers;
@@ -160,7 +160,7 @@ struct onfi_ext_param_page {
  * @tBERS: Block erase time
  * @tR: Page read time
  * @tCCS: Change column setup time
- * @async_timing_mode: Supported asynchronous timing mode
+ * @sdr_timing_modes: Supported asynchronous/SDR timing modes
  * @vendor_revision: Vendor specific revision number
  * @vendor: Vendor specific data
  */
@@ -170,7 +170,7 @@ struct onfi_params {
 	u16 tBERS;
 	u16 tR;
 	u16 tCCS;
-	u16 async_timing_mode;
+	u16 sdr_timing_modes;
 	u16 vendor_revision;
 	u8 vendor[88];
 };
-- 
2.27.0


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  parent reply	other threads:[~2021-05-05 21:39 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-05 21:37 [PATCH 00/22] mtd: rawnand: NV-DDR support Miquel Raynal
2021-05-05 21:37 ` [PATCH 01/22] mtd: rawnand: Add a helper to clarify the interface configuration Miquel Raynal
2021-05-26  9:05   ` Miquel Raynal
2021-05-05 21:37 ` [PATCH 02/22] mtd: rawnand: arasan: Check the proposed data interface is supported Miquel Raynal
2021-05-26  9:05   ` Miquel Raynal
2021-05-05 21:37 ` [PATCH 03/22] mtd: rawnand: atmel: " Miquel Raynal
2021-05-26  9:05   ` Miquel Raynal
2021-05-05 21:37 ` [PATCH 04/22] mtd: rawnand: onfi: Use the BIT() macro when possible Miquel Raynal
2021-05-26  9:05   ` Miquel Raynal
2021-05-05 21:37 ` [PATCH 05/22] mtd: rawnand: Update dead URL Miquel Raynal
2021-05-26  9:05   ` Miquel Raynal
2021-05-05 21:37 ` Miquel Raynal [this message]
2021-05-26  9:05   ` [PATCH 06/22] mtd: rawnand: Use more recent ONFI specification wording Miquel Raynal
2021-05-05 21:37 ` [PATCH 07/22] mtd: rawnand: Clarify the NV-DDR entries in the ONFI structure Miquel Raynal
2021-05-26  9:04   ` Miquel Raynal
2021-05-05 21:37 ` [PATCH 08/22] mtd: rawnand: Add NV-DDR timings Miquel Raynal
2021-05-26  9:04   ` Miquel Raynal
2021-05-05 21:37 ` [PATCH 09/22] mtd: rawnand: Retrieve NV-DDR timing modes from the ONFI parameter page Miquel Raynal
2021-05-26  9:04   ` Miquel Raynal
2021-05-05 21:37 ` [PATCH 10/22] mtd: rawnand: Add an indirection on onfi_fill_interface_config() Miquel Raynal
2021-05-26  9:04   ` Miquel Raynal
2021-05-05 21:37 ` [PATCH 11/22] mtd: rawnand: Add onfi_fill_nvddr_interface_config() helper Miquel Raynal
2021-05-26  9:04   ` Miquel Raynal
2021-05-05 21:37 ` [PATCH 12/22] mtd: rawnand: Avoid accessing NV-DDR timings from legacy code Miquel Raynal
2021-05-26  9:04   ` Miquel Raynal
2021-05-05 21:37 ` [PATCH 13/22] mtd: rawnand: Access SDR and NV-DDR timings through a common macro Miquel Raynal
2021-05-26  9:04   ` Miquel Raynal
2021-05-05 21:37 ` [PATCH 14/22] mtd: rawnand: Handle the double bytes in NV-DDR mode Miquel Raynal
2021-05-26  9:04   ` Miquel Raynal
2021-05-05 21:37 ` [PATCH 15/22] mtd: rawnand: Add a helper to find the closest ONFI " Miquel Raynal
2021-05-26  9:04   ` Miquel Raynal
2021-05-05 21:37 ` [PATCH 16/22] mtd: rawnand: Support enabling NV-DDR through SET_FEATURES Miquel Raynal
2021-05-05 21:37 ` [PATCH 17/22] mtd: rawnand: Allow SDR timings to be nacked Miquel Raynal
2021-05-26  9:04   ` Miquel Raynal
2021-05-05 21:37 ` [PATCH 18/22] mtd: rawnand: Choose the best timings, NV-DDR included Miquel Raynal
2021-05-26  9:04   ` Miquel Raynal
2021-05-05 21:37 ` [PATCH 19/22] MAINTAINERS: Add myself as co-maintainer of the Arasan NAND controller driver Miquel Raynal
2021-05-26  9:04   ` Miquel Raynal
2021-05-05 21:37 ` [PATCH 20/22] mtd: rawnand: arasan: Fix a macro parameter Miquel Raynal
2021-05-26  9:03   ` Miquel Raynal
2021-05-05 21:37 ` [PATCH 21/22] mtd: rawnand: arasan: Workaround a misbehaving prog type with NV-DDR Miquel Raynal
2021-05-26  9:03   ` Miquel Raynal
2021-05-05 21:37 ` [PATCH 22/22] mtd: rawnand: arasan: Support NV-DDR interface Miquel Raynal
2021-05-26  9:03   ` Miquel Raynal

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