From: Pratyush Yadav <p.yadav@ti.com>
To: Tudor Ambarus <tudor.ambarus@microchip.com>,
Michael Walle <michael@walle.cc>,
Miquel Raynal <miquel.raynal@bootlin.com>,
Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>,
Mark Brown <broonie@kernel.org>, <linux-mtd@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <linux-spi@vger.kernel.org>
Cc: Pratyush Yadav <p.yadav@ti.com>
Subject: [PATCH 4/6] spi: spi-mem: reject partial cycle transfers in 8D-8D-8D mode
Date: Fri, 7 May 2021 00:48:27 +0530 [thread overview]
Message-ID: <20210506191829.8271-5-p.yadav@ti.com> (raw)
In-Reply-To: <20210506191829.8271-1-p.yadav@ti.com>
In 8D-8D-8D mode two bytes are transferred per cycle. So an odd number
of bytes cannot be transferred because it would leave a residual half
cycle at the end. Consider such a transfer invalid and reject it.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
---
This patch should go through the SPI tree but I have included it in this
series because if it goes in before patches 1-3, Micron MT35XU and
Cypress S28HS flashes will stop working correctly.
drivers/spi/spi-mem.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index 1513553e4080..ab9eefbaa1d9 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -162,7 +162,17 @@ static bool spi_mem_check_buswidth(struct spi_mem *mem,
bool spi_mem_dtr_supports_op(struct spi_mem *mem,
const struct spi_mem_op *op)
{
- if (op->cmd.nbytes != 2)
+ if (op->cmd.buswidth == 8 && op->cmd.nbytes % 2)
+ return false;
+
+ if (op->addr.nbytes && op->addr.buswidth == 8 && op->addr.nbytes % 2)
+ return false;
+
+ if (op->dummy.nbytes && op->dummy.buswidth == 8 && op->dummy.nbytes % 2)
+ return false;
+
+ if (op->data.dir != SPI_MEM_NO_DATA &&
+ op->dummy.buswidth == 8 && op->data.nbytes % 2)
return false;
return spi_mem_check_buswidth(mem, op);
--
2.30.0
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next prev parent reply other threads:[~2021-05-06 19:21 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-06 19:18 [PATCH 0/6] Avoid odd length/address read/writes in 8D-8D-8D mode Pratyush Yadav
2021-05-06 19:18 ` [PATCH 1/6] mtd: spi-nor: core: use 2 data bytes for template ops Pratyush Yadav
2021-05-06 19:18 ` [PATCH 2/6] mtd: spi-nor: spansion: write 2 bytes when disabling Octal DTR mode Pratyush Yadav
2021-05-06 19:18 ` [PATCH 3/6] mtd: spi-nor: micron-st: " Pratyush Yadav
2021-05-06 19:18 ` Pratyush Yadav [this message]
2021-05-07 12:55 ` [PATCH 4/6] spi: spi-mem: reject partial cycle transfers in 8D-8D-8D mode Mark Brown
2021-05-07 13:56 ` Pratyush Yadav
2021-05-07 15:31 ` Mark Brown
2021-05-07 15:48 ` Mark Brown
2021-05-07 16:49 ` Pratyush Yadav
2021-05-06 19:18 ` [PATCH 5/6] mtd: spi-nor: core; avoid odd length/address reads on " Pratyush Yadav
2021-05-07 15:51 ` Michael Walle
2021-05-07 18:04 ` Pratyush Yadav
2021-05-07 18:14 ` Michael Walle
2021-05-07 18:23 ` Pratyush Yadav
2021-05-06 19:18 ` [PATCH 6/6] mtd: spi-nor: core; avoid odd length/address writes in " Pratyush Yadav
2021-05-07 15:56 ` Michael Walle
2021-05-07 17:02 ` Pratyush Yadav
2021-05-07 15:50 ` [PATCH 0/6] Avoid odd length/address read/writes " Mark Brown
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