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From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Richard Weinberger <richard@nod.at>,
	Vignesh Raghavendra <vigneshr@ti.com>,
	Tudor Ambarus <Tudor.Ambarus@microchip.com>,
	<linux-mtd@lists.infradead.org>
Cc: Michal Simek <monstr@monstr.eu>,
	Naga Sureshkumar Relli <nagasure@xilinx.com>,
	Amit Kumar Mahapatra <akumarma@xilinx.com>,
	Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
	Miquel Raynal <miquel.raynal@bootlin.com>
Subject: [PATCH 1/2] mtd: rawnand: arasan: Rename the data interface register
Date: Thu, 27 May 2021 10:49:58 +0200	[thread overview]
Message-ID: <20210527084959.208804-1-miquel.raynal@bootlin.com> (raw)

There are 2 timing registers:
- "data interface"
- "timings"

So far, the "data interface" register was named "timings" which begins
misleading when bringing support for the "timings" register. Rename it
to "data_iface".

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
 drivers/mtd/nand/raw/arasan-nand-controller.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/mtd/nand/raw/arasan-nand-controller.c b/drivers/mtd/nand/raw/arasan-nand-controller.c
index 6e8d33173c6b..2bb62d193b78 100644
--- a/drivers/mtd/nand/raw/arasan-nand-controller.c
+++ b/drivers/mtd/nand/raw/arasan-nand-controller.c
@@ -144,7 +144,7 @@ struct anfc_op {
  * @rb:			Ready-busy line
  * @page_sz:		Register value of the page_sz field to use
  * @clk:		Expected clock frequency to use
- * @timings:		Data interface timing mode to use
+ * @data_iface:		Data interface timing mode to use
  * @ecc_conf:		Hardware ECC configuration value
  * @strength:		Register value of the ECC strength
  * @raddr_cycles:	Row address cycle information
@@ -164,7 +164,7 @@ struct anand {
 	unsigned int rb;
 	unsigned int page_sz;
 	unsigned long clk;
-	u32 timings;
+	u32 data_iface;
 	u32 ecc_conf;
 	u32 strength;
 	u16 raddr_cycles;
@@ -331,7 +331,7 @@ static int anfc_select_target(struct nand_chip *chip, int target)
 	anfc_assert_cs(nfc, nfc_cs_idx);
 
 	/* Update the controller timings and the potential ECC configuration */
-	writel_relaxed(anand->timings, nfc->base + DATA_INTERFACE_REG);
+	writel_relaxed(anand->data_iface, nfc->base + DATA_INTERFACE_REG);
 
 	/* Update clock frequency */
 	if (nfc->cur_clk != anand->clk) {
@@ -970,11 +970,11 @@ static int anfc_setup_interface(struct nand_chip *chip, int target,
 		return 0;
 
 	if (nand_interface_is_sdr(conf))
-		anand->timings = DIFACE_SDR |
-				 DIFACE_SDR_MODE(conf->timings.mode);
+		anand->data_iface = DIFACE_SDR |
+				    DIFACE_SDR_MODE(conf->timings.mode);
 	else
-		anand->timings = DIFACE_NVDDR |
-				 DIFACE_DDR_MODE(conf->timings.mode);
+		anand->data_iface = DIFACE_NVDDR |
+				    DIFACE_DDR_MODE(conf->timings.mode);
 
 	anand->clk = ANFC_XLNX_SDR_DFLT_CORE_CLK;
 
-- 
2.27.0


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             reply	other threads:[~2021-05-27  8:50 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-27  8:49 Miquel Raynal [this message]
2021-05-27  8:49 ` [PATCH 2/2] mtd: rawnand: arasan: Finer grain NV-DDR configuration Miquel Raynal
2021-06-11 19:03   ` Miquel Raynal
2021-06-11 19:03 ` [PATCH 1/2] mtd: rawnand: arasan: Rename the data interface register Miquel Raynal

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