From: Tudor Ambarus <tudor.ambarus@microchip.com>
To: <michael@walle.cc>, <vigneshr@ti.com>, <p.yadav@ti.com>
Cc: macromorgan@hotmail.com, jaimeliao@mxic.com.tw,
Tudor Ambarus <tudor.ambarus@microchip.com>,
richard@nod.at, esben@geanix.com, linux@rasmusvillemoes.dk,
knaerzche@gmail.com, nicolas.ferre@microchip.com,
linux-mtd@lists.infradead.org,
linux-arm-kernel@lists.infradead.org, code@reto-schneider.ch,
miquel.raynal@bootlin.com, heiko.thiery@gmail.com, sr@denx.de,
mail@david-bauer.net, zhengxunli@mxic.com.tw
Subject: [PATCH v4 04/13] mtd: spi-nor: core: Introduce flash_info mfr_flags
Date: Mon, 22 Nov 2021 11:50:11 +0200 [thread overview]
Message-ID: <20211122095020.393346-5-tudor.ambarus@microchip.com> (raw)
In-Reply-To: <20211122095020.393346-1-tudor.ambarus@microchip.com>
Used in the manufacturer fixup hooks to differentiate support
between flashes of the same manufacturer. Not used in the
SPI NOR core.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
v4: new patch
drivers/mtd/spi-nor/core.h | 10 +++++++++-
drivers/mtd/spi-nor/sst.c | 41 ++++++++++++++++++++++++++++----------
2 files changed, 40 insertions(+), 11 deletions(-)
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index f6c4b6f4743b..a9fd956eed4e 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -336,7 +336,6 @@ struct flash_info {
u32 flags;
#define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */
#define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */
-#define SST_WRITE BIT(2) /* use SST byte programming */
#define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */
#define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */
#define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */
@@ -385,6 +384,12 @@ struct flash_info {
* protection bits. Usually these will
* power-up in a write-protected state.
*/
+ u8 mfr_flags; /*
+ * Manufacturer private flags. Used in
+ * the manufacturer fixup hooks to
+ * differentiate support between flashes
+ * of the same manufacturer.
+ */
const struct spi_nor_otp_organization otp_org;
@@ -450,6 +455,9 @@ struct flash_info {
.n_regions = (_n_regions), \
},
+#define MFR_FLAGS(_mfr_flags) \
+ .mfr_flags = (_mfr_flags), \
+
/**
* struct spi_nor_manufacturer - SPI NOR manufacturer object
* @name: manufacturer name
diff --git a/drivers/mtd/spi-nor/sst.c b/drivers/mtd/spi-nor/sst.c
index 3593aae0920f..8f1ebb8fd05f 100644
--- a/drivers/mtd/spi-nor/sst.c
+++ b/drivers/mtd/spi-nor/sst.c
@@ -8,6 +8,9 @@
#include "core.h"
+/* SST flash_info mfr_flag. Used to specify SST byte programming. */
+#define SST_WRITE BIT(0)
+
#define SST26VF_CR_BPNV BIT(3)
static int sst26vf_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
@@ -58,28 +61,46 @@ static const struct spi_nor_fixups sst26vf_fixups = {
static const struct flash_info sst_parts[] = {
/* SST -- large erase sizes are "overlays", "sectors" are 4K */
{ "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8,
- SECT_4K | SST_WRITE | SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE) },
+ SECT_4K | SPI_NOR_HAS_LOCK |
+ SPI_NOR_SWP_IS_VOLATILE)
+ MFR_FLAGS(SST_WRITE) },
{ "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16,
- SECT_4K | SST_WRITE | SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE) },
+ SECT_4K | SPI_NOR_HAS_LOCK |
+ SPI_NOR_SWP_IS_VOLATILE)
+ MFR_FLAGS(SST_WRITE) },
{ "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32,
- SECT_4K | SST_WRITE | SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE) },
+ SECT_4K | SPI_NOR_HAS_LOCK |
+ SPI_NOR_SWP_IS_VOLATILE)
+ MFR_FLAGS(SST_WRITE) },
{ "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64,
- SECT_4K | SST_WRITE | SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE) },
+ SECT_4K | SPI_NOR_HAS_LOCK |
+ SPI_NOR_SWP_IS_VOLATILE)
+ MFR_FLAGS(SST_WRITE) },
{ "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128,
SECT_4K | SPI_NOR_4BIT_BP | SPI_NOR_HAS_LOCK |
SPI_NOR_SWP_IS_VOLATILE) },
{ "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1,
- SECT_4K | SST_WRITE | SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE) },
+ SECT_4K | SPI_NOR_HAS_LOCK |
+ SPI_NOR_SWP_IS_VOLATILE)
+ MFR_FLAGS(SST_WRITE) },
{ "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2,
- SECT_4K | SST_WRITE | SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE) },
+ SECT_4K | SPI_NOR_HAS_LOCK |
+ SPI_NOR_SWP_IS_VOLATILE)
+ MFR_FLAGS(SST_WRITE) },
{ "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4,
- SECT_4K | SST_WRITE | SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE) },
+ SECT_4K | SPI_NOR_HAS_LOCK |
+ SPI_NOR_SWP_IS_VOLATILE)
+ MFR_FLAGS(SST_WRITE) },
{ "sst25wf020a", INFO(0x621612, 0, 64 * 1024, 4, SECT_4K | SPI_NOR_HAS_LOCK) },
{ "sst25wf040b", INFO(0x621613, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_HAS_LOCK) },
{ "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8,
- SECT_4K | SST_WRITE | SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE) },
+ SECT_4K | SPI_NOR_HAS_LOCK |
+ SPI_NOR_SWP_IS_VOLATILE)
+ MFR_FLAGS(SST_WRITE) },
{ "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16,
- SECT_4K | SST_WRITE | SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE) },
+ SECT_4K | SPI_NOR_HAS_LOCK |
+ SPI_NOR_SWP_IS_VOLATILE)
+ MFR_FLAGS(SST_WRITE) },
{ "sst26wf016b", INFO(0xbf2651, 0, 64 * 1024, 32,
SECT_4K | SPI_NOR_DUAL_READ |
SPI_NOR_QUAD_READ) },
@@ -179,7 +200,7 @@ static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
static void sst_late_init(struct spi_nor *nor)
{
- if (nor->info->flags & SST_WRITE)
+ if (nor->info->mfr_flags & SST_WRITE)
nor->mtd._write = sst_write;
}
--
2.25.1
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next prev parent reply other threads:[~2021-11-22 10:18 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-22 9:50 [PATCH v4 00/13] mtd: spi-nor: Clean params init Tudor Ambarus
2021-11-22 9:50 ` [PATCH v4 01/13] mtd: spi-nor: core: Don't use mtd_info in the NOR's probe sequence of calls Tudor Ambarus
2021-11-22 18:28 ` Michael Walle
2021-11-30 9:56 ` Pratyush Yadav
2021-12-03 12:03 ` Tudor.Ambarus
2021-11-22 9:50 ` [PATCH v4 02/13] mtd: spi-nor: Introduce spi_nor_set_mtd_info() Tudor Ambarus
2021-12-02 9:19 ` Pratyush Yadav
2021-12-03 12:03 ` Tudor.Ambarus
2021-11-22 9:50 ` [PATCH v4 03/13] mtd: spi-nor: core: Call spi_nor_post_sfdp_fixups() only when SFDP is defined Tudor Ambarus
2021-12-02 9:31 ` Pratyush Yadav
2021-11-22 9:50 ` Tudor Ambarus [this message]
2021-11-22 18:34 ` [PATCH v4 04/13] mtd: spi-nor: core: Introduce flash_info mfr_flags Michael Walle
2021-11-23 6:43 ` Tudor.Ambarus
2021-12-02 9:32 ` Pratyush Yadav
2021-11-22 9:50 ` [PATCH v4 05/13] mtd: spi-nor: Rework the flash_info flags Tudor Ambarus
2021-12-02 10:01 ` Pratyush Yadav
2021-11-22 9:50 ` [PATCH v4 06/13] mtd: spi-nor: Introduce spi_nor_init_flags() Tudor Ambarus
2021-11-22 9:50 ` [PATCH v4 07/13] mtd: spi-nor: Introduce spi_nor_init_fixup_flags() Tudor Ambarus
2021-11-22 9:50 ` [PATCH v4 08/13] mtd: spi-nor: core: Init all flash parameters based on SFDP where possible Tudor Ambarus
2021-11-22 9:50 ` [PATCH v4 09/13] mtd: spi-nor: core: Move spi_nor_set_addr_width() in spi_nor_setup() Tudor Ambarus
2021-11-22 9:50 ` [PATCH v4 10/13] mtd: spi-nor: winbond: w25q256jvm: Init flash based on SFDP Tudor Ambarus
2021-11-22 9:50 ` [PATCH v4 11/13] mtd: spi-nor: spansion: s25fl256s0: Skip SFDP parsing Tudor Ambarus
2021-11-22 9:50 ` [PATCH v4 12/13] mtd: spi-nor: gigadevice: gd25q256: Init flash based on SFDP Tudor Ambarus
2021-11-22 18:19 ` Michael Walle
2021-11-22 9:50 ` [PATCH v4 13/13] mtd: spi-nor: issi: is25lp256: " Tudor Ambarus
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