From: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
To: <broonie@kernel.org>, <p.yadav@ti.com>,
<miquel.raynal@bootlin.com>, <richard@nod.at>, <vigneshr@ti.com>
Cc: <git@xilinx.com>, <michal.simek@xilinx.com>,
<linux-spi@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <michael@walle.cc>,
<linux-mtd@lists.infradead.org>,
Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
Subject: [RFC PATCH 0/2] spi: Add support for stacked/parallel memories
Date: Mon, 6 Jun 2022 16:56:05 +0530 [thread overview]
Message-ID: <20220606112607.20800-1-amit.kumar-mahapatra@xilinx.com> (raw)
This RFC is the continuation to the discussion which happened on
'commit f89504300e94 ("spi: Stacked/parallel memories bindings")' for
adding dtbinding support for stacked/parallel memories.
The purpose of this patch series is to demonstrate the changes in spi-nor,
spi core and ZynqMP GQSPI driver w.r.t to stacked/parallel memories
support.Please go through the series and share you comments.
To support stacked/parallel configuration following changes are done to spi
core and spi-nor.
- The chip select member (chip_select) of the spi_device structure is changed
to an array (chip_select[2]). This array is used to store the CS values coming
form the "reg" DT property.
- Added a new member (cs_index_mask) in the spi_device structure to hold the
index information of above chip_select array. SPI-NOR is not aware of the
chip_select values, For any incoming request SPI-NOR will decide the flash
index with the help of individual flash size and the configuration type
(single/stacked/parallel). SPI-NOR will pass on the flash index information
to the SPI core by setting the appropriate bit(s) of "cs_index_mask".
For example if nth bit of "cs_index_mask" is set then the driver would
assert chip_slect[n].
- The flash parameter member(*params) of the spi_nor structure is changed
to an array (*params[2]). The array is used to store the parameters of each
flash connected in stacked/parallel configuration.
This patch series targets flashes of same make connected in stacked
configuration and for parallel configuration both the flashes should be
identical.
---
BRANCH: mtd/next
---
Amit Kumar Mahapatra (2):
spi: Add multiple CS support for a single SPI device
mtd: spi-nor: Add support for stacked/parallel memories
drivers/mtd/spi-nor/core.c | 104 +++++++++++++++++++++++++++++----
drivers/mtd/spi-nor/core.h | 5 ++
drivers/spi/spi-zynqmp-gqspi.c | 30 ++++++++--
drivers/spi/spi.c | 10 +++-
include/linux/mtd/spi-nor.h | 8 ++-
include/linux/spi/spi.h | 10 +++-
6 files changed, 146 insertions(+), 21 deletions(-)
--
2.17.1
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next reply other threads:[~2022-06-06 11:27 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-06 11:26 Amit Kumar Mahapatra [this message]
2022-06-06 11:26 ` [RFC PATCH 1/2] spi: Add multiple CS support for a single SPI device Amit Kumar Mahapatra
2022-06-09 11:54 ` Mark Brown
2022-06-23 11:39 ` Mahapatra, Amit Kumar
2022-06-23 12:06 ` Mark Brown
2022-07-15 15:35 ` Mahapatra, Amit Kumar
2022-07-15 15:54 ` Mark Brown
2022-07-19 13:21 ` Mahapatra, Amit Kumar
2022-07-19 17:53 ` Mark Brown
2022-07-27 13:02 ` Mahapatra, Amit Kumar
2022-07-11 12:47 ` Michal Simek
2022-07-11 14:52 ` Mark Brown
2022-07-15 15:36 ` Mahapatra, Amit Kumar
2022-07-15 16:03 ` Mark Brown
2022-06-06 11:26 ` [RFC PATCH 2/2] mtd: spi-nor: Add support for stacked/parallel memories Amit Kumar Mahapatra
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