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From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
To: linux-mtd@lists.infradead.org, devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, tlanger@maxlinear.com,
	rtanwar@maxlinear.com, miquel.raynal@bootlin.com, richard@nod.at,
	vigneshr@ti.com,
	Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Subject: [PATCH RFC v1 2/8] dt-bindings: mtd: intel: lgm-nand: Fix maximum chip select value
Date: Tue, 28 Jun 2022 13:27:25 +0200	[thread overview]
Message-ID: <20220628112731.2041976-3-martin.blumenstingl@googlemail.com> (raw)
In-Reply-To: <20220628112731.2041976-1-martin.blumenstingl@googlemail.com>

The Intel LGM NAND IP only supports two chip selects: There's only two
CS and ADDR_SEL register sets. Fix the maximum allowed chip select value
according to the dt-bindings.

Fixes: 2f9cea8eae44f5 ("dt-bindings: mtd: Add Nand Flash Controller support for Intel LGM SoC")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml b/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml
index 763ee3e1faf3..04f26196c4c1 100644
--- a/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml
+++ b/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml
@@ -51,7 +51,7 @@ patternProperties:
     properties:
       reg:
         minimum: 0
-        maximum: 7
+        maximum: 1
 
       nand-ecc-mode: true
 
-- 
2.36.1


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  parent reply	other threads:[~2022-06-28 11:28 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-28 11:27 [PATCH RFC v1 0/8] intel-nand-controller: Fixes, cleanups and questions Martin Blumenstingl
2022-06-28 11:27 ` [PATCH RFC v1 1/8] dt-bindings: mtd: intel: lgm-nand: Fix compatible string Martin Blumenstingl
2022-06-28 13:15   ` Rob Herring
2022-06-28 11:27 ` Martin Blumenstingl [this message]
2022-06-28 11:27 ` [PATCH RFC v1 3/8] mtd: rawnand: intel: Read the chip-select line from the correct OF node Martin Blumenstingl
2022-06-28 11:27 ` [PATCH RFC v1 4/8] mtd: rawnand: intel: Remove undocumented compatible string Martin Blumenstingl
2022-06-28 11:27 ` [PATCH RFC v1 5/8] mtd: rawnand: intel: Don't re-define NAND_DATA_IFACE_CHECK_ONLY Martin Blumenstingl
2022-06-28 11:27 ` [PATCH RFC v1 6/8] mtd: rawnand: intel: Remove unused nand_pa member from ebu_nand_cs Martin Blumenstingl
2022-06-28 11:27 ` [PATCH RFC v1 7/8] mtd: rawnand: intel: Remove unused clk_rate member from struct ebu_nand Martin Blumenstingl
2022-06-28 11:27 ` [PATCH RFC v1 8/8] mtd: rawnand: intel: Use devm_platform_ioremap_resource_byname() Martin Blumenstingl
2022-06-28 14:38 ` [PATCH RFC v1 0/8] intel-nand-controller: Fixes, cleanups and questions Miquel Raynal

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