[PATCH v17 0/7] mtd: spi-nor: Add support for Infineon s25hl-t/s25hs-t

[PATCH v17 0/7] mtd: spi-nor: Add support for Infineon s25hl-t/s25hs-t

[Tudor Ambarus]

v17 introduces nor->params->addr_mode_nbytes in order to track the number
of address bytes of current address mode. This is useful when the flash
operates with 4B opcodes but needs the internal address mode for opcodes
that don't have a 4B opcode correspondent. Such an example is the Infineon
Semper chips which provide 4B opcodes for read/program/erase but do not
provide 4B opcodes for Read/Write Any Register. These registers are indexed
by address and require the internal address mode of the flash before
Read/Write Any Register opcodes are issued.
4B opcodes are preferred over changing the flash's address mode to 4byte,
as set_4byte_addr_mode could be done in a non-volatile way and could break
the boot sequence. Thus we need to track the flash's internal address mode
so that we can use the 4B opcodes together with the opcodes that don't
have a 4B opcode correspondent.
All other minor comments were addressed as well:
- s/address width/ address nbytes where needed
- "mtd: spi-nor: spansion: Add local function to discover page size" no
longer replaces the hardcoded value of 3 for the number of address bytes.
- few patches were dropped as they no longer made sense with the
introduction of nor->params->addr_mode_nbytes.

The S25HL-T/S25HS-T family is the Infineon SEMPER Flash with Quad SPI.

Previous cover letter description and the versioning of changes below:
"""
The datasheets can be found in the following link.
https://www.infineon.com/dgdl/Infineon-S25HS256T_S25HS512T_S25HS01GT_S25HL256T_S25HL512T_S25HL01GT_256-Mb_(32-MB)_512-Mb_(64-MB)_1-Gb_(128-MB)_HS-T_(1.8-V)_HL-T_(3.0-V)_Semper_Flash_with_Quad_SPI-DataSheet-v02_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ee674b86ee3&da=t

Device ID, SFDP, and test script output:
------------------------------------------------------------
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
s25hl512t
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
342a1a0f0390
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
spansion
zynq> xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
53464450080103ff00000114000100ff84000102500100ff81000116c801
00ff8700011c580100ffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffe720faffffffff1f48eb086b00ff
88bbfeffffffffff00ffffff48eb0c2000ff00ff12d823faff8b82e7ffe3
ec031c608a857a75f766805c8cd6ddfff938f8a1000000000000bc000000
0000f7f5ffff7b920ffe21ffffdc0000800000000000c0ffc3ebc8ffe3eb
00650090060500a10065009600650095716503d0716503d000000000b02e
000088a489aa716503967165039600000000000000000000000000000000
000000000000000000000000000000000000000000000000716505d57165
05d50000a015fc65ff0804008000fc65ff4002008000fd65ff0402008000
fe0002fff1ff0100f8ff0100f8fffb03fe0302fff8fffb03f8ff0100f1ff
0100fe0104fff1ff0000f8ff0200f8fff703f8ff0200f1ff0000ff0400ff
f8ffff03
zynq> md5sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
8a0aa90112e154ae3a797df2c211ef61  /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
zynq> test_qspi.sh
6+0 records in
6+0 records out
6291456 bytes (6.0MB) copied, 0.230748 seconds, 26.0MB/s
Copied 6291456 bytes from qspi_test to address 0x00000000 in flash
Erased 6291456 bytes from address 0x00000000 in flash
Copied 6291456 bytes from address 0x00000000 in flash to qspi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0600000
Copied 6291456 bytes from qspi_test to address 0x00000000 in flash
Copied 6291456 bytes from address 0x00000000 in flash to qspi_read
8fd5e1d95c3a5b8d7d66ade561f51fe5257897ff  qspi_test
8fd5e1d95c3a5b8d7d66ade561f51fe5257897ff  qspi_read
------------------------------------------------------------

------------------------------------------------------------
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
s25hs512t
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
342b1a0f0390
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
spansion
zynq> xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
53464450080103ff00000114000100ff84000102500100ff81000116c801
00ff8700011c580100ffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffe720faffffffff1f48eb086b00ff
88bbfeffffffffff00ffffff48eb0c2000ff00ff12d823faff8b91e8ffe3
ec031c608a857a75f766805c84d6ddfff938f8a100000000000080000000
0000f7f5ffff7b920ffe20ffffd80000800000000000c0ffc3ebc8ffe3eb
00650090060500a10065009600650095716503d0716503d000000000b02e
000088a489aa716503967165039600000000000000000000000000000000
000000000000000000000000000000000000000000000000716505d57165
05d50000ee72fc65ff0804008000fc65ff4002008000fd65ff0402008000
fe0002fff1ff0100f8ff0100f8fffb03fe0302fff8fffb03f8ff0100f1ff
0100fe0104fff1ff0100f8ff0200f8fff703f8ff0200f1ff0100ff0400ff
f8ffff03
zynq> md5sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
f17d9e784602187a0933edec3688e30f  /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
zynq> test_qspi.sh
6+0 records in
6+0 records out
6291456 bytes (6.0MB) copied, 0.230827 seconds, 26.0MB/s
Copied 6291456 bytes from qspi_test to address 0x00000000 in flash
Erased 6291456 bytes from address 0x00000000 in flash
Copied 6291456 bytes from address 0x00000000 in flash to qspi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0600000
Copied 6291456 bytes from qspi_test to address 0x00000000 in flash
Copied 6291456 bytes from address 0x00000000 in flash to qspi_read
3c4cc1be627a88da0364b2a866fbb6ac04dba80e  qspi_test
3c4cc1be627a88da0364b2a866fbb6ac04dba80e  qspi_read
------------------------------------------------------------

------------------------------------------------------------
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
s25hl01gt
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
342a1b0f0390
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
spansion
zynq> xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
53464450080103ff00000114000100ff84000102500100ff81000116c801
00ff8700011c580100ffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffe720faffffffff3f48eb086b00ff
88bbfeffffffffff00ffffff48eb0c2000ff00ff12d823faff8b82e7ffe6
ec031c608a857a75f766805c8cd6ddfff938f8a1000000000000bc000000
0000f7f5ffff7b920ffe21ffffdc0000800000000000c0ffc3ebc8ffe3eb
00650090060500a10065009600650095716503d0716503d000000000b02e
000088a489aa716503967165039600000000000000000000000000000000
000000000000000000000000000000000000000000000000716505d57165
05d50000a015fc65ff0804008000fc65ff4002008000fd65ff0402008000
fe0002fff1ff0100f8ff0100f8fffb07fe0302fff8fffb07f8ff0100f1ff
0100fe0104fff1ff0000f8ff0200f8fff707f8ff0200f1ff0000ff0400ff
f8ffff07
zynq> md5sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
1ad5a0d7d7e0e656986c1e678c416a7e  /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
zynq> test_qspi.sh
6+0 records in
6+0 records out
6291456 bytes (6.0MB) copied, 0.230878 seconds, 26.0MB/s
Copied 6291456 bytes from qspi_test to address 0x00000000 in flash
Erased 6291456 bytes from address 0x00000000 in flash
Copied 6291456 bytes from address 0x00000000 in flash to qspi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0600000
Copied 6291456 bytes from qspi_test to address 0x00000000 in flash
Copied 6291456 bytes from address 0x00000000 in flash to qspi_read
50b8cc948f8b05fa5650a6d0ba74be8f95ff3332  qspi_test
50b8cc948f8b05fa5650a6d0ba74be8f95ff3332  qspi_read
------------------------------------------------------------

------------------------------------------------------------
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
s25hs01gt
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
342b1b0f0390
zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
spansion
zynq> xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
53464450080103ff00000114000100ff84000102500100ff81000116c801
00ff8700011c580100ffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
ffffffffffffffffffffffffffffffffe720faffffffff3f48eb086b00ff
88bbfeffffffffff00ffffff48eb0c2000ff00ff12d823faff8b82e7ffe6
ec031c608a857a75f766805c8cd6ddfff938f8a1000000000000bc000000
0000f7f5ffff7b920ffe21ffffdc0000800000000000c0ffc3ebc8ffe3eb
00650090060500a10065009600650095716503d0716503d000000000b02e
000088a489aa716503967165039600000000000000000000000000000000
000000000000000000000000000000000000000000000000716505d57165
05d50000a015fc65ff0804008000fc65ff4002008000fd65ff0402008000
fe0002fff1ff0100f8ff0100f8fffb07fe0302fff8fffb07f8ff0100f1ff
0100fe0104fff1ff0000f8ff0200f8fff707f8ff0200f1ff0000ff0400ff
f8ffff07
zynq> md5sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
1ad5a0d7d7e0e656986c1e678c416a7e  /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
zynq> test_qspi.sh
6+0 records in
6+0 records out
6291456 bytes (6.0MB) copied, 0.230712 seconds, 26.0MB/s
Copied 6291456 bytes from qspi_test to address 0x00000000 in flash
Erased 6291456 bytes from address 0x00000000 in flash
Copied 6291456 bytes from address 0x00000000 in flash to qspi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0600000
Copied 6291456 bytes from qspi_test to address 0x00000000 in flash
Copied 6291456 bytes from address 0x00000000 in flash to qspi_read
e9515a880d836d9fdfa8b2b7c870825fd8300cc1  qspi_test
e9515a880d836d9fdfa8b2b7c870825fd8300cc1  qspi_read
------------------------------------------------------------

Changes in v16:
  - stop restoring read_opcode, read_dummy and addr_nbytes to uninitialized
    state at SFDP parsing time

Changes in v15:
  - add missing read any reg call in volatile quad enable method (patch 8/8)

Changes in v14:
  - add prerequisite patches for s25hl-t/s25hs-t addition.
  - squash volatile quad enable method to the patch that adds the flashes
    to avoid unused function warning.

Changes in v13:
  - Remove patch, Call set_4byte_addr_mode() before spi_nor_quad_enalbe()
  - Remove patch, Rename local macro
  - Use 3-byte address width in cypress_nor_quad_enable_volatile()
  - Add post_sfdp to fix 3 byte erase opcode in 4BAIT

Changes in v12:
  - Rebase on top of Tudor's series
    https://patchwork.ozlabs.org/project/linux-mtd/list/?series=295933
    https://patchwork.ozlabs.org/project/linux-mtd/list/?series=294533
  - New patch: Retain nor->addr_width at 4BAIT parse
  - New patch: Call set_4byte_addr_mode() before spi_nor_quad_enalbe()
  - New patch: Rename local macro

Changes in v11:
  - Rebase on top of Tudor's series
    https://patchwork.ozlabs.org/project/linux-mtd/list/?series=294490
  - Remove 'nor->info->addr_width for SMPT parse' patch

Changes in v10:
  - Rebase to v5.18-rc1
  - Remove dependencies on other series
  - Use nor->info->addr_width for SMPT parse
  - Add a local function for page size discovery
  - Clean up volatile QE function

Changes in v9:
  - Rebase to v5.17-rc6
  - Rename function and macro per mwalle's series
  - Fix some issues in ID table and fixup hook

Changes in v8:
  - Rebase to v5.17-rc4
  - Use spi_nor_read_reg and spi_nor_write_reg()

Changes in v7:
  - Some changes were missing in v6 patch. Fix it

Changes in v6:
  - Remove 2Gb dual die package parts and related changes to split mulit
    die package support into another series of patches

Changes in v5:
  - Fix 'if (ret == 1)' to 'if (ret < 0)' in spansion_read_any_reg()
  - Add NO_CHIP_ERASE flag to S25HL02GT and S25HS02GT

Changes in v4:
  - Reword 'legacy' to 'default'
  - Rename spi_nor_read() to spi_nor_default_ready()
  - Fix dummy cycle calculation in spansion_read_any_reg()
  - Modify comment for spansion_write_any_reg()
  - Merge block comments about SMPT in s25hx_t_post_sfdp_fixups()
  - Remove USE_CLSR flags from S25HL02GT and S25HS02GT

Changes in v3:
  - Split into multiple patches
  - Remove S25HL256T and S25HS256T
  - Add S25HL02GT and S25HS02GT
  - Add support for multi-die package parts support
  - Cleanup Read/Write Any Register implementation
  - Remove erase_map fix for top/split sector layout
  - Set ECC data unit size (16B) to writesize

Changes in v2:
  - Remove SPI_NOR_SKIP_SFDP flag and clean up related fixups
  - Check CFR3V[4] to determine page_size instead of force 512B
  - Depend on the patchset below to support non-uniform sector layout
    https://lore.kernel.org/linux-mtd/cover.1601612872.git.Takahiro.Kuwano@infineon.com
"""

Takahiro Kuwano (3):
  mtd: spi-nor: core: Return error code from set_4byte_addr_mode()
  mtd: spi-nor: spansion: Add local function to discover page size
  mtd: spi-nor: spansion: Add s25hl-t/s25hs-t IDs and fixups

Tudor Ambarus (4):
  mtd: spi-nor: s/addr_width/addr_nbytes
  mtd: spi-nor: core: Shrink the storage size of the flash_info's
    addr_nbytes
  mtd: spi-nor: Do not change nor->addr_nbytes at SFDP parsing time
  mtd: spi-nor: core: Track flash's internal address mode

 drivers/mtd/spi-nor/controllers/hisi-sfc.c  |   2 +-
 drivers/mtd/spi-nor/controllers/nxp-spifi.c |   8 +-
 drivers/mtd/spi-nor/core.c                  |  57 +++---
 drivers/mtd/spi-nor/core.h                  |  19 +-
 drivers/mtd/spi-nor/debugfs.c               |   2 +-
 drivers/mtd/spi-nor/issi.c                  |   8 +-
 drivers/mtd/spi-nor/otp.c                   |  12 +-
 drivers/mtd/spi-nor/sfdp.c                  |  32 ++--
 drivers/mtd/spi-nor/spansion.c              | 185 +++++++++++++++++---
 drivers/mtd/spi-nor/xilinx.c                |   2 +-
 include/linux/mtd/spi-nor.h                 |   4 +-
 11 files changed, 239 insertions(+), 92 deletions(-)

-- 
2.25.1


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

[PATCH v17 1/7] mtd: spi-nor: s/addr_width/addr_nbytes

[Tudor Ambarus]

Address width was an unfortunate name, as it means the number of IO lines
used for the address, whereas in the code it is used as the number of
address bytes. s/addr_width/addr_nbytes throughout the entire SPI NOR
framework.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Michael Walle <michael@walle.cc>
Acked-by: Pratyush Yadav <p.yadav@ti.com>
---
 drivers/mtd/spi-nor/controllers/hisi-sfc.c  |  2 +-
 drivers/mtd/spi-nor/controllers/nxp-spifi.c |  8 +--
 drivers/mtd/spi-nor/core.c                  | 54 ++++++++++-----------
 drivers/mtd/spi-nor/core.h                  | 12 ++---
 drivers/mtd/spi-nor/debugfs.c               |  2 +-
 drivers/mtd/spi-nor/issi.c                  |  8 +--
 drivers/mtd/spi-nor/otp.c                   | 12 ++---
 drivers/mtd/spi-nor/sfdp.c                  | 32 ++++++------
 drivers/mtd/spi-nor/xilinx.c                |  2 +-
 include/linux/mtd/spi-nor.h                 |  4 +-
 10 files changed, 68 insertions(+), 68 deletions(-)

diff --git a/drivers/mtd/spi-nor/controllers/hisi-sfc.c b/drivers/mtd/spi-nor/controllers/hisi-sfc.c
index 94a969185ceb..5070d72835ec 100644
--- a/drivers/mtd/spi-nor/controllers/hisi-sfc.c
+++ b/drivers/mtd/spi-nor/controllers/hisi-sfc.c
@@ -237,7 +237,7 @@ static int hisi_spi_nor_dma_transfer(struct spi_nor *nor, loff_t start_off,
 	reg = readl(host->regbase + FMC_CFG);
 	reg &= ~(FMC_CFG_OP_MODE_MASK | SPI_NOR_ADDR_MODE_MASK);
 	reg |= FMC_CFG_OP_MODE_NORMAL;
-	reg |= (nor->addr_width == 4) ? SPI_NOR_ADDR_MODE_4BYTES
+	reg |= (nor->addr_nbytes == 4) ? SPI_NOR_ADDR_MODE_4BYTES
 		: SPI_NOR_ADDR_MODE_3BYTES;
 	writel(reg, host->regbase + FMC_CFG);
 
diff --git a/drivers/mtd/spi-nor/controllers/nxp-spifi.c b/drivers/mtd/spi-nor/controllers/nxp-spifi.c
index 9032b9ab2eaf..ab3990e6ac25 100644
--- a/drivers/mtd/spi-nor/controllers/nxp-spifi.c
+++ b/drivers/mtd/spi-nor/controllers/nxp-spifi.c
@@ -203,7 +203,7 @@ static ssize_t nxp_spifi_write(struct spi_nor *nor, loff_t to, size_t len,
 	      SPIFI_CMD_DATALEN(len) |
 	      SPIFI_CMD_FIELDFORM_ALL_SERIAL |
 	      SPIFI_CMD_OPCODE(nor->program_opcode) |
-	      SPIFI_CMD_FRAMEFORM(spifi->nor.addr_width + 1);
+	      SPIFI_CMD_FRAMEFORM(spifi->nor.addr_nbytes + 1);
 	writel(cmd, spifi->io_base + SPIFI_CMD);
 
 	for (i = 0; i < len; i++)
@@ -230,7 +230,7 @@ static int nxp_spifi_erase(struct spi_nor *nor, loff_t offs)
 
 	cmd = SPIFI_CMD_FIELDFORM_ALL_SERIAL |
 	      SPIFI_CMD_OPCODE(nor->erase_opcode) |
-	      SPIFI_CMD_FRAMEFORM(spifi->nor.addr_width + 1);
+	      SPIFI_CMD_FRAMEFORM(spifi->nor.addr_nbytes + 1);
 	writel(cmd, spifi->io_base + SPIFI_CMD);
 
 	return nxp_spifi_wait_for_cmd(spifi);
@@ -252,12 +252,12 @@ static int nxp_spifi_setup_memory_cmd(struct nxp_spifi *spifi)
 	}
 
 	/* Memory mode supports address length between 1 and 4 */
-	if (spifi->nor.addr_width < 1 || spifi->nor.addr_width > 4)
+	if (spifi->nor.addr_nbytes < 1 || spifi->nor.addr_nbytes > 4)
 		return -EINVAL;
 
 	spifi->mcmd |= SPIFI_CMD_OPCODE(spifi->nor.read_opcode) |
 		       SPIFI_CMD_INTLEN(spifi->nor.read_dummy / 8) |
-		       SPIFI_CMD_FRAMEFORM(spifi->nor.addr_width + 1);
+		       SPIFI_CMD_FRAMEFORM(spifi->nor.addr_nbytes + 1);
 
 	return 0;
 }
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index ce5d69317d46..31604188ee59 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -38,7 +38,7 @@
  */
 #define CHIP_ERASE_2MB_READY_WAIT_JIFFIES	(40UL * HZ)
 
-#define SPI_NOR_MAX_ADDR_WIDTH	4
+#define SPI_NOR_MAX_ADDR_NBYTES	4
 
 #define SPI_NOR_SRST_SLEEP_MIN 200
 #define SPI_NOR_SRST_SLEEP_MAX 400
@@ -198,7 +198,7 @@ static ssize_t spi_nor_spimem_read_data(struct spi_nor *nor, loff_t from,
 {
 	struct spi_mem_op op =
 		SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0),
-			   SPI_MEM_OP_ADDR(nor->addr_width, from, 0),
+			   SPI_MEM_OP_ADDR(nor->addr_nbytes, from, 0),
 			   SPI_MEM_OP_DUMMY(nor->read_dummy, 0),
 			   SPI_MEM_OP_DATA_IN(len, buf, 0));
 	bool usebouncebuf;
@@ -262,7 +262,7 @@ static ssize_t spi_nor_spimem_write_data(struct spi_nor *nor, loff_t to,
 {
 	struct spi_mem_op op =
 		SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 0),
-			   SPI_MEM_OP_ADDR(nor->addr_width, to, 0),
+			   SPI_MEM_OP_ADDR(nor->addr_nbytes, to, 0),
 			   SPI_MEM_OP_NO_DUMMY,
 			   SPI_MEM_OP_DATA_OUT(len, buf, 0));
 	ssize_t nbytes;
@@ -1113,7 +1113,7 @@ int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
 	if (nor->spimem) {
 		struct spi_mem_op op =
 			SPI_NOR_SECTOR_ERASE_OP(nor->erase_opcode,
-						nor->addr_width, addr);
+						nor->addr_nbytes, addr);
 
 		spi_nor_spimem_setup_op(nor, &op, nor->write_proto);
 
@@ -1126,13 +1126,13 @@ int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
 	 * Default implementation, if driver doesn't have a specialized HW
 	 * control
 	 */
-	for (i = nor->addr_width - 1; i >= 0; i--) {
+	for (i = nor->addr_nbytes - 1; i >= 0; i--) {
 		nor->bouncebuf[i] = addr & 0xff;
 		addr >>= 8;
 	}
 
 	return spi_nor_controller_ops_write_reg(nor, nor->erase_opcode,
-						nor->bouncebuf, nor->addr_width);
+						nor->bouncebuf, nor->addr_nbytes);
 }
 
 /**
@@ -2249,43 +2249,43 @@ static int spi_nor_default_setup(struct spi_nor *nor,
 	return 0;
 }
 
-static int spi_nor_set_addr_width(struct spi_nor *nor)
+static int spi_nor_set_addr_nbytes(struct spi_nor *nor)
 {
-	if (nor->addr_width) {
+	if (nor->addr_nbytes) {
 		/* already configured from SFDP */
 	} else if (nor->read_proto == SNOR_PROTO_8_8_8_DTR) {
 		/*
 		 * In 8D-8D-8D mode, one byte takes half a cycle to transfer. So
-		 * in this protocol an odd address width cannot be used because
+		 * in this protocol an odd addr_nbytes cannot be used because
 		 * then the address phase would only span a cycle and a half.
 		 * Half a cycle would be left over. We would then have to start
 		 * the dummy phase in the middle of a cycle and so too the data
 		 * phase, and we will end the transaction with half a cycle left
 		 * over.
 		 *
-		 * Force all 8D-8D-8D flashes to use an address width of 4 to
+		 * Force all 8D-8D-8D flashes to use an addr_nbytes of 4 to
 		 * avoid this situation.
 		 */
-		nor->addr_width = 4;
-	} else if (nor->info->addr_width) {
-		nor->addr_width = nor->info->addr_width;
+		nor->addr_nbytes = 4;
+	} else if (nor->info->addr_nbytes) {
+		nor->addr_nbytes = nor->info->addr_nbytes;
 	} else {
-		nor->addr_width = 3;
+		nor->addr_nbytes = 3;
 	}
 
-	if (nor->addr_width == 3 && nor->params->size > 0x1000000) {
+	if (nor->addr_nbytes == 3 && nor->params->size > 0x1000000) {
 		/* enable 4-byte addressing if the device exceeds 16MiB */
-		nor->addr_width = 4;
+		nor->addr_nbytes = 4;
 	}
 
-	if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
-		dev_dbg(nor->dev, "address width is too large: %u\n",
-			nor->addr_width);
+	if (nor->addr_nbytes > SPI_NOR_MAX_ADDR_NBYTES) {
+		dev_dbg(nor->dev, "The number of address bytes is too large: %u\n",
+			nor->addr_nbytes);
 		return -EINVAL;
 	}
 
 	/* Set 4byte opcodes when possible. */
-	if (nor->addr_width == 4 && nor->flags & SNOR_F_4B_OPCODES &&
+	if (nor->addr_nbytes == 4 && nor->flags & SNOR_F_4B_OPCODES &&
 	    !(nor->flags & SNOR_F_HAS_4BAIT))
 		spi_nor_set_4byte_opcodes(nor);
 
@@ -2304,7 +2304,7 @@ static int spi_nor_setup(struct spi_nor *nor,
 	if (ret)
 		return ret;
 
-	return spi_nor_set_addr_width(nor);
+	return spi_nor_set_addr_nbytes(nor);
 }
 
 /**
@@ -2492,7 +2492,7 @@ static void spi_nor_sfdp_init_params_deprecated(struct spi_nor *nor)
 
 	if (spi_nor_parse_sfdp(nor)) {
 		memcpy(nor->params, &sfdp_params, sizeof(*nor->params));
-		nor->addr_width = 0;
+		nor->addr_nbytes = 0;
 		nor->flags &= ~SNOR_F_4B_OPCODES;
 	}
 }
@@ -2713,7 +2713,7 @@ static int spi_nor_init(struct spi_nor *nor)
 	     nor->flags & SNOR_F_SWP_IS_VOLATILE))
 		spi_nor_try_unlock_all(nor);
 
-	if (nor->addr_width == 4 &&
+	if (nor->addr_nbytes == 4 &&
 	    nor->read_proto != SNOR_PROTO_8_8_8_DTR &&
 	    !(nor->flags & SNOR_F_4B_OPCODES)) {
 		/*
@@ -2840,7 +2840,7 @@ static void spi_nor_put_device(struct mtd_info *mtd)
 void spi_nor_restore(struct spi_nor *nor)
 {
 	/* restore the addressing mode */
-	if (nor->addr_width == 4 && !(nor->flags & SNOR_F_4B_OPCODES) &&
+	if (nor->addr_nbytes == 4 && !(nor->flags & SNOR_F_4B_OPCODES) &&
 	    nor->flags & SNOR_F_BROKEN_RESET)
 		nor->params->set_4byte_addr_mode(nor, false);
 
@@ -2984,7 +2984,7 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
 	 * - select op codes for (Fast) Read, Page Program and Sector Erase.
 	 * - set the number of dummy cycles (mode cycles + wait states).
 	 * - set the SPI protocols for register and memory accesses.
-	 * - set the address width.
+	 * - set the number of address bytes.
 	 */
 	ret = spi_nor_setup(nor, hwcaps);
 	if (ret)
@@ -3025,7 +3025,7 @@ static int spi_nor_create_read_dirmap(struct spi_nor *nor)
 {
 	struct spi_mem_dirmap_info info = {
 		.op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0),
-				      SPI_MEM_OP_ADDR(nor->addr_width, 0, 0),
+				      SPI_MEM_OP_ADDR(nor->addr_nbytes, 0, 0),
 				      SPI_MEM_OP_DUMMY(nor->read_dummy, 0),
 				      SPI_MEM_OP_DATA_IN(0, NULL, 0)),
 		.offset = 0,
@@ -3056,7 +3056,7 @@ static int spi_nor_create_write_dirmap(struct spi_nor *nor)
 {
 	struct spi_mem_dirmap_info info = {
 		.op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 0),
-				      SPI_MEM_OP_ADDR(nor->addr_width, 0, 0),
+				      SPI_MEM_OP_ADDR(nor->addr_nbytes, 0, 0),
 				      SPI_MEM_OP_NO_DUMMY,
 				      SPI_MEM_OP_DATA_OUT(0, NULL, 0)),
 		.offset = 0,
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index 61886868cd02..14921a507b0f 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -84,9 +84,9 @@
 		   SPI_MEM_OP_NO_DUMMY,					\
 		   SPI_MEM_OP_NO_DATA)
 
-#define SPI_NOR_SECTOR_ERASE_OP(opcode, addr_width, addr)		\
+#define SPI_NOR_SECTOR_ERASE_OP(opcode, addr_nbytes, addr)		\
 	SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0),				\
-		   SPI_MEM_OP_ADDR(addr_width, addr, 0),		\
+		   SPI_MEM_OP_ADDR(addr_nbytes, addr, 0),		\
 		   SPI_MEM_OP_NO_DUMMY,					\
 		   SPI_MEM_OP_NO_DATA)
 
@@ -429,7 +429,7 @@ struct spi_nor_fixups {
  *                  isn't necessarily called a "sector" by the vendor.
  * @n_sectors:      the number of sectors.
  * @page_size:      the flash's page size.
- * @addr_width:     the flash's address width.
+ * @addr_nbytes:    number of address bytes to send.
  *
  * @parse_sfdp:     true when flash supports SFDP tables. The false value has no
  *                  meaning. If one wants to skip the SFDP tables, one should
@@ -487,7 +487,7 @@ struct flash_info {
 	unsigned sector_size;
 	u16 n_sectors;
 	u16 page_size;
-	u16 addr_width;
+	u16 addr_nbytes;
 
 	bool parse_sfdp;
 	u16 flags;
@@ -548,11 +548,11 @@ struct flash_info {
 		.n_sectors = (_n_sectors),				\
 		.page_size = 256,					\
 
-#define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width)	\
+#define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_nbytes)	\
 		.sector_size = (_sector_size),				\
 		.n_sectors = (_n_sectors),				\
 		.page_size = (_page_size),				\
-		.addr_width = (_addr_width),				\
+		.addr_nbytes = (_addr_nbytes),				\
 		.flags = SPI_NOR_NO_ERASE | SPI_NOR_NO_FR,		\
 
 #define OTP_INFO(_len, _n_regions, _base, _offset)			\
diff --git a/drivers/mtd/spi-nor/debugfs.c b/drivers/mtd/spi-nor/debugfs.c
index eaf84f7a0676..df76cb5de3f9 100644
--- a/drivers/mtd/spi-nor/debugfs.c
+++ b/drivers/mtd/spi-nor/debugfs.c
@@ -86,7 +86,7 @@ static int spi_nor_params_show(struct seq_file *s, void *data)
 	seq_printf(s, "size\t\t%s\n", buf);
 	seq_printf(s, "write size\t%u\n", params->writesize);
 	seq_printf(s, "page size\t%u\n", params->page_size);
-	seq_printf(s, "address width\t%u\n", nor->addr_width);
+	seq_printf(s, "address nbytes\t%u\n", nor->addr_nbytes);
 
 	seq_puts(s, "flags\t\t");
 	spi_nor_print_flags(s, nor->flags, snor_f_names, sizeof(snor_f_names));
diff --git a/drivers/mtd/spi-nor/issi.c b/drivers/mtd/spi-nor/issi.c
index 3c7d51d2b050..71687e5babdc 100644
--- a/drivers/mtd/spi-nor/issi.c
+++ b/drivers/mtd/spi-nor/issi.c
@@ -14,13 +14,13 @@ is25lp256_post_bfpt_fixups(struct spi_nor *nor,
 			   const struct sfdp_bfpt *bfpt)
 {
 	/*
-	 * IS25LP256 supports 4B opcodes, but the BFPT advertises a
-	 * BFPT_DWORD1_ADDRESS_BYTES_3_ONLY address width.
-	 * Overwrite the address width advertised by the BFPT.
+	 * IS25LP256 supports 4B opcodes, but the BFPT advertises
+	 * BFPT_DWORD1_ADDRESS_BYTES_3_ONLY.
+	 * Overwrite the number of address bytes advertised by the BFPT.
 	 */
 	if ((bfpt->dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) ==
 		BFPT_DWORD1_ADDRESS_BYTES_3_ONLY)
-		nor->addr_width = 4;
+		nor->addr_nbytes = 4;
 
 	return 0;
 }
diff --git a/drivers/mtd/spi-nor/otp.c b/drivers/mtd/spi-nor/otp.c
index fa63d8571218..00ab0d2d6d2f 100644
--- a/drivers/mtd/spi-nor/otp.c
+++ b/drivers/mtd/spi-nor/otp.c
@@ -35,13 +35,13 @@
  */
 int spi_nor_otp_read_secr(struct spi_nor *nor, loff_t addr, size_t len, u8 *buf)
 {
-	u8 addr_width, read_opcode, read_dummy;
+	u8 addr_nbytes, read_opcode, read_dummy;
 	struct spi_mem_dirmap_desc *rdesc;
 	enum spi_nor_protocol read_proto;
 	int ret;
 
 	read_opcode = nor->read_opcode;
-	addr_width = nor->addr_width;
+	addr_nbytes = nor->addr_nbytes;
 	read_dummy = nor->read_dummy;
 	read_proto = nor->read_proto;
 	rdesc = nor->dirmap.rdesc;
@@ -54,7 +54,7 @@ int spi_nor_otp_read_secr(struct spi_nor *nor, loff_t addr, size_t len, u8 *buf)
 	ret = spi_nor_read_data(nor, addr, len, buf);
 
 	nor->read_opcode = read_opcode;
-	nor->addr_width = addr_width;
+	nor->addr_nbytes = addr_nbytes;
 	nor->read_dummy = read_dummy;
 	nor->read_proto = read_proto;
 	nor->dirmap.rdesc = rdesc;
@@ -85,11 +85,11 @@ int spi_nor_otp_write_secr(struct spi_nor *nor, loff_t addr, size_t len,
 {
 	enum spi_nor_protocol write_proto;
 	struct spi_mem_dirmap_desc *wdesc;
-	u8 addr_width, program_opcode;
+	u8 addr_nbytes, program_opcode;
 	int ret, written;
 
 	program_opcode = nor->program_opcode;
-	addr_width = nor->addr_width;
+	addr_nbytes = nor->addr_nbytes;
 	write_proto = nor->write_proto;
 	wdesc = nor->dirmap.wdesc;
 
@@ -113,7 +113,7 @@ int spi_nor_otp_write_secr(struct spi_nor *nor, loff_t addr, size_t len,
 
 out:
 	nor->program_opcode = program_opcode;
-	nor->addr_width = addr_width;
+	nor->addr_nbytes = addr_nbytes;
 	nor->write_proto = write_proto;
 	nor->dirmap.wdesc = wdesc;
 
diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c
index a5211543d30d..61ae8c8c5237 100644
--- a/drivers/mtd/spi-nor/sfdp.c
+++ b/drivers/mtd/spi-nor/sfdp.c
@@ -134,7 +134,7 @@ struct sfdp_4bait {
 
 /**
  * spi_nor_read_raw() - raw read of serial flash memory. read_opcode,
- *			addr_width and read_dummy members of the struct spi_nor
+ *			addr_nbytes and read_dummy members of the struct spi_nor
  *			should be previously
  * set.
  * @nor:	pointer to a 'struct spi_nor'
@@ -178,21 +178,21 @@ static int spi_nor_read_raw(struct spi_nor *nor, u32 addr, size_t len, u8 *buf)
 static int spi_nor_read_sfdp(struct spi_nor *nor, u32 addr,
 			     size_t len, void *buf)
 {
-	u8 addr_width, read_opcode, read_dummy;
+	u8 addr_nbytes, read_opcode, read_dummy;
 	int ret;
 
 	read_opcode = nor->read_opcode;
-	addr_width = nor->addr_width;
+	addr_nbytes = nor->addr_nbytes;
 	read_dummy = nor->read_dummy;
 
 	nor->read_opcode = SPINOR_OP_RDSFDP;
-	nor->addr_width = 3;
+	nor->addr_nbytes = 3;
 	nor->read_dummy = 8;
 
 	ret = spi_nor_read_raw(nor, addr, len, buf);
 
 	nor->read_opcode = read_opcode;
-	nor->addr_width = addr_width;
+	nor->addr_nbytes = addr_nbytes;
 	nor->read_dummy = read_dummy;
 
 	return ret;
@@ -462,11 +462,11 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
 	switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) {
 	case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY:
 	case BFPT_DWORD1_ADDRESS_BYTES_3_OR_4:
-		nor->addr_width = 3;
+		nor->addr_nbytes = 3;
 		break;
 
 	case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY:
-		nor->addr_width = 4;
+		nor->addr_nbytes = 4;
 		break;
 
 	default:
@@ -637,12 +637,12 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
 }
 
 /**
- * spi_nor_smpt_addr_width() - return the address width used in the
+ * spi_nor_smpt_addr_nbytes() - return the number of address bytes used in the
  *			       configuration detection command.
  * @nor:	pointer to a 'struct spi_nor'
  * @settings:	configuration detection command descriptor, dword1
  */
-static u8 spi_nor_smpt_addr_width(const struct spi_nor *nor, const u32 settings)
+static u8 spi_nor_smpt_addr_nbytes(const struct spi_nor *nor, const u32 settings)
 {
 	switch (settings & SMPT_CMD_ADDRESS_LEN_MASK) {
 	case SMPT_CMD_ADDRESS_LEN_0:
@@ -653,7 +653,7 @@ static u8 spi_nor_smpt_addr_width(const struct spi_nor *nor, const u32 settings)
 		return 4;
 	case SMPT_CMD_ADDRESS_LEN_USE_CURRENT:
 	default:
-		return nor->addr_width;
+		return nor->addr_nbytes;
 	}
 }
 
@@ -690,7 +690,7 @@ static const u32 *spi_nor_get_map_in_use(struct spi_nor *nor, const u32 *smpt,
 	u32 addr;
 	int err;
 	u8 i;
-	u8 addr_width, read_opcode, read_dummy;
+	u8 addr_nbytes, read_opcode, read_dummy;
 	u8 read_data_mask, map_id;
 
 	/* Use a kmalloc'ed bounce buffer to guarantee it is DMA-able. */
@@ -698,7 +698,7 @@ static const u32 *spi_nor_get_map_in_use(struct spi_nor *nor, const u32 *smpt,
 	if (!buf)
 		return ERR_PTR(-ENOMEM);
 
-	addr_width = nor->addr_width;
+	addr_nbytes = nor->addr_nbytes;
 	read_dummy = nor->read_dummy;
 	read_opcode = nor->read_opcode;
 
@@ -709,7 +709,7 @@ static const u32 *spi_nor_get_map_in_use(struct spi_nor *nor, const u32 *smpt,
 			break;
 
 		read_data_mask = SMPT_CMD_READ_DATA(smpt[i]);
-		nor->addr_width = spi_nor_smpt_addr_width(nor, smpt[i]);
+		nor->addr_nbytes = spi_nor_smpt_addr_nbytes(nor, smpt[i]);
 		nor->read_dummy = spi_nor_smpt_read_dummy(nor, smpt[i]);
 		nor->read_opcode = SMPT_CMD_OPCODE(smpt[i]);
 		addr = smpt[i + 1];
@@ -756,7 +756,7 @@ static const u32 *spi_nor_get_map_in_use(struct spi_nor *nor, const u32 *smpt,
 	/* fall through */
 out:
 	kfree(buf);
-	nor->addr_width = addr_width;
+	nor->addr_nbytes = addr_nbytes;
 	nor->read_dummy = read_dummy;
 	nor->read_opcode = read_opcode;
 	return ret;
@@ -1044,7 +1044,7 @@ static int spi_nor_parse_4bait(struct spi_nor *nor,
 	/*
 	 * We need at least one 4-byte op code per read, program and erase
 	 * operation; the .read(), .write() and .erase() hooks share the
-	 * nor->addr_width value.
+	 * nor->addr_nbytes value.
 	 */
 	if (!read_hwcaps || !pp_hwcaps || !erase_mask)
 		goto out;
@@ -1098,7 +1098,7 @@ static int spi_nor_parse_4bait(struct spi_nor *nor,
 	 * Spansion memory. However this quirk is no longer needed with new
 	 * SFDP compliant memories.
 	 */
-	nor->addr_width = 4;
+	nor->addr_nbytes = 4;
 	nor->flags |= SNOR_F_4B_OPCODES | SNOR_F_HAS_4BAIT;
 
 	/* fall through */
diff --git a/drivers/mtd/spi-nor/xilinx.c b/drivers/mtd/spi-nor/xilinx.c
index 1d2f5db047bd..5723157739fc 100644
--- a/drivers/mtd/spi-nor/xilinx.c
+++ b/drivers/mtd/spi-nor/xilinx.c
@@ -31,7 +31,7 @@
 		.sector_size = (8 * (_page_size)),			\
 		.n_sectors = (_n_sectors),				\
 		.page_size = (_page_size),				\
-		.addr_width = 3,					\
+		.addr_nbytes = 3,					\
 		.flags = SPI_NOR_NO_FR
 
 /* Xilinx S3AN share MFR with Atmel SPI NOR */
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 1ede4c89805a..42218a1164f6 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -351,7 +351,7 @@ struct spi_nor_flash_parameter;
  * @bouncebuf_size:	size of the bounce buffer
  * @info:		SPI NOR part JEDEC MFR ID and other info
  * @manufacturer:	SPI NOR manufacturer
- * @addr_width:		number of address bytes
+ * @addr_nbytes:	number of address bytes
  * @erase_opcode:	the opcode for erasing a sector
  * @read_opcode:	the read opcode
  * @read_dummy:		the dummy needed by the read operation
@@ -381,7 +381,7 @@ struct spi_nor {
 	size_t			bouncebuf_size;
 	const struct flash_info	*info;
 	const struct spi_nor_manufacturer *manufacturer;
-	u8			addr_width;
+	u8			addr_nbytes;
 	u8			erase_opcode;
 	u8			read_opcode;
 	u8			read_dummy;
-- 
2.25.1


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

[PATCH v17 2/7] mtd: spi-nor: core: Shrink the storage size of the flash_info's addr_nbytes

[Tudor Ambarus]

The maximum number of address bytes in SPI NOR is 4. Shrink the storage
size of the flash_info's addr_nbytes.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Michael Walle <michael@walle.cc>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
---
 drivers/mtd/spi-nor/core.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index 14921a507b0f..19a692e27c92 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -487,7 +487,7 @@ struct flash_info {
 	unsigned sector_size;
 	u16 n_sectors;
 	u16 page_size;
-	u16 addr_nbytes;
+	u8 addr_nbytes;
 
 	bool parse_sfdp;
 	u16 flags;
-- 
2.25.1


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

[PATCH v17 3/7] mtd: spi-nor: Do not change nor->addr_nbytes at SFDP parsing time

[Tudor Ambarus]

At the SFDP parsing time we should not change members of struct spi_nor,
but instead fill members of struct spi_nor_flash_parameters which could
later on be used by callers. The caller will then decide if SFDP params
should be used and more importantly when they should be used. Clean the
code flow and don't initialize nor->addr_nbytes at SFDP parsing time.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Tested-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Michael Walle <michael@walle.cc>
---
 drivers/mtd/spi-nor/core.c | 5 ++---
 drivers/mtd/spi-nor/core.h | 2 ++
 drivers/mtd/spi-nor/issi.c | 2 +-
 drivers/mtd/spi-nor/sfdp.c | 8 ++++----
 4 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 31604188ee59..9f07f1036151 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -2251,8 +2251,8 @@ static int spi_nor_default_setup(struct spi_nor *nor,
 
 static int spi_nor_set_addr_nbytes(struct spi_nor *nor)
 {
-	if (nor->addr_nbytes) {
-		/* already configured from SFDP */
+	if (nor->params->addr_nbytes) {
+		nor->addr_nbytes = nor->params->addr_nbytes;
 	} else if (nor->read_proto == SNOR_PROTO_8_8_8_DTR) {
 		/*
 		 * In 8D-8D-8D mode, one byte takes half a cycle to transfer. So
@@ -2492,7 +2492,6 @@ static void spi_nor_sfdp_init_params_deprecated(struct spi_nor *nor)
 
 	if (spi_nor_parse_sfdp(nor)) {
 		memcpy(nor->params, &sfdp_params, sizeof(*nor->params));
-		nor->addr_nbytes = 0;
 		nor->flags &= ~SNOR_F_4B_OPCODES;
 	}
 }
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index 19a692e27c92..7dc4cda41db3 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -340,6 +340,7 @@ struct spi_nor_otp {
  * @writesize		Minimal writable flash unit size. Defaults to 1. Set to
  *			ECC unit size for ECC-ed flashes.
  * @page_size:		the page size of the SPI NOR flash memory.
+ * @addr_nbytes:	number of address bytes to send.
  * @rdsr_dummy:		dummy cycles needed for Read Status Register command
  *			in octal DTR mode.
  * @rdsr_addr_nbytes:	dummy address bytes needed for Read Status Register
@@ -372,6 +373,7 @@ struct spi_nor_flash_parameter {
 	u64				size;
 	u32				writesize;
 	u32				page_size;
+	u8				addr_nbytes;
 	u8				rdsr_dummy;
 	u8				rdsr_addr_nbytes;
 
diff --git a/drivers/mtd/spi-nor/issi.c b/drivers/mtd/spi-nor/issi.c
index 71687e5babdc..89a66a19d754 100644
--- a/drivers/mtd/spi-nor/issi.c
+++ b/drivers/mtd/spi-nor/issi.c
@@ -20,7 +20,7 @@ is25lp256_post_bfpt_fixups(struct spi_nor *nor,
 	 */
 	if ((bfpt->dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) ==
 		BFPT_DWORD1_ADDRESS_BYTES_3_ONLY)
-		nor->addr_nbytes = 4;
+		nor->params->addr_nbytes = 4;
 
 	return 0;
 }
diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c
index 61ae8c8c5237..3a48173a2d78 100644
--- a/drivers/mtd/spi-nor/sfdp.c
+++ b/drivers/mtd/spi-nor/sfdp.c
@@ -462,11 +462,11 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
 	switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) {
 	case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY:
 	case BFPT_DWORD1_ADDRESS_BYTES_3_OR_4:
-		nor->addr_nbytes = 3;
+		params->addr_nbytes = 3;
 		break;
 
 	case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY:
-		nor->addr_nbytes = 4;
+		params->addr_nbytes = 4;
 		break;
 
 	default:
@@ -653,7 +653,7 @@ static u8 spi_nor_smpt_addr_nbytes(const struct spi_nor *nor, const u32 settings
 		return 4;
 	case SMPT_CMD_ADDRESS_LEN_USE_CURRENT:
 	default:
-		return nor->addr_nbytes;
+		return nor->params->addr_nbytes;
 	}
 }
 
@@ -1098,7 +1098,7 @@ static int spi_nor_parse_4bait(struct spi_nor *nor,
 	 * Spansion memory. However this quirk is no longer needed with new
 	 * SFDP compliant memories.
 	 */
-	nor->addr_nbytes = 4;
+	params->addr_nbytes = 4;
 	nor->flags |= SNOR_F_4B_OPCODES | SNOR_F_HAS_4BAIT;
 
 	/* fall through */
-- 
2.25.1


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Re: [PATCH v17 3/7] mtd: spi-nor: Do not change nor->addr_nbytes at SFDP parsing time

[Pratyush Yadav]

On 25/07/22 12:25PM, Tudor Ambarus wrote:
> At the SFDP parsing time we should not change members of struct spi_nor,
> but instead fill members of struct spi_nor_flash_parameters which could
> later on be used by callers. The caller will then decide if SFDP params
> should be used and more importantly when they should be used. Clean the
> code flow and don't initialize nor->addr_nbytes at SFDP parsing time.
> 
> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
> Tested-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
> Reviewed-by: Michael Walle <michael@walle.cc>

Reviewed-by: Pratyush Yadav <p.yadav@ti.com>

-- 
Regards,
Pratyush Yadav
Texas Instruments Inc.

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[PATCH v17 4/7] mtd: spi-nor: core: Return error code from set_4byte_addr_mode()

[Tudor Ambarus]

From: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>

The prams->set_4byte_addr_mode returns error code but is not handled
in spi_nor_init(). Handle the return code from set_4byte_addr_mode().

Suggested-by: Michael Walle <michael@walle.cc>
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
 drivers/mtd/spi-nor/core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 9f07f1036151..ec4c368b4ba6 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -2724,7 +2724,7 @@ static int spi_nor_init(struct spi_nor *nor)
 		 */
 		WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET,
 			  "enabling reset hack; may not recover from unexpected reboots\n");
-		nor->params->set_4byte_addr_mode(nor, true);
+		return nor->params->set_4byte_addr_mode(nor, true);
 	}
 
 	return 0;
-- 
2.25.1


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Re: [PATCH v17 4/7] mtd: spi-nor: core: Return error code from set_4byte_addr_mode()

[Pratyush Yadav]

On 25/07/22 12:25PM, Tudor Ambarus wrote:
> From: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
> 
> The prams->set_4byte_addr_mode returns error code but is not handled
> in spi_nor_init(). Handle the return code from set_4byte_addr_mode().
> 
> Suggested-by: Michael Walle <michael@walle.cc>
> Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>

Reviewed-by: Pratyush Yadav <p.yadav@ti.com>

You could also add a print if this returns an error in 
spi_nor_restore(), but that can be a separate patch.

> ---
>  drivers/mtd/spi-nor/core.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
> index 9f07f1036151..ec4c368b4ba6 100644
> --- a/drivers/mtd/spi-nor/core.c
> +++ b/drivers/mtd/spi-nor/core.c
> @@ -2724,7 +2724,7 @@ static int spi_nor_init(struct spi_nor *nor)
>  		 */
>  		WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET,
>  			  "enabling reset hack; may not recover from unexpected reboots\n");
> -		nor->params->set_4byte_addr_mode(nor, true);
> +		return nor->params->set_4byte_addr_mode(nor, true);
>  	}
>  
>  	return 0;
> -- 
> 2.25.1
> 

-- 
Regards,
Pratyush Yadav
Texas Instruments Inc.

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Re: [PATCH v17 4/7] mtd: spi-nor: core: Return error code from set_4byte_addr_mode()

[Michael Walle]

Am 2022-07-25 11:25, schrieb Tudor Ambarus:
> From: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
> 
> The prams->set_4byte_addr_mode returns error code but is not handled
> in spi_nor_init(). Handle the return code from set_4byte_addr_mode().
> 
> Suggested-by: Michael Walle <michael@walle.cc>
> Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>

Reviewed-by: Michael Walle <michael@walle.cc>

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[PATCH v17 5/7] mtd: spi-nor: core: Track flash's internal address mode

[Tudor Ambarus]

We need to track the flash's internal address mode as there are flashes
that can operate with 4B opcodes but unfortunately do not have a 4B opcode
correspondent for all the 3B opcodes. Such an example is the Infineon
Semper chips which provide 4B opcodes for read/program/erase but do not
provide 4B opcodes for Read/Write Any Register. These registers are
indexed by address and require the internal address mode of the flash
before Read/Write Any Register opcodes are issued.
4B opcodes are preferred over changing the flash's address mode to 4byte,
as set_4byte_addr_mode could be done in a non-volatile way and could break
the boot sequence. Thus we need to track the flash's internal address mode
so that we can use 4B opcodes together with opcodes that don't have a 4B
opcode correspondent. Track flash's internal address mode.

addr_mode_nbytes is discovered when parsing BFPT. For the
BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 case, one could introduce a method that
queries the flash's internal address mode at run-time (works for Winbond).
If a run-time querying can not be accomplished or if SFDP is not defined
at all, but the address mode is volatile and resets to a default known
value at boot, one can change the default addr_mode_nbytes value of 3 by
introducing a flash_info flag. If the address mode can not be queried,
discovered and it is configured via a non-volatile register, we may
introduce a dt property, but it will harm the generic approach of the
jedec,spi-nor compatible. All this complexity is not needed now, so let it
for future development.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
 drivers/mtd/spi-nor/core.h | 5 +++++
 drivers/mtd/spi-nor/sfdp.c | 6 +++---
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index 7dc4cda41db3..85b0cf254e97 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -341,6 +341,10 @@ struct spi_nor_otp {
  *			ECC unit size for ECC-ed flashes.
  * @page_size:		the page size of the SPI NOR flash memory.
  * @addr_nbytes:	number of address bytes to send.
+ * @addr_mode_nbytes:	number of address bytes of current address mode. Useful
+ *			when the flash operates with 4B opcodes but needs the
+ *			internal address mode for opcodes that don't have a 4B
+ *			opcode correspondent.
  * @rdsr_dummy:		dummy cycles needed for Read Status Register command
  *			in octal DTR mode.
  * @rdsr_addr_nbytes:	dummy address bytes needed for Read Status Register
@@ -374,6 +378,7 @@ struct spi_nor_flash_parameter {
 	u32				writesize;
 	u32				page_size;
 	u8				addr_nbytes;
+	u8				addr_mode_nbytes;
 	u8				rdsr_dummy;
 	u8				rdsr_addr_nbytes;
 
diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c
index 3a48173a2d78..c7973368f5dc 100644
--- a/drivers/mtd/spi-nor/sfdp.c
+++ b/drivers/mtd/spi-nor/sfdp.c
@@ -462,11 +462,11 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
 	switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) {
 	case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY:
 	case BFPT_DWORD1_ADDRESS_BYTES_3_OR_4:
-		params->addr_nbytes = 3;
+		params->addr_mode_nbytes = params->addr_nbytes = 3;
 		break;
 
 	case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY:
-		params->addr_nbytes = 4;
+		params->addr_mode_nbytes = params->addr_nbytes = 4;
 		break;
 
 	default:
@@ -653,7 +653,7 @@ static u8 spi_nor_smpt_addr_nbytes(const struct spi_nor *nor, const u32 settings
 		return 4;
 	case SMPT_CMD_ADDRESS_LEN_USE_CURRENT:
 	default:
-		return nor->params->addr_nbytes;
+		return nor->params->addr_mode_nbytes;
 	}
 }
 
-- 
2.25.1


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Re: [PATCH v17 5/7] mtd: spi-nor: core: Track flash's internal address mode

[Tudor.Ambarus]

Hi, Takahiro,

Can I have your R-b tag on this patch, please?

Thanks,
ta

On 7/25/22 12:25, Tudor Ambarus wrote:
> We need to track the flash's internal address mode as there are flashes
> that can operate with 4B opcodes but unfortunately do not have a 4B opcode
> correspondent for all the 3B opcodes. Such an example is the Infineon
> Semper chips which provide 4B opcodes for read/program/erase but do not
> provide 4B opcodes for Read/Write Any Register. These registers are
> indexed by address and require the internal address mode of the flash
> before Read/Write Any Register opcodes are issued.
> 4B opcodes are preferred over changing the flash's address mode to 4byte,
> as set_4byte_addr_mode could be done in a non-volatile way and could break
> the boot sequence. Thus we need to track the flash's internal address mode
> so that we can use 4B opcodes together with opcodes that don't have a 4B
> opcode correspondent. Track flash's internal address mode.
> 
> addr_mode_nbytes is discovered when parsing BFPT. For the
> BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 case, one could introduce a method that
> queries the flash's internal address mode at run-time (works for Winbond).
> If a run-time querying can not be accomplished or if SFDP is not defined
> at all, but the address mode is volatile and resets to a default known
> value at boot, one can change the default addr_mode_nbytes value of 3 by
> introducing a flash_info flag. If the address mode can not be queried,
> discovered and it is configured via a non-volatile register, we may
> introduce a dt property, but it will harm the generic approach of the
> jedec,spi-nor compatible. All this complexity is not needed now, so let it
> for future development.
> 
> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
> ---
>  drivers/mtd/spi-nor/core.h | 5 +++++
>  drivers/mtd/spi-nor/sfdp.c | 6 +++---
>  2 files changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
> index 7dc4cda41db3..85b0cf254e97 100644
> --- a/drivers/mtd/spi-nor/core.h
> +++ b/drivers/mtd/spi-nor/core.h
> @@ -341,6 +341,10 @@ struct spi_nor_otp {
>   *			ECC unit size for ECC-ed flashes.
>   * @page_size:		the page size of the SPI NOR flash memory.
>   * @addr_nbytes:	number of address bytes to send.
> + * @addr_mode_nbytes:	number of address bytes of current address mode. Useful
> + *			when the flash operates with 4B opcodes but needs the
> + *			internal address mode for opcodes that don't have a 4B
> + *			opcode correspondent.
>   * @rdsr_dummy:		dummy cycles needed for Read Status Register command
>   *			in octal DTR mode.
>   * @rdsr_addr_nbytes:	dummy address bytes needed for Read Status Register
> @@ -374,6 +378,7 @@ struct spi_nor_flash_parameter {
>  	u32				writesize;
>  	u32				page_size;
>  	u8				addr_nbytes;
> +	u8				addr_mode_nbytes;
>  	u8				rdsr_dummy;
>  	u8				rdsr_addr_nbytes;
>  
> diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c
> index 3a48173a2d78..c7973368f5dc 100644
> --- a/drivers/mtd/spi-nor/sfdp.c
> +++ b/drivers/mtd/spi-nor/sfdp.c
> @@ -462,11 +462,11 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
>  	switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) {
>  	case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY:
>  	case BFPT_DWORD1_ADDRESS_BYTES_3_OR_4:
> -		params->addr_nbytes = 3;
> +		params->addr_mode_nbytes = params->addr_nbytes = 3;
>  		break;
>  
>  	case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY:
> -		params->addr_nbytes = 4;
> +		params->addr_mode_nbytes = params->addr_nbytes = 4;
>  		break;
>  
>  	default:
> @@ -653,7 +653,7 @@ static u8 spi_nor_smpt_addr_nbytes(const struct spi_nor *nor, const u32 settings
>  		return 4;
>  	case SMPT_CMD_ADDRESS_LEN_USE_CURRENT:
>  	default:
> -		return nor->params->addr_nbytes;
> +		return nor->params->addr_mode_nbytes;
>  	}
>  }
>  


-- 
Cheers,
ta
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Re: [PATCH v17 5/7] mtd: spi-nor: core: Track flash's internal address mode

[Takahiro Kuwano]

On 7/26/2022 5:04 PM, Tudor.Ambarus@microchip.com wrote:
> Hi, Takahiro,
> 
> Can I have your R-b tag on this patch, please?
> 
I confirmed this works on SEMPER S25 devices.

Reviewed-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>

Best Regards,
Takahiro



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Re: [PATCH v17 5/7] mtd: spi-nor: core: Track flash's internal address mode

[Vanessa Page]

This is the dumbest shit I’ve never seen

Sent from my iPhone

> On Jul 26, 2022, at 4:37 AM, Takahiro Kuwano <tkuw584924@gmail.com> wrote:
> 
> On 7/26/2022 5:04 PM, Tudor.Ambarus@microchip.com wrote:
>> Hi, Takahiro,
>> 
>> Can I have your R-b tag on this patch, please?
>> 
> I confirmed this works on SEMPER S25 devices.
> 
> Reviewed-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
> 
> Best Regards,
> Takahiro
> 
> 
> 
> ______________________________________________________
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> http://lists.infradead.org/mailman/listinfo/linux-mtd/
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Re: [PATCH v17 5/7] mtd: spi-nor: core: Track flash's internal address mode

[Michael Walle]

Am 2022-07-25 11:25, schrieb Tudor Ambarus:
> We need to track the flash's internal address mode as there are flashes
> that can operate with 4B opcodes but unfortunately do not have a 4B 
> opcode
> correspondent for all the 3B opcodes. Such an example is the Infineon
> Semper chips which provide 4B opcodes for read/program/erase but do not
> provide 4B opcodes for Read/Write Any Register. These registers are
> indexed by address and require the internal address mode of the flash
> before Read/Write Any Register opcodes are issued.
> 4B opcodes are preferred over changing the flash's address mode to 
> 4byte,
> as set_4byte_addr_mode could be done in a non-volatile way and could 
> break
> the boot sequence. Thus we need to track the flash's internal address 
> mode
> so that we can use 4B opcodes together with opcodes that don't have a 
> 4B
> opcode correspondent. Track flash's internal address mode.
> 
> addr_mode_nbytes is discovered when parsing BFPT. For the
> BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 case, one could introduce a method 
> that
> queries the flash's internal address mode at run-time (works for 
> Winbond).
> If a run-time querying can not be accomplished or if SFDP is not 
> defined
> at all, but the address mode is volatile and resets to a default known
> value at boot, one can change the default addr_mode_nbytes value of 3 
> by
> introducing a flash_info flag. If the address mode can not be queried,
> discovered and it is configured via a non-volatile register, we may
> introduce a dt property, but it will harm the generic approach of the
> jedec,spi-nor compatible. All this complexity is not needed now, so let 
> it
> for future development.
> 
> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
> ---
>  drivers/mtd/spi-nor/core.h | 5 +++++
>  drivers/mtd/spi-nor/sfdp.c | 6 +++---
>  2 files changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
> index 7dc4cda41db3..85b0cf254e97 100644
> --- a/drivers/mtd/spi-nor/core.h
> +++ b/drivers/mtd/spi-nor/core.h
> @@ -341,6 +341,10 @@ struct spi_nor_otp {
>   *			ECC unit size for ECC-ed flashes.
>   * @page_size:		the page size of the SPI NOR flash memory.
>   * @addr_nbytes:	number of address bytes to send.
> + * @addr_mode_nbytes:	number of address bytes of current address mode. 
> Useful
> + *			when the flash operates with 4B opcodes but needs the
> + *			internal address mode for opcodes that don't have a 4B
> + *			opcode correspondent.
>   * @rdsr_dummy:		dummy cycles needed for Read Status Register command
>   *			in octal DTR mode.
>   * @rdsr_addr_nbytes:	dummy address bytes needed for Read Status 
> Register
> @@ -374,6 +378,7 @@ struct spi_nor_flash_parameter {
>  	u32				writesize;
>  	u32				page_size;
>  	u8				addr_nbytes;
> +	u8				addr_mode_nbytes;
>  	u8				rdsr_dummy;
>  	u8				rdsr_addr_nbytes;
> 
> diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c
> index 3a48173a2d78..c7973368f5dc 100644
> --- a/drivers/mtd/spi-nor/sfdp.c
> +++ b/drivers/mtd/spi-nor/sfdp.c
> @@ -462,11 +462,11 @@ static int spi_nor_parse_bfpt(struct spi_nor 
> *nor,
>  	switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) 
> {
>  	case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY:
>  	case BFPT_DWORD1_ADDRESS_BYTES_3_OR_4:
> -		params->addr_nbytes = 3;
> +		params->addr_mode_nbytes = params->addr_nbytes = 3;

I'd suggest to just use two lines here because you still can do a git
blame and (maybe) see what the purpose of addr_nbytes was. But I
don't have an objection here. You might or might not change it while
committing.

Reviewed-by: Michael Walle <michael@walle.cc>

>  		break;
> 
>  	case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY:
> -		params->addr_nbytes = 4;
> +		params->addr_mode_nbytes = params->addr_nbytes = 4;
>  		break;
> 
>  	default:
> @@ -653,7 +653,7 @@ static u8 spi_nor_smpt_addr_nbytes(const struct
> spi_nor *nor, const u32 settings
>  		return 4;
>  	case SMPT_CMD_ADDRESS_LEN_USE_CURRENT:
>  	default:
> -		return nor->params->addr_nbytes;
> +		return nor->params->addr_mode_nbytes;
>  	}
>  }

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Re: [PATCH v17 5/7] mtd: spi-nor: core: Track flash's internal address mode

[Tudor.Ambarus]

On 7/27/22 14:12, Michael Walle wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Am 2022-07-25 11:25, schrieb Tudor Ambarus:
>> We need to track the flash's internal address mode as there are flashes
>> that can operate with 4B opcodes but unfortunately do not have a 4B
>> opcode
>> correspondent for all the 3B opcodes. Such an example is the Infineon
>> Semper chips which provide 4B opcodes for read/program/erase but do not
>> provide 4B opcodes for Read/Write Any Register. These registers are
>> indexed by address and require the internal address mode of the flash
>> before Read/Write Any Register opcodes are issued.
>> 4B opcodes are preferred over changing the flash's address mode to
>> 4byte,
>> as set_4byte_addr_mode could be done in a non-volatile way and could
>> break
>> the boot sequence. Thus we need to track the flash's internal address
>> mode
>> so that we can use 4B opcodes together with opcodes that don't have a
>> 4B
>> opcode correspondent. Track flash's internal address mode.
>>
>> addr_mode_nbytes is discovered when parsing BFPT. For the
>> BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 case, one could introduce a method
>> that
>> queries the flash's internal address mode at run-time (works for
>> Winbond).
>> If a run-time querying can not be accomplished or if SFDP is not
>> defined
>> at all, but the address mode is volatile and resets to a default known
>> value at boot, one can change the default addr_mode_nbytes value of 3
>> by
>> introducing a flash_info flag. If the address mode can not be queried,
>> discovered and it is configured via a non-volatile register, we may
>> introduce a dt property, but it will harm the generic approach of the
>> jedec,spi-nor compatible. All this complexity is not needed now, so let
>> it
>> for future development.
>>
>> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
>> ---
>>  drivers/mtd/spi-nor/core.h | 5 +++++
>>  drivers/mtd/spi-nor/sfdp.c | 6 +++---
>>  2 files changed, 8 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
>> index 7dc4cda41db3..85b0cf254e97 100644
>> --- a/drivers/mtd/spi-nor/core.h
>> +++ b/drivers/mtd/spi-nor/core.h
>> @@ -341,6 +341,10 @@ struct spi_nor_otp {
>>   *                   ECC unit size for ECC-ed flashes.
>>   * @page_size:               the page size of the SPI NOR flash memory.
>>   * @addr_nbytes:     number of address bytes to send.
>> + * @addr_mode_nbytes:        number of address bytes of current address mode.
>> Useful
>> + *                   when the flash operates with 4B opcodes but needs the
>> + *                   internal address mode for opcodes that don't have a 4B
>> + *                   opcode correspondent.
>>   * @rdsr_dummy:              dummy cycles needed for Read Status Register command
>>   *                   in octal DTR mode.
>>   * @rdsr_addr_nbytes:        dummy address bytes needed for Read Status
>> Register
>> @@ -374,6 +378,7 @@ struct spi_nor_flash_parameter {
>>       u32                             writesize;
>>       u32                             page_size;
>>       u8                              addr_nbytes;
>> +     u8                              addr_mode_nbytes;
>>       u8                              rdsr_dummy;
>>       u8                              rdsr_addr_nbytes;
>>
>> diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c
>> index 3a48173a2d78..c7973368f5dc 100644
>> --- a/drivers/mtd/spi-nor/sfdp.c
>> +++ b/drivers/mtd/spi-nor/sfdp.c
>> @@ -462,11 +462,11 @@ static int spi_nor_parse_bfpt(struct spi_nor
>> *nor,
>>       switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK)
>> {
>>       case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY:
>>       case BFPT_DWORD1_ADDRESS_BYTES_3_OR_4:
>> -             params->addr_nbytes = 3;
>> +             params->addr_mode_nbytes = params->addr_nbytes = 3;
> 
> I'd suggest to just use two lines here because you still can do a git
> blame and (maybe) see what the purpose of addr_nbytes was. But I
> don't have an objection here. You might or might not change it while
> committing.

will change, thanks for reviewing it!

> 
> Reviewed-by: Michael Walle <michael@walle.cc>
> 
>>               break;
>>
>>       case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY:
>> -             params->addr_nbytes = 4;
>> +             params->addr_mode_nbytes = params->addr_nbytes = 4;
>>               break;
>>
>>       default:
>> @@ -653,7 +653,7 @@ static u8 spi_nor_smpt_addr_nbytes(const struct
>> spi_nor *nor, const u32 settings
>>               return 4;
>>       case SMPT_CMD_ADDRESS_LEN_USE_CURRENT:
>>       default:
>> -             return nor->params->addr_nbytes;
>> +             return nor->params->addr_mode_nbytes;
>>       }
>>  }


-- 
Cheers,
ta
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[PATCH v17 6/7] mtd: spi-nor: spansion: Add local function to discover page size

[Tudor Ambarus]

From: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>

The page size check in s28hs512t fixup can be used for s25hs/hl-t as well.
Move that to a newly created local function.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
 drivers/mtd/spi-nor/spansion.c | 53 ++++++++++++++++++++--------------
 1 file changed, 31 insertions(+), 22 deletions(-)

diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
index 43cd6cd92537..60e41e1a9a92 100644
--- a/drivers/mtd/spi-nor/spansion.c
+++ b/drivers/mtd/spi-nor/spansion.c
@@ -113,6 +113,36 @@ static int cypress_nor_octal_dtr_dis(struct spi_nor *nor)
 	return 0;
 }
 
+/**
+ * cypress_nor_set_page_size() - Set page size which corresponds to the flash
+ *                               configuration.
+ * @nor:	pointer to a 'struct spi_nor'
+ *
+ * The BFPT table advertises a 512B or 256B page size depending on part but the
+ * page size is actually configurable (with the default being 256B). Read from
+ * CFR3V[4] and set the correct size.
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int cypress_nor_set_page_size(struct spi_nor *nor)
+{
+	struct spi_mem_op op =
+		CYPRESS_NOR_RD_ANY_REG_OP(3, SPINOR_REG_CYPRESS_CFR3V,
+					  nor->bouncebuf);
+	int ret;
+
+	ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto);
+	if (ret)
+		return ret;
+
+	if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR3V_PGSZ)
+		nor->params->page_size = 512;
+	else
+		nor->params->page_size = 256;
+
+	return 0;
+}
+
 /**
  * cypress_nor_octal_dtr_enable() - Enable octal DTR on Cypress flashes.
  * @nor:		pointer to a 'struct spi_nor'
@@ -167,28 +197,7 @@ static int s28hs512t_post_bfpt_fixup(struct spi_nor *nor,
 				     const struct sfdp_parameter_header *bfpt_header,
 				     const struct sfdp_bfpt *bfpt)
 {
-	/*
-	 * The BFPT table advertises a 512B page size but the page size is
-	 * actually configurable (with the default being 256B). Read from
-	 * CFR3V[4] and set the correct size.
-	 */
-	struct spi_mem_op op =
-		CYPRESS_NOR_RD_ANY_REG_OP(3, SPINOR_REG_CYPRESS_CFR3V,
-					  nor->bouncebuf);
-	int ret;
-
-	spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
-
-	ret = spi_mem_exec_op(nor->spimem, &op);
-	if (ret)
-		return ret;
-
-	if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR3V_PGSZ)
-		nor->params->page_size = 512;
-	else
-		nor->params->page_size = 256;
-
-	return 0;
+	return cypress_nor_set_page_size(nor);
 }
 
 static const struct spi_nor_fixups s28hs512t_fixups = {
-- 
2.25.1


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Re: [PATCH v17 6/7] mtd: spi-nor: spansion: Add local function to discover page size

[Michael Walle]

Am 2022-07-25 11:25, schrieb Tudor Ambarus:
> From: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
> 
> The page size check in s28hs512t fixup can be used for s25hs/hl-t as 
> well.
> Move that to a newly created local function.
> 
> Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>

Reviewed-by: Michael Walle <michael@walle.cc>

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[PATCH v17 7/7] mtd: spi-nor: spansion: Add s25hl-t/s25hs-t IDs and fixups

[Tudor Ambarus]

From: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>

The S25HL-T/S25HS-T family is the Infineon SEMPER Flash with Quad SPI.

These Infineon chips support volatile version of configuration registers
and it is recommended to update volatile registers in the field application
due to a risk of the non-volatile registers corruption by power interrupt.
Add support for volatile QE bit.

For the single-die package parts (512Mb and 1Gb), only bottom 4KB and
uniform sector sizes are supported. This is due to missing or incorrect
entries in SMPT. Fixup for other sector sizes configurations will be
followed up as needed.

Tested on Xilinx Zynq-7000 FPGA board.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
 drivers/mtd/spi-nor/spansion.c | 132 +++++++++++++++++++++++++++++++++
 1 file changed, 132 insertions(+)

diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
index 60e41e1a9a92..0f5b9e81719f 100644
--- a/drivers/mtd/spi-nor/spansion.c
+++ b/drivers/mtd/spi-nor/spansion.c
@@ -14,6 +14,8 @@
 #define SPINOR_OP_CLSR		0x30	/* Clear status register 1 */
 #define SPINOR_OP_RD_ANY_REG			0x65	/* Read any register */
 #define SPINOR_OP_WR_ANY_REG			0x71	/* Write any register */
+#define SPINOR_REG_CYPRESS_CFR1V		0x00800002
+#define SPINOR_REG_CYPRESS_CFR1V_QUAD_EN	BIT(1)	/* Quad Enable */
 #define SPINOR_REG_CYPRESS_CFR2V		0x00800003
 #define SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24	0xb
 #define SPINOR_REG_CYPRESS_CFR3V		0x00800004
@@ -113,6 +115,68 @@ static int cypress_nor_octal_dtr_dis(struct spi_nor *nor)
 	return 0;
 }
 
+/**
+ * cypress_nor_quad_enable_volatile() - enable Quad I/O mode in volatile
+ *                                      register.
+ * @nor:	pointer to a 'struct spi_nor'
+ *
+ * It is recommended to update volatile registers in the field application due
+ * to a risk of the non-volatile registers corruption by power interrupt. This
+ * function sets Quad Enable bit in CFR1 volatile. If users set the Quad Enable
+ * bit in the CFR1 non-volatile in advance (typically by a Flash programmer
+ * before mounting Flash on PCB), the Quad Enable bit in the CFR1 volatile is
+ * also set during Flash power-up.
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int cypress_nor_quad_enable_volatile(struct spi_nor *nor)
+{
+	struct spi_mem_op op;
+	u8 addr_mode_nbytes = nor->params->addr_mode_nbytes;
+	u8 cfr1v_written;
+	int ret;
+
+	op = (struct spi_mem_op)
+		CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes,
+					  SPINOR_REG_CYPRESS_CFR1V,
+					  nor->bouncebuf);
+
+	ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto);
+	if (ret)
+		return ret;
+
+	if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR1V_QUAD_EN)
+		return 0;
+
+	/* Update the Quad Enable bit. */
+	nor->bouncebuf[0] |= SPINOR_REG_CYPRESS_CFR1V_QUAD_EN;
+	op = (struct spi_mem_op)
+		CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes,
+					  SPINOR_REG_CYPRESS_CFR1V, 1,
+					  nor->bouncebuf);
+	ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
+	if (ret)
+		return ret;
+
+	cfr1v_written = nor->bouncebuf[0];
+
+	/* Read back and check it. */
+	op = (struct spi_mem_op)
+		CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes,
+					  SPINOR_REG_CYPRESS_CFR1V,
+					  nor->bouncebuf);
+	ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto);
+	if (ret)
+		return ret;
+
+	if (nor->bouncebuf[0] != cfr1v_written) {
+		dev_err(nor->dev, "CFR1: Read back test failed\n");
+		return -EIO;
+	}
+
+	return 0;
+}
+
 /**
  * cypress_nor_set_page_size() - Set page size which corresponds to the flash
  *                               configuration.
@@ -143,6 +207,58 @@ static int cypress_nor_set_page_size(struct spi_nor *nor)
 	return 0;
 }
 
+static int
+s25hx_t_post_bfpt_fixup(struct spi_nor *nor,
+			const struct sfdp_parameter_header *bfpt_header,
+			const struct sfdp_bfpt *bfpt)
+{
+	/* Replace Quad Enable with volatile version */
+	nor->params->quad_enable = cypress_nor_quad_enable_volatile;
+
+	return cypress_nor_set_page_size(nor);
+}
+
+static void s25hx_t_post_sfdp_fixup(struct spi_nor *nor)
+{
+	struct spi_nor_erase_type *erase_type =
+					nor->params->erase_map.erase_type;
+	int i;
+
+	/*
+	 * In some parts, 3byte erase opcodes are advertised by 4BAIT.
+	 * Convert them to 4byte erase opcodes.
+	 */
+	for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
+		switch (erase_type[i].opcode) {
+		case SPINOR_OP_SE:
+			erase_type[i].opcode = SPINOR_OP_SE_4B;
+			break;
+		case SPINOR_OP_BE_4K:
+			erase_type[i].opcode = SPINOR_OP_BE_4K_4B;
+			break;
+		default:
+			break;
+		}
+	}
+}
+
+static void s25hx_t_late_init(struct spi_nor *nor)
+{
+	struct spi_nor_flash_parameter *params = nor->params;
+
+	/* Fast Read 4B requires mode cycles */
+	params->reads[SNOR_CMD_READ_FAST].num_mode_clocks = 8;
+
+	/* The writesize should be ECC data unit size */
+	params->writesize = 16;
+}
+
+static struct spi_nor_fixups s25hx_t_fixups = {
+	.post_bfpt = s25hx_t_post_bfpt_fixup,
+	.post_sfdp = s25hx_t_post_sfdp_fixup,
+	.late_init = s25hx_t_late_init,
+};
+
 /**
  * cypress_nor_octal_dtr_enable() - Enable octal DTR on Cypress flashes.
  * @nor:		pointer to a 'struct spi_nor'
@@ -319,6 +435,22 @@ static const struct flash_info spansion_nor_parts[] = {
 	{ "s25fl256l",  INFO(0x016019,      0,  64 * 1024, 512)
 		NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
 		FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
+	{ "s25hl512t",  INFO6(0x342a1a, 0x0f0390, 256 * 1024, 256)
+		PARSE_SFDP
+		MFR_FLAGS(USE_CLSR)
+		.fixups = &s25hx_t_fixups },
+	{ "s25hl01gt",  INFO6(0x342a1b, 0x0f0390, 256 * 1024, 512)
+		PARSE_SFDP
+		MFR_FLAGS(USE_CLSR)
+		.fixups = &s25hx_t_fixups },
+	{ "s25hs512t",  INFO6(0x342b1a, 0x0f0390, 256 * 1024, 256)
+		PARSE_SFDP
+		MFR_FLAGS(USE_CLSR)
+		.fixups = &s25hx_t_fixups },
+	{ "s25hs01gt",  INFO6(0x342b1b, 0x0f0390, 256 * 1024, 512)
+		PARSE_SFDP
+		MFR_FLAGS(USE_CLSR)
+		.fixups = &s25hx_t_fixups },
 	{ "cy15x104q",  INFO6(0x042cc2, 0x7f7f7f, 512 * 1024, 1)
 		FLAGS(SPI_NOR_NO_ERASE) },
 	{ "s28hs512t",   INFO(0x345b1a,      0, 256 * 1024, 256)
-- 
2.25.1


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Re: [PATCH v17 7/7] mtd: spi-nor: spansion: Add s25hl-t/s25hs-t IDs and fixups

[Michael Walle]

Am 2022-07-25 11:25, schrieb Tudor Ambarus:
> From: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
> 
> The S25HL-T/S25HS-T family is the Infineon SEMPER Flash with Quad SPI.
> 
> These Infineon chips support volatile version of configuration 
> registers
> and it is recommended to update volatile registers in the field 
> application
> due to a risk of the non-volatile registers corruption by power 
> interrupt.
> Add support for volatile QE bit.
> 
> For the single-die package parts (512Mb and 1Gb), only bottom 4KB and
> uniform sector sizes are supported. This is due to missing or incorrect
> entries in SMPT. Fixup for other sector sizes configurations will be
> followed up as needed.
> 
> Tested on Xilinx Zynq-7000 FPGA board.
> 
> Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
> ---
>  drivers/mtd/spi-nor/spansion.c | 132 +++++++++++++++++++++++++++++++++
>  1 file changed, 132 insertions(+)
> 
> diff --git a/drivers/mtd/spi-nor/spansion.c 
> b/drivers/mtd/spi-nor/spansion.c
> index 60e41e1a9a92..0f5b9e81719f 100644
> --- a/drivers/mtd/spi-nor/spansion.c
> +++ b/drivers/mtd/spi-nor/spansion.c
> @@ -14,6 +14,8 @@
>  #define SPINOR_OP_CLSR		0x30	/* Clear status register 1 */
>  #define SPINOR_OP_RD_ANY_REG			0x65	/* Read any register */
>  #define SPINOR_OP_WR_ANY_REG			0x71	/* Write any register */
> +#define SPINOR_REG_CYPRESS_CFR1V		0x00800002
> +#define SPINOR_REG_CYPRESS_CFR1V_QUAD_EN	BIT(1)	/* Quad Enable */
>  #define SPINOR_REG_CYPRESS_CFR2V		0x00800003
>  #define SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24	0xb
>  #define SPINOR_REG_CYPRESS_CFR3V		0x00800004
> @@ -113,6 +115,68 @@ static int cypress_nor_octal_dtr_dis(struct 
> spi_nor *nor)
>  	return 0;
>  }
> 
> +/**
> + * cypress_nor_quad_enable_volatile() - enable Quad I/O mode in 
> volatile
> + *                                      register.
> + * @nor:	pointer to a 'struct spi_nor'
> + *
> + * It is recommended to update volatile registers in the field 
> application due
> + * to a risk of the non-volatile registers corruption by power 
> interrupt. This
> + * function sets Quad Enable bit in CFR1 volatile. If users set the 
> Quad Enable
> + * bit in the CFR1 non-volatile in advance (typically by a Flash 
> programmer
> + * before mounting Flash on PCB), the Quad Enable bit in the CFR1 
> volatile is
> + * also set during Flash power-up.
> + *
> + * Return: 0 on success, -errno otherwise.
> + */
> +static int cypress_nor_quad_enable_volatile(struct spi_nor *nor)
> +{
> +	struct spi_mem_op op;
> +	u8 addr_mode_nbytes = nor->params->addr_mode_nbytes;
> +	u8 cfr1v_written;
> +	int ret;
> +
> +	op = (struct spi_mem_op)
> +		CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes,
> +					  SPINOR_REG_CYPRESS_CFR1V,
> +					  nor->bouncebuf);
> +
> +	ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto);
> +	if (ret)
> +		return ret;
> +
> +	if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR1V_QUAD_EN)
> +		return 0;
> +
> +	/* Update the Quad Enable bit. */
> +	nor->bouncebuf[0] |= SPINOR_REG_CYPRESS_CFR1V_QUAD_EN;
> +	op = (struct spi_mem_op)
> +		CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes,
> +					  SPINOR_REG_CYPRESS_CFR1V, 1,
> +					  nor->bouncebuf);
> +	ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
> +	if (ret)
> +		return ret;
> +
> +	cfr1v_written = nor->bouncebuf[0];
> +
> +	/* Read back and check it. */
> +	op = (struct spi_mem_op)
> +		CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes,
> +					  SPINOR_REG_CYPRESS_CFR1V,
> +					  nor->bouncebuf);
> +	ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto);
> +	if (ret)
> +		return ret;
> +
> +	if (nor->bouncebuf[0] != cfr1v_written) {
> +		dev_err(nor->dev, "CFR1: Read back test failed\n");
> +		return -EIO;
> +	}
> +
> +	return 0;
> +}
> +
>  /**
>   * cypress_nor_set_page_size() - Set page size which corresponds to 
> the flash
>   *                               configuration.
> @@ -143,6 +207,58 @@ static int cypress_nor_set_page_size(struct 
> spi_nor *nor)
>  	return 0;
>  }
> 
> +static int
> +s25hx_t_post_bfpt_fixup(struct spi_nor *nor,
> +			const struct sfdp_parameter_header *bfpt_header,
> +			const struct sfdp_bfpt *bfpt)
> +{
> +	/* Replace Quad Enable with volatile version */
> +	nor->params->quad_enable = cypress_nor_quad_enable_volatile;
> +
> +	return cypress_nor_set_page_size(nor);
> +}
> +
> +static void s25hx_t_post_sfdp_fixup(struct spi_nor *nor)
> +{
> +	struct spi_nor_erase_type *erase_type =
> +					nor->params->erase_map.erase_type;
> +	int i;
> +
> +	/*
> +	 * In some parts, 3byte erase opcodes are advertised by 4BAIT.
> +	 * Convert them to 4byte erase opcodes.
> +	 */
> +	for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
> +		switch (erase_type[i].opcode) {
> +		case SPINOR_OP_SE:
> +			erase_type[i].opcode = SPINOR_OP_SE_4B;
> +			break;
> +		case SPINOR_OP_BE_4K:
> +			erase_type[i].opcode = SPINOR_OP_BE_4K_4B;
> +			break;
> +		default:
> +			break;
> +		}
> +	}
> +}
> +
> +static void s25hx_t_late_init(struct spi_nor *nor)
> +{
> +	struct spi_nor_flash_parameter *params = nor->params;
> +
> +	/* Fast Read 4B requires mode cycles */
> +	params->reads[SNOR_CMD_READ_FAST].num_mode_clocks = 8;
> +
> +	/* The writesize should be ECC data unit size */
> +	params->writesize = 16;
> +}
> +
> +static struct spi_nor_fixups s25hx_t_fixups = {
> +	.post_bfpt = s25hx_t_post_bfpt_fixup,
> +	.post_sfdp = s25hx_t_post_sfdp_fixup,
> +	.late_init = s25hx_t_late_init,
> +};
> +
>  /**
>   * cypress_nor_octal_dtr_enable() - Enable octal DTR on Cypress 
> flashes.
>   * @nor:		pointer to a 'struct spi_nor'
> @@ -319,6 +435,22 @@ static const struct flash_info 
> spansion_nor_parts[] = {
>  	{ "s25fl256l",  INFO(0x016019,      0,  64 * 1024, 512)
>  		NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
>  		FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
> +	{ "s25hl512t",  INFO6(0x342a1a, 0x0f0390, 256 * 1024, 256)

I know I'm really late, but would this also work with
{ "s25hl512t",  INFO6(0x342a1a, 0x0f0390, 0, 0)
		PARSE_SFDP

It seems the former patch will figure out the page size anyway.

-michael

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Re: [PATCH v17 7/7] mtd: spi-nor: spansion: Add s25hl-t/s25hs-t IDs and fixups

[Tudor.Ambarus]

On 7/27/22 14:18, Michael Walle wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Am 2022-07-25 11:25, schrieb Tudor Ambarus:
>> From: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
>>
>> The S25HL-T/S25HS-T family is the Infineon SEMPER Flash with Quad SPI.
>>
>> These Infineon chips support volatile version of configuration
>> registers
>> and it is recommended to update volatile registers in the field
>> application
>> due to a risk of the non-volatile registers corruption by power
>> interrupt.
>> Add support for volatile QE bit.
>>
>> For the single-die package parts (512Mb and 1Gb), only bottom 4KB and
>> uniform sector sizes are supported. This is due to missing or incorrect
>> entries in SMPT. Fixup for other sector sizes configurations will be
>> followed up as needed.
>>
>> Tested on Xilinx Zynq-7000 FPGA board.
>>
>> Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
>> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
>> ---
>>  drivers/mtd/spi-nor/spansion.c | 132 +++++++++++++++++++++++++++++++++
>>  1 file changed, 132 insertions(+)
>>
>> diff --git a/drivers/mtd/spi-nor/spansion.c
>> b/drivers/mtd/spi-nor/spansion.c
>> index 60e41e1a9a92..0f5b9e81719f 100644
>> --- a/drivers/mtd/spi-nor/spansion.c
>> +++ b/drivers/mtd/spi-nor/spansion.c
>> @@ -14,6 +14,8 @@
>>  #define SPINOR_OP_CLSR               0x30    /* Clear status register 1 */
>>  #define SPINOR_OP_RD_ANY_REG                 0x65    /* Read any register */
>>  #define SPINOR_OP_WR_ANY_REG                 0x71    /* Write any register */
>> +#define SPINOR_REG_CYPRESS_CFR1V             0x00800002
>> +#define SPINOR_REG_CYPRESS_CFR1V_QUAD_EN     BIT(1)  /* Quad Enable */
>>  #define SPINOR_REG_CYPRESS_CFR2V             0x00800003
>>  #define SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24        0xb
>>  #define SPINOR_REG_CYPRESS_CFR3V             0x00800004
>> @@ -113,6 +115,68 @@ static int cypress_nor_octal_dtr_dis(struct
>> spi_nor *nor)
>>       return 0;
>>  }
>>
>> +/**
>> + * cypress_nor_quad_enable_volatile() - enable Quad I/O mode in
>> volatile
>> + *                                      register.
>> + * @nor:     pointer to a 'struct spi_nor'
>> + *
>> + * It is recommended to update volatile registers in the field
>> application due
>> + * to a risk of the non-volatile registers corruption by power
>> interrupt. This
>> + * function sets Quad Enable bit in CFR1 volatile. If users set the
>> Quad Enable
>> + * bit in the CFR1 non-volatile in advance (typically by a Flash
>> programmer
>> + * before mounting Flash on PCB), the Quad Enable bit in the CFR1
>> volatile is
>> + * also set during Flash power-up.
>> + *
>> + * Return: 0 on success, -errno otherwise.
>> + */
>> +static int cypress_nor_quad_enable_volatile(struct spi_nor *nor)
>> +{
>> +     struct spi_mem_op op;
>> +     u8 addr_mode_nbytes = nor->params->addr_mode_nbytes;
>> +     u8 cfr1v_written;
>> +     int ret;
>> +
>> +     op = (struct spi_mem_op)
>> +             CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes,
>> +                                       SPINOR_REG_CYPRESS_CFR1V,
>> +                                       nor->bouncebuf);
>> +
>> +     ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto);
>> +     if (ret)
>> +             return ret;
>> +
>> +     if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR1V_QUAD_EN)
>> +             return 0;
>> +
>> +     /* Update the Quad Enable bit. */
>> +     nor->bouncebuf[0] |= SPINOR_REG_CYPRESS_CFR1V_QUAD_EN;
>> +     op = (struct spi_mem_op)
>> +             CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes,
>> +                                       SPINOR_REG_CYPRESS_CFR1V, 1,
>> +                                       nor->bouncebuf);
>> +     ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
>> +     if (ret)
>> +             return ret;
>> +
>> +     cfr1v_written = nor->bouncebuf[0];
>> +
>> +     /* Read back and check it. */
>> +     op = (struct spi_mem_op)
>> +             CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes,
>> +                                       SPINOR_REG_CYPRESS_CFR1V,
>> +                                       nor->bouncebuf);
>> +     ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto);
>> +     if (ret)
>> +             return ret;
>> +
>> +     if (nor->bouncebuf[0] != cfr1v_written) {
>> +             dev_err(nor->dev, "CFR1: Read back test failed\n");
>> +             return -EIO;
>> +     }
>> +
>> +     return 0;
>> +}
>> +
>>  /**
>>   * cypress_nor_set_page_size() - Set page size which corresponds to
>> the flash
>>   *                               configuration.
>> @@ -143,6 +207,58 @@ static int cypress_nor_set_page_size(struct
>> spi_nor *nor)
>>       return 0;
>>  }
>>
>> +static int
>> +s25hx_t_post_bfpt_fixup(struct spi_nor *nor,
>> +                     const struct sfdp_parameter_header *bfpt_header,
>> +                     const struct sfdp_bfpt *bfpt)
>> +{
>> +     /* Replace Quad Enable with volatile version */
>> +     nor->params->quad_enable = cypress_nor_quad_enable_volatile;
>> +
>> +     return cypress_nor_set_page_size(nor);
>> +}
>> +
>> +static void s25hx_t_post_sfdp_fixup(struct spi_nor *nor)
>> +{
>> +     struct spi_nor_erase_type *erase_type =
>> +                                     nor->params->erase_map.erase_type;
>> +     int i;
>> +
>> +     /*
>> +      * In some parts, 3byte erase opcodes are advertised by 4BAIT.
>> +      * Convert them to 4byte erase opcodes.
>> +      */
>> +     for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
>> +             switch (erase_type[i].opcode) {
>> +             case SPINOR_OP_SE:
>> +                     erase_type[i].opcode = SPINOR_OP_SE_4B;
>> +                     break;
>> +             case SPINOR_OP_BE_4K:
>> +                     erase_type[i].opcode = SPINOR_OP_BE_4K_4B;
>> +                     break;
>> +             default:
>> +                     break;
>> +             }
>> +     }
>> +}
>> +
>> +static void s25hx_t_late_init(struct spi_nor *nor)
>> +{
>> +     struct spi_nor_flash_parameter *params = nor->params;
>> +
>> +     /* Fast Read 4B requires mode cycles */
>> +     params->reads[SNOR_CMD_READ_FAST].num_mode_clocks = 8;
>> +
>> +     /* The writesize should be ECC data unit size */
>> +     params->writesize = 16;
>> +}
>> +
>> +static struct spi_nor_fixups s25hx_t_fixups = {
>> +     .post_bfpt = s25hx_t_post_bfpt_fixup,
>> +     .post_sfdp = s25hx_t_post_sfdp_fixup,
>> +     .late_init = s25hx_t_late_init,
>> +};
>> +
>>  /**
>>   * cypress_nor_octal_dtr_enable() - Enable octal DTR on Cypress
>> flashes.
>>   * @nor:             pointer to a 'struct spi_nor'
>> @@ -319,6 +435,22 @@ static const struct flash_info
>> spansion_nor_parts[] = {
>>       { "s25fl256l",  INFO(0x016019,      0,  64 * 1024, 512)
>>               NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
>>               FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
>> +     { "s25hl512t",  INFO6(0x342a1a, 0x0f0390, 256 * 1024, 256)
> 
> I know I'm really late, but would this also work with
> { "s25hl512t",  INFO6(0x342a1a, 0x0f0390, 0, 0)
>                PARSE_SFDP
> 
> It seems the former patch will figure out the page size anyway.

That's sector_size and n_sectors. Probably works, but we'd have
to change it anyway when the SNOR_ID3 patch is integrated. Plus, it may
confuse people as using zero values for these parameters will make
BP protection fail. I'd queue this as it is, and we'll ping Takahiro to
give us a Tested-by tag when converting all these to SNOR_ID3.

If it sounds fair to you, I'm happy to receive your R-b tag.

Thanks again for taking the time to review these.
-- 
Cheers,
ta
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Re: [PATCH v17 7/7] mtd: spi-nor: spansion: Add s25hl-t/s25hs-t IDs and fixups

[Michael Walle]

Am 2022-07-27 15:00, schrieb Tudor.Ambarus@microchip.com:
> On 7/27/22 14:18, Michael Walle wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know 
>> the content is safe
>> 
>> Am 2022-07-25 11:25, schrieb Tudor Ambarus:
>>> From: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
>>> 
>>> The S25HL-T/S25HS-T family is the Infineon SEMPER Flash with Quad 
>>> SPI.
>>> 
>>> These Infineon chips support volatile version of configuration
>>> registers
>>> and it is recommended to update volatile registers in the field
>>> application
>>> due to a risk of the non-volatile registers corruption by power
>>> interrupt.
>>> Add support for volatile QE bit.
>>> 
>>> For the single-die package parts (512Mb and 1Gb), only bottom 4KB and
>>> uniform sector sizes are supported. This is due to missing or 
>>> incorrect
>>> entries in SMPT. Fixup for other sector sizes configurations will be
>>> followed up as needed.
>>> 
>>> Tested on Xilinx Zynq-7000 FPGA board.
>>> 
>>> Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
>>> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
>>> ---
>>>  drivers/mtd/spi-nor/spansion.c | 132 
>>> +++++++++++++++++++++++++++++++++
>>>  1 file changed, 132 insertions(+)
>>> 
>>> diff --git a/drivers/mtd/spi-nor/spansion.c
>>> b/drivers/mtd/spi-nor/spansion.c
>>> index 60e41e1a9a92..0f5b9e81719f 100644
>>> --- a/drivers/mtd/spi-nor/spansion.c
>>> +++ b/drivers/mtd/spi-nor/spansion.c
>>> @@ -14,6 +14,8 @@
>>>  #define SPINOR_OP_CLSR               0x30    /* Clear status 
>>> register 1 */
>>>  #define SPINOR_OP_RD_ANY_REG                 0x65    /* Read any 
>>> register */
>>>  #define SPINOR_OP_WR_ANY_REG                 0x71    /* Write any 
>>> register */
>>> +#define SPINOR_REG_CYPRESS_CFR1V             0x00800002
>>> +#define SPINOR_REG_CYPRESS_CFR1V_QUAD_EN     BIT(1)  /* Quad Enable 
>>> */
>>>  #define SPINOR_REG_CYPRESS_CFR2V             0x00800003
>>>  #define SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24        0xb
>>>  #define SPINOR_REG_CYPRESS_CFR3V             0x00800004
>>> @@ -113,6 +115,68 @@ static int cypress_nor_octal_dtr_dis(struct
>>> spi_nor *nor)
>>>       return 0;
>>>  }
>>> 
>>> +/**
>>> + * cypress_nor_quad_enable_volatile() - enable Quad I/O mode in
>>> volatile
>>> + *                                      register.
>>> + * @nor:     pointer to a 'struct spi_nor'
>>> + *
>>> + * It is recommended to update volatile registers in the field
>>> application due
>>> + * to a risk of the non-volatile registers corruption by power
>>> interrupt. This
>>> + * function sets Quad Enable bit in CFR1 volatile. If users set the
>>> Quad Enable
>>> + * bit in the CFR1 non-volatile in advance (typically by a Flash
>>> programmer
>>> + * before mounting Flash on PCB), the Quad Enable bit in the CFR1
>>> volatile is
>>> + * also set during Flash power-up.
>>> + *
>>> + * Return: 0 on success, -errno otherwise.
>>> + */
>>> +static int cypress_nor_quad_enable_volatile(struct spi_nor *nor)
>>> +{
>>> +     struct spi_mem_op op;
>>> +     u8 addr_mode_nbytes = nor->params->addr_mode_nbytes;
>>> +     u8 cfr1v_written;
>>> +     int ret;
>>> +
>>> +     op = (struct spi_mem_op)
>>> +             CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes,
>>> +                                       SPINOR_REG_CYPRESS_CFR1V,
>>> +                                       nor->bouncebuf);
>>> +
>>> +     ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto);
>>> +     if (ret)
>>> +             return ret;
>>> +
>>> +     if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR1V_QUAD_EN)
>>> +             return 0;
>>> +
>>> +     /* Update the Quad Enable bit. */
>>> +     nor->bouncebuf[0] |= SPINOR_REG_CYPRESS_CFR1V_QUAD_EN;
>>> +     op = (struct spi_mem_op)
>>> +             CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes,
>>> +                                       SPINOR_REG_CYPRESS_CFR1V, 1,
>>> +                                       nor->bouncebuf);
>>> +     ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
>>> +     if (ret)
>>> +             return ret;
>>> +
>>> +     cfr1v_written = nor->bouncebuf[0];
>>> +
>>> +     /* Read back and check it. */
>>> +     op = (struct spi_mem_op)
>>> +             CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes,
>>> +                                       SPINOR_REG_CYPRESS_CFR1V,
>>> +                                       nor->bouncebuf);
>>> +     ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto);
>>> +     if (ret)
>>> +             return ret;
>>> +
>>> +     if (nor->bouncebuf[0] != cfr1v_written) {
>>> +             dev_err(nor->dev, "CFR1: Read back test failed\n");
>>> +             return -EIO;
>>> +     }
>>> +
>>> +     return 0;
>>> +}
>>> +
>>>  /**
>>>   * cypress_nor_set_page_size() - Set page size which corresponds to
>>> the flash
>>>   *                               configuration.
>>> @@ -143,6 +207,58 @@ static int cypress_nor_set_page_size(struct
>>> spi_nor *nor)
>>>       return 0;
>>>  }
>>> 
>>> +static int
>>> +s25hx_t_post_bfpt_fixup(struct spi_nor *nor,
>>> +                     const struct sfdp_parameter_header 
>>> *bfpt_header,
>>> +                     const struct sfdp_bfpt *bfpt)
>>> +{
>>> +     /* Replace Quad Enable with volatile version */
>>> +     nor->params->quad_enable = cypress_nor_quad_enable_volatile;
>>> +
>>> +     return cypress_nor_set_page_size(nor);
>>> +}
>>> +
>>> +static void s25hx_t_post_sfdp_fixup(struct spi_nor *nor)
>>> +{
>>> +     struct spi_nor_erase_type *erase_type =
>>> +                                     
>>> nor->params->erase_map.erase_type;
>>> +     int i;
>>> +
>>> +     /*
>>> +      * In some parts, 3byte erase opcodes are advertised by 4BAIT.
>>> +      * Convert them to 4byte erase opcodes.
>>> +      */
>>> +     for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
>>> +             switch (erase_type[i].opcode) {
>>> +             case SPINOR_OP_SE:
>>> +                     erase_type[i].opcode = SPINOR_OP_SE_4B;
>>> +                     break;
>>> +             case SPINOR_OP_BE_4K:
>>> +                     erase_type[i].opcode = SPINOR_OP_BE_4K_4B;
>>> +                     break;
>>> +             default:
>>> +                     break;
>>> +             }
>>> +     }
>>> +}
>>> +
>>> +static void s25hx_t_late_init(struct spi_nor *nor)
>>> +{
>>> +     struct spi_nor_flash_parameter *params = nor->params;
>>> +
>>> +     /* Fast Read 4B requires mode cycles */
>>> +     params->reads[SNOR_CMD_READ_FAST].num_mode_clocks = 8;
>>> +
>>> +     /* The writesize should be ECC data unit size */
>>> +     params->writesize = 16;
>>> +}
>>> +
>>> +static struct spi_nor_fixups s25hx_t_fixups = {
>>> +     .post_bfpt = s25hx_t_post_bfpt_fixup,
>>> +     .post_sfdp = s25hx_t_post_sfdp_fixup,
>>> +     .late_init = s25hx_t_late_init,
>>> +};
>>> +
>>>  /**
>>>   * cypress_nor_octal_dtr_enable() - Enable octal DTR on Cypress
>>> flashes.
>>>   * @nor:             pointer to a 'struct spi_nor'
>>> @@ -319,6 +435,22 @@ static const struct flash_info
>>> spansion_nor_parts[] = {
>>>       { "s25fl256l",  INFO(0x016019,      0,  64 * 1024, 512)
>>>               NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | 
>>> SPI_NOR_QUAD_READ)
>>>               FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
>>> +     { "s25hl512t",  INFO6(0x342a1a, 0x0f0390, 256 * 1024, 256)
>> 
>> I know I'm really late, but would this also work with
>> { "s25hl512t",  INFO6(0x342a1a, 0x0f0390, 0, 0)
>>                PARSE_SFDP
>> 
>> It seems the former patch will figure out the page size anyway.
> 
> That's sector_size and n_sectors. Probably works, but we'd have
> to change it anyway when the SNOR_ID3 patch is integrated. Plus, it may
> confuse people as using zero values for these parameters will make
> BP protection fail. I'd queue this as it is, and we'll ping Takahiro to
> give us a Tested-by tag when converting all these to SNOR_ID3.

These would be SNOR_ID6. Let's see if the retest will actually work ;)

I haven't looked too closely, so
Acked-by: Michael Walle <michael@walle.cc>

-michael

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Re: [PATCH v17 7/7] mtd: spi-nor: spansion: Add s25hl-t/s25hs-t IDs and fixups

[Tudor.Ambarus]

On 7/27/22 16:00, Tudor.Ambarus@microchip.com wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On 7/27/22 14:18, Michael Walle wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> Am 2022-07-25 11:25, schrieb Tudor Ambarus:
>>> From: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
>>>
>>> The S25HL-T/S25HS-T family is the Infineon SEMPER Flash with Quad SPI.
>>>
>>> These Infineon chips support volatile version of configuration
>>> registers
>>> and it is recommended to update volatile registers in the field
>>> application
>>> due to a risk of the non-volatile registers corruption by power
>>> interrupt.
>>> Add support for volatile QE bit.
>>>
>>> For the single-die package parts (512Mb and 1Gb), only bottom 4KB and
>>> uniform sector sizes are supported. This is due to missing or incorrect
>>> entries in SMPT. Fixup for other sector sizes configurations will be
>>> followed up as needed.
>>>
>>> Tested on Xilinx Zynq-7000 FPGA board.
>>>
>>> Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
>>> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
>>> ---
>>>  drivers/mtd/spi-nor/spansion.c | 132 +++++++++++++++++++++++++++++++++
>>>  1 file changed, 132 insertions(+)
>>>
>>> diff --git a/drivers/mtd/spi-nor/spansion.c
>>> b/drivers/mtd/spi-nor/spansion.c
>>> index 60e41e1a9a92..0f5b9e81719f 100644
>>> --- a/drivers/mtd/spi-nor/spansion.c
>>> +++ b/drivers/mtd/spi-nor/spansion.c
>>> @@ -14,6 +14,8 @@
>>>  #define SPINOR_OP_CLSR               0x30    /* Clear status register 1 */
>>>  #define SPINOR_OP_RD_ANY_REG                 0x65    /* Read any register */
>>>  #define SPINOR_OP_WR_ANY_REG                 0x71    /* Write any register */
>>> +#define SPINOR_REG_CYPRESS_CFR1V             0x00800002
>>> +#define SPINOR_REG_CYPRESS_CFR1V_QUAD_EN     BIT(1)  /* Quad Enable */
>>>  #define SPINOR_REG_CYPRESS_CFR2V             0x00800003
>>>  #define SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24        0xb
>>>  #define SPINOR_REG_CYPRESS_CFR3V             0x00800004
>>> @@ -113,6 +115,68 @@ static int cypress_nor_octal_dtr_dis(struct
>>> spi_nor *nor)
>>>       return 0;
>>>  }
>>>
>>> +/**
>>> + * cypress_nor_quad_enable_volatile() - enable Quad I/O mode in
>>> volatile
>>> + *                                      register.
>>> + * @nor:     pointer to a 'struct spi_nor'
>>> + *
>>> + * It is recommended to update volatile registers in the field
>>> application due
>>> + * to a risk of the non-volatile registers corruption by power
>>> interrupt. This
>>> + * function sets Quad Enable bit in CFR1 volatile. If users set the
>>> Quad Enable
>>> + * bit in the CFR1 non-volatile in advance (typically by a Flash
>>> programmer
>>> + * before mounting Flash on PCB), the Quad Enable bit in the CFR1
>>> volatile is
>>> + * also set during Flash power-up.
>>> + *
>>> + * Return: 0 on success, -errno otherwise.
>>> + */
>>> +static int cypress_nor_quad_enable_volatile(struct spi_nor *nor)
>>> +{
>>> +     struct spi_mem_op op;
>>> +     u8 addr_mode_nbytes = nor->params->addr_mode_nbytes;
>>> +     u8 cfr1v_written;
>>> +     int ret;
>>> +
>>> +     op = (struct spi_mem_op)
>>> +             CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes,
>>> +                                       SPINOR_REG_CYPRESS_CFR1V,
>>> +                                       nor->bouncebuf);
>>> +
>>> +     ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto);
>>> +     if (ret)
>>> +             return ret;
>>> +
>>> +     if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR1V_QUAD_EN)
>>> +             return 0;
>>> +
>>> +     /* Update the Quad Enable bit. */
>>> +     nor->bouncebuf[0] |= SPINOR_REG_CYPRESS_CFR1V_QUAD_EN;
>>> +     op = (struct spi_mem_op)
>>> +             CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes,
>>> +                                       SPINOR_REG_CYPRESS_CFR1V, 1,
>>> +                                       nor->bouncebuf);
>>> +     ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
>>> +     if (ret)
>>> +             return ret;
>>> +
>>> +     cfr1v_written = nor->bouncebuf[0];
>>> +
>>> +     /* Read back and check it. */
>>> +     op = (struct spi_mem_op)
>>> +             CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes,
>>> +                                       SPINOR_REG_CYPRESS_CFR1V,
>>> +                                       nor->bouncebuf);
>>> +     ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto);
>>> +     if (ret)
>>> +             return ret;
>>> +
>>> +     if (nor->bouncebuf[0] != cfr1v_written) {
>>> +             dev_err(nor->dev, "CFR1: Read back test failed\n");
>>> +             return -EIO;
>>> +     }
>>> +
>>> +     return 0;
>>> +}
>>> +
>>>  /**
>>>   * cypress_nor_set_page_size() - Set page size which corresponds to
>>> the flash
>>>   *                               configuration.
>>> @@ -143,6 +207,58 @@ static int cypress_nor_set_page_size(struct
>>> spi_nor *nor)
>>>       return 0;
>>>  }
>>>
>>> +static int
>>> +s25hx_t_post_bfpt_fixup(struct spi_nor *nor,
>>> +                     const struct sfdp_parameter_header *bfpt_header,
>>> +                     const struct sfdp_bfpt *bfpt)
>>> +{
>>> +     /* Replace Quad Enable with volatile version */
>>> +     nor->params->quad_enable = cypress_nor_quad_enable_volatile;
>>> +
>>> +     return cypress_nor_set_page_size(nor);
>>> +}
>>> +
>>> +static void s25hx_t_post_sfdp_fixup(struct spi_nor *nor)
>>> +{
>>> +     struct spi_nor_erase_type *erase_type =
>>> +                                     nor->params->erase_map.erase_type;
>>> +     int i;

here should have been unsigned int i;
>>> +
>>> +     /*
>>> +      * In some parts, 3byte erase opcodes are advertised by 4BAIT.
>>> +      * Convert them to 4byte erase opcodes.
>>> +      */
>>> +     for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
>>> +             switch (erase_type[i].opcode) {
>>> +             case SPINOR_OP_SE:
>>> +                     erase_type[i].opcode = SPINOR_OP_SE_4B;
>>> +                     break;
>>> +             case SPINOR_OP_BE_4K:
>>> +                     erase_type[i].opcode = SPINOR_OP_BE_4K_4B;
>>> +                     break;
>>> +             default:
>>> +                     break;
>>> +             }
>>> +     }
>>> +}
>>> +
>>> +static void s25hx_t_late_init(struct spi_nor *nor)
>>> +{
>>> +     struct spi_nor_flash_parameter *params = nor->params;
>>> +
>>> +     /* Fast Read 4B requires mode cycles */
>>> +     params->reads[SNOR_CMD_READ_FAST].num_mode_clocks = 8;
>>> +
>>> +     /* The writesize should be ECC data unit size */
>>> +     params->writesize = 16;
>>> +}
>>> +
>>> +static struct spi_nor_fixups s25hx_t_fixups = {
>>> +     .post_bfpt = s25hx_t_post_bfpt_fixup,
>>> +     .post_sfdp = s25hx_t_post_sfdp_fixup,
>>> +     .late_init = s25hx_t_late_init,
>>> +};
>>> +
>>>  /**
>>>   * cypress_nor_octal_dtr_enable() - Enable octal DTR on Cypress
>>> flashes.
>>>   * @nor:             pointer to a 'struct spi_nor'
>>> @@ -319,6 +435,22 @@ static const struct flash_info
>>> spansion_nor_parts[] = {
>>>       { "s25fl256l",  INFO(0x016019,      0,  64 * 1024, 512)
>>>               NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
>>>               FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
>>> +     { "s25hl512t",  INFO6(0x342a1a, 0x0f0390, 256 * 1024, 256)
>>
>> I know I'm really late, but would this also work with
>> { "s25hl512t",  INFO6(0x342a1a, 0x0f0390, 0, 0)
>>                PARSE_SFDP
>>
>> It seems the former patch will figure out the page size anyway.
> 
> That's sector_size and n_sectors. Probably works, but we'd have
> to change it anyway when the SNOR_ID3 patch is integrated. Plus, it may

maybe SFDP_INFO and SFDP_INFO6 instead of SNOR_ID3?

> confuse people as using zero values for these parameters will make
> BP protection fail. I'd queue this as it is, and we'll ping Takahiro to
> give us a Tested-by tag when converting all these to SNOR_ID3.
> 
> If it sounds fair to you, I'm happy to receive your R-b tag.
> 
> Thanks again for taking the time to review these.
> --
> Cheers,
> ta
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/


-- 
Cheers,
ta
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Re: [PATCH v17 0/7] mtd: spi-nor: Add support for Infineon s25hl-t/s25hs-t

[Tudor Ambarus]

On Mon, 25 Jul 2022 12:24:58 +0300, Tudor Ambarus wrote:
> v17 introduces nor->params->addr_mode_nbytes in order to track the number
> of address bytes of current address mode. This is useful when the flash
> operates with 4B opcodes but needs the internal address mode for opcodes
> that don't have a 4B opcode correspondent. Such an example is the Infineon
> Semper chips which provide 4B opcodes for read/program/erase but do not
> provide 4B opcodes for Read/Write Any Register. These registers are indexed
> by address and require the internal address mode of the flash before
> Read/Write Any Register opcodes are issued.
> 4B opcodes are preferred over changing the flash's address mode to 4byte,
> as set_4byte_addr_mode could be done in a non-volatile way and could break
> the boot sequence. Thus we need to track the flash's internal address mode
> so that we can use the 4B opcodes together with the opcodes that don't
> have a 4B opcode correspondent.
> All other minor comments were addressed as well:
> - s/address width/ address nbytes where needed
> - "mtd: spi-nor: spansion: Add local function to discover page size" no
> longer replaces the hardcoded value of 3 for the number of address bytes.
> - few patches were dropped as they no longer made sense with the
> introduction of nor->params->addr_mode_nbytes.
> 
> [...]

Moved params->addr_mode_nbytes initialization to dedicated line,
s/int i;/unsigned int i; and applied to spi-nor/next, thanks!

[1/7] mtd: spi-nor: s/addr_width/addr_nbytes
      https://git.kernel.org/mtd/c/c452d49849d4
[2/7] mtd: spi-nor: core: Shrink the storage size of the flash_info's addr_nbytes
      https://git.kernel.org/mtd/c/aa5d980a144c
[3/7] mtd: spi-nor: Do not change nor->addr_nbytes at SFDP parsing time
      https://git.kernel.org/mtd/c/47c6f8a67f2c
[4/7] mtd: spi-nor: core: Return error code from set_4byte_addr_mode()
      https://git.kernel.org/mtd/c/08412e72afba
[5/7] mtd: spi-nor: core: Track flash's internal address mode
      https://git.kernel.org/mtd/c/d7931a215063
[6/7] mtd: spi-nor: spansion: Add local function to discover page size
      https://git.kernel.org/mtd/c/a6b50aa12796
[7/7] mtd: spi-nor: spansion: Add s25hl-t/s25hs-t IDs and fixups
      https://git.kernel.org/mtd/c/b6b23833fc42

Best regards,
-- 
Tudor Ambarus <tudor.ambarus@microchip.com>

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