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From: <Tudor.Ambarus@microchip.com>
To: <michael@walle.cc>
Cc: vigneshr@ti.com, richard@nod.at, linux-mtd@lists.infradead.org,
	linux-kernel@vger.kernel.org, miquel.raynal@bootlin.com
Subject: Re: [PATCH] mtd: spi-nor: Add support for at25sl321
Date: Sun, 19 Jan 2020 07:18:29 +0000
Message-ID: <2121499.oPre2Eb8Qh@192.168.0.113> (raw)
In-Reply-To: <20200116160209.20129-1-michael@walle.cc>

On Thursday, January 16, 2020 6:02:09 PM EET Michael Walle wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
> 
> This was tested in single, dual and quad mode on a custom board with the
> NXP FlexSPI controller.
> 
> Signed-off-by: Michael Walle <michael@walle.cc>
> ---
>  drivers/mtd/spi-nor/spi-nor.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index 8226d6450069..94747059344a 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -2332,6 +2332,12 @@ static const struct flash_info spi_nor_ids[] = {
> 
>         { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
> 
> +       /* Adesto (former Atmel) */

All the atmel flashes from above start with Adesto's manufacturer id, 0x1f.
I dropped this comment, ordered the entry alphabetically and applied to spi-
nor/next. Thanks.
ta

> +       {
> +               "at25sl321",  INFO(0x1f4216, 0, 64 * 1024, 64,
> +                       SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
> +       },
> +
>         /* EON -- en25xxx */
>         { "en25f32",    INFO(0x1c3116, 0, 64 * 1024,   64, SECT_4K) },
>         { "en25p32",    INFO(0x1c2016, 0, 64 * 1024,   64, 0) },
> --
> 2.20.1




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Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-16 16:02 Michael Walle
2020-01-19  7:18 ` Tudor.Ambarus [this message]

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