From: Marek Vasut <marex@denx.de>
To: Masahiro Yamada <masahiroy@kernel.org>
Cc: Dinh Nguyen <dinguyen@kernel.org>,
Boris Brezillon <boris.brezillon@collabora.com>,
linux-mtd <linux-mtd@lists.infradead.org>,
Tim Sander <tim@krieglstein.org>,
Miquel Raynal <miquel.raynal@bootlin.com>
Subject: Re: [PATCH] Revert "mtd: rawnand: denali: get ->setup_data_interface() working again"
Date: Wed, 12 Feb 2020 18:44:43 +0100 [thread overview]
Message-ID: <29cce21c-2214-7238-0bc5-db2c1a54576f@denx.de> (raw)
In-Reply-To: <CAK7LNAR4MU+Rfmpz99iwLuEbD4jMwUdh91uz3zyQdvjyLEQcMQ@mail.gmail.com>
On 2/12/20 5:56 PM, Masahiro Yamada wrote:
> Hi.
Hi,
[...]
>>>>>>>>>>> On SoCFPGA, denali->clk_rate = 31.25 MHz and denali->clk_x_rate = 125 MHz,
>>>>>>>>>>> hence the driver sets NAND_KEEP_TIMINGS flag.
>>>
>>>
>>> Interesting.
>>> I have never seen such clock rates before.
>>>
>>>
>>> For all known upstream platforms
>>> (Altera SOCFPGA, Socionext UniPhier, Intel MRST),
>>> the NAND controller core clock is 50 MHz,
>>> the NAND bus clock is 200MHz.
>>
>> You can configure whatever rate you want in the QSys HPS component.
>
> OK.
>
> The SOCFPGA maintainer, Dinh Nguyen, said this:
> "From the clock controller, it provides a single 200MHz clock to the NAND
> IP. Inside the NAND IP, there is a /4 for the clk. The 200MHz clock is
> used for the clk_x and ecc_clk."
That sounds like some root clock. You can read the entire documentation
for the SoCFPGA CV/AV here:
http://www.altera.com/literature/hb/cyclone-v/cv_5v4.pdf
See section 3 , look for 'nand' there. Note that NAND can be supplied
from at least two different PLLs -- main and peripheral.
> http://lists.infradead.org/pipermail/linux-arm-kernel/2018-July/592702.html
>
>
>
> Maybe, you are using a brand-new,
> different type of SOCFPGA?
Cyclone V and Arria V , so no.
>>> What would happen if you hard-code:
>>> denali->clk_rate = 50000000;
>>> denali->clk_x_rate = 200000000;
>>
>> It will not work, because the IP would be using incorrect clock.
>
> I wanted to see the past tense here instead of
> future tense + subjunctive mood.
>
> I wanted you to try it.
>
>
>
>>
>>> like I had already suggested to Tim Sander:
>>> https://lore.kernel.org/lkml/CAK7LNAQOCoJC0RzOhTEofHdR+zU5sQTxV-t4nERBExW1ddW5hw@mail.gmail.com/
>>>
>>> Unfortunately, he did not want to do it, but
>>> I am still interested in this experiment because
>>> I suspect this might be a bug of drivers/clk/socfpga/.
>>
>> No, this is a feature of the platform, you can configure any clock you
>> want pretty much.
>
>
> OK, but if you agree the 4.19.10 is working,
>
> denali->clk_rate = 50000000; denali->clk_x_rate = 200000000;
>
> is worth trying.
Why would misconfiguring the IP be worth trying ?
>>> 4.19.10 kernel (, which Tim Sander agreed the timing was working fine)
>>> was hard-coding them in order to deal with the immature SOCFPGA clock driver.
>>
>> The 4.19 was working fine for Tim (and me as well), because it didn't
>> have this bug which this patch removes.
>
>
> d311e0c27b8fcc27f707f8ca did not exist in 4.19
>
> But, 7a08dbaedd36 did not exist either in 4.19
>
>
> $ git describe 7a08dbae
> v4.20-rc2-34-g7a08dbaedd36
> $ git describe d311e0c
> v5.0-rc2-3-gd311e0c27b8f
>
>
> So, your patch is getting it back to
> v4.20-rc2-34-g7a08dbaedd36
> where the condition for ->setup_data_interface() call
> is accidentally inverted for the Denali driver.
>
>
>
> BTW, did you notice your code was doing the opposite
> to your commit description?
I think Boris / Miquel mentioned that above already.
> Your commit description goes like this:
>
> "On SoCFPGA, denali->clk_rate = 31.25 MHz and denali->clk_x_rate = 125 MHz,
> hence the driver sets NAND_KEEP_TIMINGS flag. This did not happen before
> and is actually incorrect, as on SoCFPGA we do not want to retain timings
> from previous stage (the timings might be incorrect or outright invalid)."
>
>
> You clearly state denali->clk_rate and denali->clk_x_rate
> are non-zero values.
They are non-zero, 31.25 MHz and 125 MHz respectively.
> If this patch were applied, we would end up with NAND_KEEP_TIMINGS set.
> Then ->setup_data_interface() hook would be skipped.
> So, the timings from previous stage would be retained.
>
> Is this what you want to do?
I don't know ? The calculated timings are apparently not working.
> One more thing, if your patch were applied,
> we would get back to the situation
> where the back-trace happens due to zero-division:
>
>
> When denali->clk_x_rate is zero,
> NAND_KEEP_TIMINGS would not be set with your patch.
> So, ->setup_data_interface() would be called.
>
> This would cause zero divion at line 781.
> t_x = DIV_ROUND_DOWN_ULL(1000000000000ULL, denali->clk_x_rate);
If the clock are non-zero, how would this be a division by zero ?
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next prev parent reply other threads:[~2020-02-12 17:45 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-05 7:08 [PATCH] Revert "mtd: rawnand: denali: get ->setup_data_interface() working again" Marek Vasut
2020-02-05 9:12 ` Miquel Raynal
2020-02-05 9:41 ` Marek Vasut
2020-02-05 9:50 ` Miquel Raynal
2020-02-05 10:05 ` Boris Brezillon
2020-02-05 10:08 ` Marek Vasut
2020-02-11 10:04 ` Marek Vasut
2020-02-11 16:07 ` Miquel Raynal
2020-02-11 20:35 ` Marek Vasut
2020-02-12 9:00 ` Masahiro Yamada
2020-02-12 9:37 ` Marek Vasut
2020-02-12 16:56 ` Masahiro Yamada
2020-02-12 17:13 ` Masahiro Yamada
2020-02-12 17:44 ` Marek Vasut [this message]
2020-02-17 8:33 ` Masahiro Yamada
2020-02-18 5:55 ` Masahiro Yamada
2020-02-19 18:42 ` Marek Vasut
2020-02-25 0:41 ` Masahiro Yamada
2020-03-03 17:11 ` Marek Vasut
2020-03-09 10:27 ` Masahiro Yamada
2020-03-11 12:52 ` Marek Vasut
2020-03-11 13:08 ` Miquel Raynal
2020-03-11 13:19 ` Marek Vasut
2020-03-11 13:33 ` Miquel Raynal
2020-03-11 14:07 ` Marek Vasut
2020-03-11 14:39 ` Miquel Raynal
2020-03-14 14:48 ` Marek Vasut
2020-03-17 9:27 ` Masahiro Yamada
2020-03-16 4:36 ` Masahiro Yamada
2020-02-19 18:27 ` Marek Vasut
2020-02-25 0:38 ` Masahiro Yamada
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