From: Marek Vasut <marek.vasut@gmail.com>
To: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Boris Brezillon <bbrezillon@kernel.org>,
Richard Weinberger <richard@nod.at>,
Tudor Ambarus <tudor.ambarus@microchip.com>,
linux-kernel <linux-kernel@vger.kernel.org>,
linux-mtd@lists.infradead.org,
Brian Norris <computersforpeace@gmail.com>,
David Woodhouse <dwmw2@infradead.org>
Subject: Re: [PATCH] mtd: spi-nor: enable 4B opcodes for n25q256a
Date: Fri, 3 May 2019 13:27:39 +0200 [thread overview]
Message-ID: <4ff197be-6ede-6644-d135-b13aab590bb6@gmail.com> (raw)
In-Reply-To: <CAAh8qsyBHCD9o_wyk6cHxyxagpQvX0dtXxy_P4KqZgoeU8VrEg@mail.gmail.com>
On 5/3/19 12:37 PM, Simon Goldschmidt wrote:
> On Fri, May 3, 2019 at 12:00 PM Marek Vasut <marek.vasut@gmail.com> wrote:
>>
>> On 5/3/19 10:53 AM, Simon Goldschmidt wrote:
>>> Tested on socfpga cyclone5 where this is required to ensure that the
>>> boot rom can access this flash after warm reboot.
>>
>> Are you sure _all_ variants of the N25Q256 support 4NB opcodes ?
>> I think there were some which didn't, but I might be wrong.
>
> Oh, damn, you're right. The documentation [1] statest that 4-byte erase and
> program opcodes are only supported for part numbers N25Q256A83ESF40x,
> N25Q256A83E1240x and N25QA83ESFA0F.
;-)
> Any idea of how I can still enable 4-byte opcodes for my chip?
Maybe SFDP tables contains some information whether the chip supports
the 4B opcodes ?
--
Best regards,
Marek Vasut
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prev parent reply other threads:[~2019-05-03 11:27 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-03 8:53 [PATCH] mtd: spi-nor: enable 4B opcodes for n25q256a Simon Goldschmidt
2019-05-03 10:00 ` Marek Vasut
2019-05-03 10:37 ` Simon Goldschmidt
2019-05-03 11:27 ` Marek Vasut [this message]
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