From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
To: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org,
Chris Brandt <chris.brandt@renesas.com>,
Mason Yang <masonccyang@mxic.com.tw>,
linux-mtd@lists.infradead.org, linux-spi@vger.kernel.org
Subject: Re: [PATCH v2 1/2] dt-bindings: memory: document Renesas RPC-IF bindings
Date: Wed, 20 May 2020 17:38:12 +0300 [thread overview]
Message-ID: <5359d5a2-5d28-058e-ce37-bc91e1aa7988@cogentembedded.com> (raw)
In-Reply-To: <20200501212547.GB15294@bogus>
On 02.05.2020 0:25, Rob Herring wrote:
>> Renesas Reduced Pin Count Interface (RPC-IF) allows a SPI flash or
>> HyperFlash connected to the SoC to be accessed via the external address
>> space read mode or the manual mode.
>>
>> Document the device tree bindings for the Renesas RPC-IF found in the R-Car
>> gen3 SoCs.
>>
>> Based on the original patch by Mason Yang <masonccyang@mxic.com.tw>.
>>
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>>
>> ---
>> Changes in version 2:
>> - rewrote the bindings in YAML.
>>
>> Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml | 88 ++++++++++
>
> Not where we normally put SPI flash controllers...
RPC-IF is not exactly SPI flash controller, it's bimodal.
MBR, Sergei
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next prev parent reply other threads:[~2020-05-20 14:38 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-30 20:45 [PATCH v2 0/2] Add Renesas RPC-IF support Sergei Shtylyov
2020-04-30 20:47 ` [PATCH v2 1/2] dt-bindings: memory: document Renesas RPC-IF bindings Sergei Shtylyov
2020-05-01 21:19 ` Rob Herring
2020-05-15 20:16 ` Sergei Shtylyov
2020-05-01 21:25 ` Rob Herring
2020-05-20 14:38 ` Sergei Shtylyov [this message]
2020-06-01 19:18 ` Sergei Shtylyov
2020-04-30 20:50 ` [PATCH v2 2/2] memory: add Renesas RPC-IF driver Sergei Shtylyov
2020-05-01 9:36 ` [PATCH v2 0/2] Add Renesas RPC-IF support Geert Uytterhoeven
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