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Tue, 27 Aug 2019 02:48:05 -0500 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 27 Aug 2019 02:48:05 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 27 Aug 2019 02:48:05 -0500 Received: from [172.24.145.136] (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x7R7m0h6129701; Tue, 27 Aug 2019 02:48:02 -0500 Subject: Re: [RESEND PATCH v3 16/20] mtd: spi-nor: Add the SPI_NOR_XSR_RDY flag To: , , , , , , References: <20190826120821.16351-1-tudor.ambarus@microchip.com> <20190826120821.16351-17-tudor.ambarus@microchip.com> From: Vignesh Raghavendra Message-ID: <6c4c1b43-426d-75c9-126d-f60c0af0e956@ti.com> Date: Tue, 27 Aug 2019 13:18:38 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <20190826120821.16351-17-tudor.ambarus@microchip.com> Content-Language: en-US X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190827_004810_781249_C33D558C X-CRM114-Status: GOOD ( 19.30 ) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: boris.brezillon@bootlin.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org On 26/08/19 5:39 PM, Tudor.Ambarus@microchip.com wrote: > From: Boris Brezillon > > S3AN flashes use a specific opcode to read the status register. > We currently use the SPI_S3AN flag to decide whether this specific > SR read opcode should be used, but SPI_S3AN is about to disappear, so > let's add a new flag. > > Note that we use the same bit as SPI_S3AN implies SPI_NOR_XSR_RDY and > vice versa. > > Signed-off-by: Boris Brezillon > Signed-off-by: Tudor Ambarus > --- Reviewed-by: Vignesh Raghavendra Regards Vignesh > v3: no changes > > drivers/mtd/spi-nor/spi-nor.c | 10 +++++++++- > 1 file changed, 9 insertions(+), 1 deletion(-) > > diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c > index edf1c8badac9..2699e999d21a 100644 > --- a/drivers/mtd/spi-nor/spi-nor.c > +++ b/drivers/mtd/spi-nor/spi-nor.c > @@ -211,6 +211,14 @@ struct flash_info { > * bit. Must be used with > * SPI_NOR_HAS_LOCK. > */ > +#define SPI_NOR_XSR_RDY BIT(10) /* > + * S3AN flashes have specific opcode to > + * read the status register. > + * Flags SPI_NOR_XSR_RDY and SPI_S3AN > + * use the same bit as one implies the > + * other, but we will get rid of > + * SPI_S3AN soon. > + */ > #define SPI_S3AN BIT(10) /* > * Xilinx Spartan 3AN In-System Flash > * (MFR cannot be used for probing > @@ -4798,7 +4806,7 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, > * spi_nor_wait_till_ready(). Xilinx S3AN share MFR > * with Atmel spi-nor > */ > - if (info->flags & SPI_S3AN) > + if (info->flags & SPI_NOR_XSR_RDY) > nor->flags |= SNOR_F_READY_XSR_RDY; > > if (info->flags & SPI_NOR_HAS_LOCK) > -- Regards Vignesh ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/