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From: tkuw584924@gmail.com
To: linux-mtd@lists.infradead.org
Cc: tudor.ambarus@microchip.com, pratyush@kernel.org,
	michael@walle.cc, miquel.raynal@bootlin.com, richard@nod.at,
	vigneshr@ti.com, tkuw584924@gmail.com, Bacem.Daassi@infineon.com,
	Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Subject: [PATCH 7/8] mtd: spi-nor: spansion: Introduce DEF_4BAM mfr flag
Date: Sat,  6 Aug 2022 15:34:25 +0900	[thread overview]
Message-ID: <6cbf3bc0e8908d6e907bd8c705ce9376765837ba.1659764848.git.Takahiro.Kuwano@infineon.com> (raw)
In-Reply-To: <cover.1659764848.git.Takahiro.Kuwano@infineon.com>

From: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>

The params->addr_mode_nbytes is set to 3 during BFPT parse in case of
BFPT_DWORD1_ADDRESS_BYTES_3_OR_4. Infineon SEMPER multi-chip devices are
in 4-byte address mode by factory default. A new manufacturer flag,
DEF_4BAM is introduced for such devices to fix the
params->addr_mode_nbytes to 4 in post_bfpt_fixup().

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
---
 drivers/mtd/spi-nor/spansion.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
index fc9cc3484aa3..22b0be5d312b 100644
--- a/drivers/mtd/spi-nor/spansion.c
+++ b/drivers/mtd/spi-nor/spansion.c
@@ -10,6 +10,7 @@
 
 /* flash_info mfr_flag. Used to clear sticky prorietary SR bits. */
 #define USE_CLSR	BIT(0)
+#define DEF_4BAM	BIT(1)	/* 4-byte address mode by default */
 
 #define SPINOR_OP_CLSR		0x30	/* Clear status register 1 */
 #define SPINOR_OP_RD_ANY_REG			0x65	/* Read any register */
@@ -581,6 +582,17 @@ static int spansion_nor_sr_ready_and_clear(struct spi_nor *nor)
 	return !(nor->bouncebuf[0] & SR_WIP);
 }
 
+static int
+spansion_post_bfpt_fixup(struct spi_nor *nor,
+			 const struct sfdp_parameter_header *bfpt_header,
+			 const struct sfdp_bfpt *bfpt)
+{
+	if (nor->info->mfr_flags & DEF_4BAM)
+		nor->params->addr_mode_nbytes = 4;
+
+	return 0;
+}
+
 static void spansion_nor_late_init(struct spi_nor *nor)
 {
 	if (nor->params->size > SZ_16M) {
@@ -595,6 +607,7 @@ static void spansion_nor_late_init(struct spi_nor *nor)
 }
 
 static const struct spi_nor_fixups spansion_nor_fixups = {
+	.post_bfpt = spansion_post_bfpt_fixup,
 	.late_init = spansion_nor_late_init,
 };
 
-- 
2.25.1


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  parent reply	other threads:[~2022-08-06  6:36 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-06  6:34 [PATCH 0/8] mtd: spi-nor: Add support for Infineon SEMPER s25hl02gt and s25hs02gt tkuw584924
2022-08-06  6:34 ` [PATCH 1/8] mtd: spi-nor: core: Introduce number of dice and volatile register offset params tkuw584924
2022-08-06  6:34 ` [PATCH 2/8] mtd: spi-nor: sfdp: Extract volatile register offset from SCCR map tkuw584924
2022-08-06  6:34 ` [PATCH 3/8] mtd: spi-nor: sfdp: Add support for SCCR map for multi-chip device tkuw584924
2022-08-06  6:34 ` [PATCH 4/8] mtd: spi-nor: spansion: Rework cypress_nor_set_page_size() for multi-chip device support tkuw584924
2022-08-06  6:34 ` [PATCH 5/8] mtd: spi-nor: spansion: Rework cypress_nor_quad_enable_volatile() " tkuw584924
2022-08-10 14:40   ` Takahiro Kuwano
2022-08-06  6:34 ` [PATCH 6/8] mtd: spi-nor: spansion: Add a new ->ready() hook for multi-chip device tkuw584924
2022-08-06  6:34 ` tkuw584924 [this message]
2022-08-06  6:34 ` [PATCH 8/8] mtd: spi-nor: spansion: Add support for Infineon tkuw584924
2022-08-08  4:47   ` Tudor.Ambarus
2022-08-08  5:42     ` Takahiro Kuwano
2022-08-08  6:08       ` Tudor.Ambarus
2022-08-08  6:41         ` Takahiro Kuwano
2022-08-08  7:34           ` Tudor.Ambarus
2022-08-08  8:09             ` Takahiro Kuwano
2022-08-08  8:26               ` Tudor.Ambarus
2022-08-08  8:31                 ` Takahiro Kuwano
2022-08-12  8:15                   ` Takahiro Kuwano

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