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From: <Tudor.Ambarus@microchip.com>
To: <js07.lee@samsung.com>
Cc: michael@walle.cc, linux-mtd@lists.infradead.org, vigneshr@ti.com
Subject: Re: [PATCH v3 4/5] mtd: spi-nor: Add SR 4bit block protection support
Date: Mon, 23 Mar 2020 12:55:40 +0000
Message-ID: <8548006.u9pkoXE8D1@192.168.0.120> (raw)
In-Reply-To: <26331bf950dc9945aad93f874dcf15d639fe3424.camel@samsung.com>

On Monday, March 23, 2020 2:43:09 PM EET Jungseung Lee wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
> 
> Hi,

Hi, Jungseung,
> 
> On Mon, 2020-03-23 at 09:24 +0000, Tudor.Ambarus@microchip.com wrote:
> > From: Jungseung Lee <js07.lee@samsung.com>
> > 
> > Currently, we are supporting block protection only for flash chips
> > with
> > 3 block protection bits (BP0-2) in the SR register.
> > 
> > Enable block protection support for flashes with 4 block protection
> > bits
> > (BP0-3).
> > 
> > Add a flash_info flag for flashes that describe 4 block protection
> > bits.
> > Add another flash_info flag for flashes in which BP3 bit is not
> > adjacent
> > to the BP0-2 bits.
> > 
> > Signed-off-by: Jungseung Lee <js07.lee@samsung.com>
> > Reviewed-by: Michael Walle <michael@walle.cc>
> > Tested-by: Michael Walle <michael@walle.cc>
> > [ta:
> > - introduce spi_nor_get_sr_bp_mask(), spi_nor_get_sr_tb_mask()
from the previous patch set
> > - drop Micron n25q512ax3 / BP0-3) boilerplate description
> > - be explicit in spi_nor_get_locked_range_sr aboyt SR_BP3 as Michael
> > suggested,
> > - amend commit description]

I'll drop these comments when/if applying. Let me know if you're ok with the 
changes that I did. Please do the same for patches 3/5 and 5/5.

> > Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
> > ---
> > 
> >  drivers/mtd/spi-nor/core.c  | 66 +++++++++++++++++++++++++++------
> > 
> > ----
> > 
> >  drivers/mtd/spi-nor/core.h  | 10 ++++++
> >  include/linux/mtd/spi-nor.h |  2 ++
> >  3 files changed, 60 insertions(+), 18 deletions(-)

cut

> Tested with a n25q512ax3 (bp0-3) and w25q128 (bp0-2).
> It passed all of my test cases.
> 
> Tested-by: Jungseung Lee <js07.lee@samsung.com>

Great! Since you are the author of the patch, it's not necessary to add your 
T-b tag, but I'll amend the commit description to say that it was tested on 
n25q512ax3 (bp0-3) and w25q128 (bp0-2).

Also, would you please review patches 1 and 2 from the series?

Cheers,
ta


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Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-23  9:24 [PATCH v3 0/5] " Tudor.Ambarus
2020-03-23  9:24 ` [PATCH v3 1/5] mtd: spi-nor: Fix gap in SR block protection locking Tudor.Ambarus
2020-03-23 18:27   ` Michael Walle
2020-03-23 19:20     ` Tudor.Ambarus
2020-03-23 19:54       ` Michael Walle
2020-03-23 20:26         ` Tudor.Ambarus
2020-03-23 21:14           ` Michael Walle
2020-03-23 21:30             ` Tudor.Ambarus
2020-03-23 21:33               ` Tudor.Ambarus
2020-03-23 22:35               ` Michael Walle
2020-03-24  5:37                 ` Tudor.Ambarus
2020-03-24  3:52   ` Jungseung Lee
2020-03-25  9:44   ` Tudor.Ambarus
2020-03-23  9:24 ` [PATCH v3 2/5] mtd: spi-nor: Set all BP bits to one when lock_len == mtd->size Tudor.Ambarus
2020-03-23 14:08   ` Jungseung Lee
2020-03-23 18:28   ` Michael Walle
2020-03-23  9:24 ` [PATCH v3 3/5] mtd: spi-nor: Add new formula for SR block protection handling Tudor.Ambarus
     [not found]   ` <000001d600ff$063a8fd0$12afaf70$@samsung.com>
2020-03-23 13:32     ` Jungseung Lee
2020-03-23  9:24 ` [PATCH v3 4/5] mtd: spi-nor: Add SR 4bit block protection support Tudor.Ambarus
2020-03-23 12:43   ` Jungseung Lee
2020-03-23 12:55     ` Tudor.Ambarus [this message]
2020-03-23 13:16       ` Jungseung Lee
2020-03-23 18:33   ` Michael Walle
2020-03-23 18:51     ` Tudor.Ambarus
2020-03-23  9:24 ` [PATCH v3 4/5] mtd: spi-nor: Add 4bit SR " Tudor.Ambarus
2020-03-23  9:46   ` Tudor.Ambarus
2020-03-23  9:24 ` [PATCH v3 5/5] mtd: spi-nor: Enable locking for n25q512ax3/n25q512a Tudor.Ambarus

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