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From: <Tudor.Ambarus@microchip.com>
To: <john.garry@huawei.com>, <linux-mtd@lists.infradead.org>
Cc: broonie@kernel.org, fengsheng5@huawei.com
Subject: Re: flash_lock issue for n25q 128mb spi nor part
Date: Tue, 3 Dec 2019 14:44:59 +0000
Message-ID: <9d41bfca-f4e3-beb2-ff7f-78be49e8d80e@microchip.com> (raw)
In-Reply-To: <b73c8a25-a58d-a1f1-f68c-0ba35a5c7c51@huawei.com>


> Hi Tudor,

Hi, John,

> 
> Something else which I wanted to ask is why we don't check the FSR after
> a write command for that part?

no particular reason, no one asked for it :).

> 
> Without it, if the flash is locked, a flash write reports no error,
> which could be maybe misleading.

true

> 
> A more real problem is that I find that SR.WEL is not cleared when we
> attempt to write when the flash is locked, and this causes issues when
> we attempt to reset the SR.
> 
> Here's an example flow (with my hack to stop using 16b SR method):
> 
> root@ubuntu:/home/john# flash_lock -l /dev/mtd0
> root@ubuntu:/home/john# mtd_debug erase /dev/mtd0 0xe00000 4096
> [   69.650642] spi-nor spi-PRP0001:00: at 0xe00000, len 4096
> Erased 4096 bytes from address 0x00e00000 in flash
> root@ubuntu:/home/john# mtd_debug write /dev/mtd0 0xe00000 4096 dump4096
> [   77.093755] spi-nor spi-PRP0001:00: to 0x00e00000, len 4096
> Copied 4096 bytes from dump4096 to address 0x00e00000 in flash
> root@ubuntu:/home/john# mtd_debug read /dev/mtd0 0xe00000 4096 temp
> [   82.162445] spi-nor spi-PRP0001:00: from 0x00e00000, len 4096
> Copied 4096 bytes from address 0x00e00000 in flash to temp
> root@ubuntu:/home/john# flash_lock -u /dev/mtd0
> [   87.558435] spi-nor spi-PRP0001:00: SR1: read back test failed
> flash_lock: error!: could not unlock device: /dev/mtd0
> 
>             error 5 (Input/output error)
> root@ubuntu:/home/john#
> 
> Unlock reports an error as the the read back test in
> spi_nor_write_sr1_and_check() fails as the SR.WEL has never been cleared.
> 

Interesting.


Does the following do the trick?

-       { "n25q128a11",  INFO(0x20bb18, 0, 64 * 1024,  256, SECT_4K |
SPI_NOR_QUAD_READ) },
+       { "n25q128a11",  INFO(0x20bb18, 0, 64 * 1024,  256, SECT_4K | USE_FSR |
+                             SPI_NOR_QUAD_READ) },

This can of course be extended to all micron flashes, if all support FSR, but
some documentation work has to be made.

> I'm just saying this while it's fresh in my head - I don't want to seem
> pushy :)

No worries, this is a good initiative, thanks.

Cheers,
ta
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Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-12-02 17:28 John Garry
2019-12-03  9:45 ` Tudor.Ambarus
2019-12-03 10:31   ` John Garry
2019-12-03 11:07     ` Tudor.Ambarus
2019-12-03 11:44       ` John Garry
2019-12-03 12:05         ` Tudor.Ambarus
2019-12-03 12:27           ` Tudor.Ambarus
2019-12-03 12:35             ` John Garry
2019-12-03 13:57               ` John Garry
2019-12-03 14:44                 ` Tudor.Ambarus [this message]
2019-12-03 15:29                   ` John Garry
2019-12-04 11:10                     ` John Garry
2019-12-03 14:16               ` [PATCH] mtd: spi-nor: Fix the write Status Register on micron flashes Tudor.Ambarus
2019-12-03 14:50                 ` [PATCH v2] mtd: spi-nor: Fix the writing of the " Tudor.Ambarus
2019-12-04 10:18                   ` John Garry

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