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From: Tokunori Ikegami <>
To: Sergei Shtylyov <>,
	David Woodhouse <>,
	Brian Norris <>,
	Marek Vasut <>,
	Miquel Raynal <>,
	Richard Weinberger <>,
	Vignesh Raghavendra <>,
Subject: Re: [PATCH 2/2] mtd: cfi_cmdset_0002: fix delayed error detection on HyperFlash
Date: Sun, 13 Oct 2019 12:35:24 +0900
Message-ID: <> (raw)
In-Reply-To: <>


>>>            if (chipstatus & CFI_SR_SLSB)
>>>                pr_err("%s sector write protected, status %lx\n",
>>>                       map->name, chipstatus);
>>> +        return 1;
>> Is it okay to be returned 1 for the errors CFI_SR_WBASB and CFI_SR_SLSB also?
>> Before the change only CFI_Well, SR_ESB and CFI_SR_PSB were checked by chip_good().
>     Well, pr_err() calls above spoke for themselves: all bitmask 0x3a was considered
> the error bits. But I can change that back to just ESB/PSB if preferred.
It was mentioned before as it is enough to see if ESB or PSB is set to 
know if write or erase failed.
>     It's better to remove the diff you're not commenting to.

Noted it.


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Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-03 18:29 [PATCH 0/2] Fix the HyperFlash support in the AMD/Fujitsu/Spansion CFI driver Sergei Shtylyov
2019-10-03 18:32 ` [PATCH 1/2] mtd: cfi_cmdset_0002: only check errors when ready in cfi_check_err_status() Sergei Shtylyov
2019-10-03 18:34 ` [PATCH 2/2] mtd: cfi_cmdset_0002: fix delayed error detection on HyperFlash Sergei Shtylyov
2019-10-06 20:54   ` Tokunori Ikegami
2019-10-11 12:03     ` Sergei Shtylyov
2019-10-13  3:35       ` Tokunori Ikegami [this message]
2019-10-16  6:33   ` Vignesh Raghavendra
2019-10-28 19:15     ` Sergei Shtylyov
2019-10-30 15:35       ` Vignesh Raghavendra

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