From: JH <jupiter.hce@gmail.com>
To: Boris Brezillon <boris.brezillon@collabora.com>
Cc: linux-mtd <linux-mtd@lists.infradead.org>
Subject: Re: mtd_nandbiterrs errors
Date: Thu, 6 Feb 2020 11:20:37 +1100 [thread overview]
Message-ID: <CAA=hcWT+veAKUUKyJSZEx-mtoPAMzPhzd=gd8XtPq-NbrC9TMQ@mail.gmail.com> (raw)
In-Reply-To: <20200205212301.1e26c263@collabora.com>
Hi Boris,
Thanks for the response.
On 2/6/20, Boris Brezillon <boris.brezillon@collabora.com> wrote:
> On Wed, 5 Feb 2020 22:28:50 +1100
> JH <jupiter.hce@gmail.com> wrote:
>
>> Resolved, using kernel test probably a bad idea, change to use
>> mtd-utils nandbiterrs resolved issue.
>
> I doubt it solved the real problem: ECC is not working properly.
You are right, I was working and posted at middle night, my brain was
not functional well. Let me try it again to clarify it.
# nandbiterrs -i /dev/mtd2
incremental biterrors test
Successfully corrected 0 bit errors per subpage
Inserted biterror @ 1/7
Read reported 1 corrected bit errors
Successfully corrected 1 bit errors per subpage
Inserted biterror @ 3/7
Read reported 2 corrected bit errors
Successfully corrected 2 bit errors per subpage
Inserted biterror @ 5/7
Failed to recover 1 bitflips
Read error after 3 bit errors per page
It did have errors after reading 3 bit errors per page. Could it be
ECC strength not be set up correctly?
I did not set up ECC strength, how can I check the ECC strength bit? I
run the nandbiterrs --help, it did not tell me which option I could
check ECC strength bits.
Also, how to set up ECC strength bits?
Sorry for all rudimentary questions.
>> > [ 695.257984] mtd_nandbiterrs: Inserted biterror @ 0/0
>> > [ 695.262984] mtd_nandbiterrs: rewrite page
>> > [ 695.273646] mtd_nandbiterrs: read_page
>> > [ 695.280000] mtd_nandbiterrs: Read reported 2 corrected bit errors
>
> The ECC engine should report an uncorrectable error here, not 2
> corrected bits. BTW, an ECC of 2bits/512bytes sounds weak for a 2k-page
> NAND. What's the NAND part you're testing with?
I am currently testing a test unit that is using W29N02GVSIAA, it will
change to Samsung : K9F2G08U0D-SCB0 in the future, I have no idea why
the hardware contractor uses two different parts in development and in
product.
Sorry to repeat my questions above again, how to run nandbiterrs to
read ECC strength bit? And how to run nandbiterrs or other command to
set ECC strength bit? I thought that default should be 4 bits, I have
never set it up here, have no idea why it was 2 bits.
Thank you so much.
Kind regards,
- jh
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next prev parent reply other threads:[~2020-02-06 0:20 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-04 12:32 mtd_nandbiterrs errors JH
2020-02-05 11:28 ` JH
2020-02-05 20:23 ` Boris Brezillon
2020-02-06 0:20 ` JH [this message]
2020-02-06 2:03 ` Steve deRosier
2020-02-06 6:42 ` JH
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