From: Jungseung Lee <js07.lee@gmail.com>
To: Tudor.Ambarus@microchip.com
Cc: michael@walle.cc, chenxiang66@hisilicon.com,
linux-mtd@lists.infradead.org, vigneshr@ti.com,
Jungseung Lee <js07.lee@samsung.com>
Subject: Re: [PATCH 1/3] mtd: spi-nor: reimplement block protection handling
Date: Sat, 14 Mar 2020 02:20:48 +0900 [thread overview]
Message-ID: <CAPP0e=MOKw+O=q-PjfrEQo66HSU0zy42O_9=WHmHadYx_d6mfA@mail.gmail.com> (raw)
In-Reply-To: <2264052.42fd6meZLV@192.168.1.3>
Hi, Tudor,
On Sat, Mar 14, 2020 at 12:22 AM <Tudor.Ambarus@microchip.com> wrote:
>
> Hi, Jungseung,
>
> I'm going to respin your patches on top on the what will be the manufacturer
> move v2 series, https://patchwork.ozlabs.org/cover/1247794/, I want both
> included for next.
>
> On Wednesday, March 4, 2020 1:07:58 PM EET Jungseung Lee wrote:
> > The current mainline locking was restricted and could only be applied
> > to flashes that has 3 block protection bit and fixed locking ratio.
> >
> > A new method of normalization was reached at the end of the discussion [1].
> >
> > (1) - if bp slot is insufficient.
> > (2) - if bp slot is sufficient.
> >
> > if (bp_slots_needed > bp_slots) // (1)
> > min_prot_length = sector_size << (bp_slots_needed - bp_slots);
> > else // (2)
> > min_prot_length = sector_size;
> >
> > This patch changes block protection handling logic based on min_prot_length.
> > It is suitable for the overall flashes with exception of some corner case
>
> What corner case, do you refer to EON? Are you aware of other corner cases? We
> should be more precise, for easier review and understanding.
>
Yes, that is eon. eon is the only corner case I've ever seen in 3 bit
and 4 bit block protection.
In 2 bit block protection case, a significant number of flash fully
use available bp_slots (2 bit = 4) regardless of the above rule.
That is the case with microchip, catalyst and more..
Of course, none of the 2 bit block protection flash has been set to
lockable so far.
Thanks,
> Cheers,
> ta
>
> > and easy to extend and apply for the case of 2bit or 4bit block protection.
> >
> > [1] http://lists.infradead.org/pipermail/linux-mtd/2020-February/093934.html
>
>
>
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prev parent reply other threads:[~2020-03-13 17:22 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20200304110830epcas1p168bd480847959dc497ac5cc272fa2f80@epcas1p1.samsung.com>
2020-03-04 11:07 ` [PATCH 1/3] mtd: spi-nor: reimplement block protection handling Jungseung Lee
[not found] ` <CGME20200304110833epcas1p42958d6dce0081afabfdd4200258eddb8@epcas1p4.samsung.com>
2020-03-04 11:07 ` [PATCH 2/3] mtd: spi-nor: add 4bit block protection support Jungseung Lee
2020-03-13 16:24 ` Michael Walle
2020-03-17 11:00 ` Jungseung Lee
2020-03-17 11:35 ` Jungseung Lee
2020-03-17 14:52 ` Michael Walle
2020-03-18 6:01 ` Jungseung Lee
[not found] ` <CGME20200304110835epcas1p3a9daac6383c7ae2fa57a084d4992d5a9@epcas1p3.samsung.com>
2020-03-04 11:08 ` [PATCH 3/3] mtd: spi-nor: support lock/unlock for a few Micron chips Jungseung Lee
[not found] ` <3b7e6d52-e7e2-c444-1d59-5225a7260ea4@hisilicon.com>
2020-03-07 8:24 ` [PATCH 1/3] mtd: spi-nor: reimplement block protection handling Jungseung Lee
2020-03-09 7:50 ` chenxiang (M)
2020-03-09 11:20 ` Jungseung Lee
2020-03-09 11:44 ` Jungseung Lee
2020-03-14 9:58 ` chenxiang (M)
2020-03-14 13:50 ` Jungseung Lee
2020-03-16 7:21 ` chenxiang (M)
2020-03-18 7:17 ` Jungseung Lee
2020-03-13 15:21 ` Tudor.Ambarus
2020-03-13 17:20 ` Jungseung Lee [this message]
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