From: Takahiro Kuwano <tkuw584924@gmail.com>
To: Tudor.Ambarus@microchip.com, michael@walle.cc
Cc: linux-mtd@lists.infradead.org, miquel.raynal@bootlin.com,
richard@nod.at, vigneshr@ti.com, p.yadav@ti.com,
Bacem.Daassi@infineon.com, Takahiro.Kuwano@infineon.com
Subject: Re: [PATCH v15 6/8] mtd: spi-nor: Retain nor->addr_width at 4BAIT parse
Date: Fri, 22 Jul 2022 13:00:35 +0900 [thread overview]
Message-ID: <a035a1a3-0d82-48ab-5d09-1d5164999890@gmail.com> (raw)
In-Reply-To: <c42d5930-73cd-6dbe-f650-db72f35188a5@microchip.com>
On 7/22/2022 1:06 AM, Tudor.Ambarus@microchip.com wrote:
> On 5/23/22 10:49, Michael Walle wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> Am 2022-05-14 05:51, schrieb Takahiro Kuwano:
>>> On 5/13/2022 6:40 PM, Michael Walle wrote:
>>>> [btw the subject still has the old name of the addr_width]
>>>>
>>> Yes, it must be fixed in next rev.
>>>
>>>> Am 2022-05-13 03:26, schrieb Takahiro Kuwano:
>>>>> On 5/13/2022 7:14 AM, Michael Walle wrote:
>>>>>> Am 2022-05-10 00:10, schrieb tkuw584924@gmail.com:
>>>>>>> From: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
>>>>>>>
>>>>>>> In 4BAIT parse, keep nor->params->addr_width because it may be used
>>>>>>> as
>>>>>>> current address mode in SMPT parse later on.
>>>>>>
>>>>>> Mh I'm not sure this is needed at all.
>>>>>>
>>>>>> SFDP spec says
>>>>>> Variable address length (the current setting of the address
>>>>>> length mode defines the address length)
>>>>>>
>>>>>> and
>>>>>> When the length is defined as variable, the software or hardware
>>>>>> controlling the memory is aware of the address length mode last
>>>>>> set in the memory device and this same length of address.
>>>>>>
>>>>>> We don't set any address mode until all the SFDP parsing is
>>>>>> over. Therefore we should always be in 3 byte mode, no?
>>>>>>
>>>>> Actually there are some devices that have variable address length but
>>>>> 4 byte mode by default (I will work on those devices after this
>>>>> series
>>>>> is settled). To support such case, I prefer to use
>>>>> params->addr_nbytes
>>>>> as current address mode so that I can fix it in post_bfpt_fixup()
>>>>> hook.
>>>>
>>>> Are there public datasheets available? So these devices have a 3 byte
>>> I will send datasheets to you in another email. At this point, only
>>> summary datasheet is available in website.
>>>
>>>> and a 4 byte mode, but after reset, they are in the 4 byte mode? Looks
>>> Yes.
>>>
>>>> like it should be fixed in a different way. I'm not sure the "current
>>>> mode" handling is correct.
>>>>
>>> Yes, we may want to introduce a new flag like SPI_NOR_4BAM_DEFAULT and
>>> check
>>> the flag in BFPT parse. Once I send another series, please review.
>>>
>>>> We need to differentiate between the mode the flash currently is using
>>>> (nor->addr_nbytes) and the mode parsed by SFDP (params->addr_nbytes).
>>>>
>>> The flash's address mode affects the address length of Non-4B opcodes,
>>> including read/write any register ops used in SMPT parse and Infineon
>>> (spansion) specific hooks.
>>>
>>> The 4B opcodes always take address length of 4 regardless of flash's
>>> address mode. In these Infineon chips, 4B opcodes for read/program/
>>> erase are available and 4BAIT advertises them. We don't have to enter
>>> 4 byte address mode for read/program/erase.
>>
>> btw. this is a pity. you are using the stateless 4b opcodes but
>> then you don't provide stateless opcodes for the read any register
>> op :/
>>
>>> So, I think we need to differentiate between address length for
>>> read/program/erase and flash's default address mode.
>>
>> Or we keep them in sync. E.g. switch to 4bytes mode if we are
>> using the 4 byte. Granted, that sounds like a hack :)
>>
>>> Obviously we are using nor->addr_nbytes as address length for read/
>>> program/erase and should keep this usage.
>>
>> Yes, I wasn't aware that we actually two different runtime
>> parameters:
>> - the read/program/erase address width, also used with the
>> 4b opcodes
>> - internal mode 3b/4b. Up until now, this wasn't an issue
>> because either the mode was switched or the 4b opcodes
>> were used. So this was mutually exclusive. Now we have
>> flashes which uses 4b opcodes _and_ we need the state
>> of the internal mode.
>>
>> I can't think of a good solution for now. Need to think
>> more about this, but I'm pretty busy at the moment.
>> What I think is clear is that we need two different modes
>> here in the spi_nor struct. nor->addr_nbytes for the
>> read/program/erase opcodes and nor->address_mode or similar
>> which tracks the SPI flash's internal address mode.
>
> Hi, Takahiro,
>
> Can we determine the flash's internal address mode by querying
> the flash at run-time? Is this possible on Semper flashes?
>
CFR2V[7] has current address mode, but to read that, we need to
issue Read Any Register which address length relies on current
address mode. Chicken-and-egg...
> To extend the idea, when the flash supports BFPT and defines
> BFPT_DWORD1_ADDRESS_BYTES_3_ONLY or BFPT_DWORD1_ADDRESS_BYTES_4_ONLY
> the things are clear, addr_nbytes is fixed.
> If the flash does not define BFPT or uses
> BFPT_DWORD1_ADDRESS_BYTES_3_OR_4, then we could determine the addr
> mode by querying the flash.
>
>>
>>> For flash's default address mode, my preference is to use
>>> params->addr_nbytes, but I should rename it to something like
>>> params->def_addr_nbytes and rework spi_nor_set_addr_nbytes().
>>
>> IMHO params should only be used to store the parsed (or
>> hardcoded) parameters.
>
> yep, I share Michael's opinion.
>
> Cheers,
> ta
>
>>
>> -michael
>>
>>> static int spi_nor_set_addr_nbytes(struct spi_nor *nor)
>>> {
>>> if (nor->flags & SNOR_F_HAS_4BAIT) {
>>> nor->addr_nbytes = 4;
>>> } else if (nor->params->def_addr_nbytes) {
>>> nor->addr_nbytes = nor->params->def_addr_nbytes;
>>>
>>>> At some point, the mode is switched and nor->addr_nbytes becomes
>>>> params->addr_nbytes. It seems in your case nor->addr_nbytes should
>>>> be 4 right from the beginning. Which also means nor->addr_nbytes
>>>> should be 3 for the other cases (and probably not 0).
>>>>
>>> With param->def_addr_nbytes, I think we can keep nor->addr_nbytes = 0
>>> during SFDP parse.
>>>
>>> Thanks,
>>> Takahiro
>
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next prev parent reply other threads:[~2022-07-22 4:01 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-09 22:10 [PATCH v15 0/8] mtd: spi-nor: Add support for Infineon s25hl-t/s25hs-t tkuw584924
2022-05-09 22:10 ` [PATCH v15 1/8] mtd: spi-nor: s/addr_width/addr_nbytes tkuw584924
2022-05-12 21:01 ` Michael Walle
2022-05-31 11:13 ` Pratyush Yadav
2022-05-09 22:10 ` [PATCH v15 2/8] mtd: spi-nor: core: Shrink the storage size of the flash_info's addr_nbytes tkuw584924
2022-05-12 21:22 ` Michael Walle
2022-05-31 11:14 ` Pratyush Yadav
2022-05-09 22:10 ` [PATCH v15 3/8] mtd: spi-nor: sfdp: Clarify that nor->read_{opcode, dummy} are uninitialized tkuw584924
2022-05-12 21:33 ` Michael Walle
2022-05-12 21:38 ` Michael Walle
2022-05-31 11:18 ` Pratyush Yadav
2022-05-09 22:10 ` [PATCH v15 4/8] mtd: spi-nor: Do not change nor->addr_nbytes at SFDP parsing time tkuw584924
2022-05-12 21:45 ` Michael Walle
2022-05-31 11:30 ` Pratyush Yadav
2022-07-21 14:32 ` Tudor.Ambarus
2022-07-21 15:02 ` Tudor.Ambarus
2022-05-09 22:10 ` [PATCH v15 5/8] mtd: spi-nor: core: Couple the number of address bytes with the address mode tkuw584924
2022-05-12 22:07 ` Michael Walle
2022-05-09 22:10 ` [PATCH v15 6/8] mtd: spi-nor: Retain nor->addr_width at 4BAIT parse tkuw584924
2022-05-12 22:14 ` Michael Walle
2022-05-13 1:26 ` Takahiro Kuwano
2022-05-13 9:40 ` Michael Walle
2022-05-14 3:51 ` Takahiro Kuwano
2022-05-18 6:04 ` Takahiro Kuwano
2022-05-18 8:35 ` Michael Walle
2022-05-18 9:12 ` Takahiro Kuwano
2022-05-23 7:49 ` Michael Walle
2022-05-23 9:56 ` Takahiro Kuwano
2022-06-03 9:33 ` Takahiro Kuwano
2022-07-21 16:06 ` Tudor.Ambarus
2022-07-22 4:00 ` Takahiro Kuwano [this message]
2022-07-22 4:20 ` Tudor.Ambarus
2022-07-22 4:31 ` Vanessa Page
2022-07-22 4:46 ` Takahiro Kuwano
2022-07-22 5:06 ` Tudor.Ambarus
2022-07-22 5:11 ` Takahiro Kuwano
2022-07-22 6:08 ` Tudor.Ambarus
2022-07-22 7:38 ` Tudor.Ambarus
2022-07-22 7:45 ` Tudor.Ambarus
2022-06-08 11:39 ` Tudor.Ambarus
2022-05-09 22:10 ` [PATCH v15 7/8] mtd: spi-nor: spansion: Add local function to discover page size tkuw584924
2022-05-09 22:10 ` [PATCH v15 8/8] mtd: spi-nor: spansion: Add s25hl-t/s25hs-t IDs and fixups tkuw584924
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