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Subject: Re: [RFC PATCH 0/5] RFC for Zynq QSPI
To: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>,
 cyrille.pitchen@wedev4u.fr, dwmw2@infradead.org,
 computersforpeace@gmail.com, boris.brezillon@free-electrons.com
Cc: linux-mtd@lists.infradead.org, Naga Sureshkumar Relli <nagasure@xilinx.com>
References: <1521807722-21626-1-git-send-email-nagasure@xilinx.com>
From: Marek Vasut <marek.vasut@gmail.com>
Message-ID: <c06c5256-119d-ef90-0bf8-cdbc1720a7b9@gmail.com>
Date: Fri, 23 Mar 2018 13:52:18 +0100
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On 03/23/2018 01:21 PM, Naga Sureshkumar Relli wrote:
> Xilinx Zynq uses a QSPI controller that is based on the Cadence SPI IP.

Don't we have a CQSPI driver already ? Why is this adding a new one ?

-- 
Best regards,
Marek Vasut