Linux-mtd Archive on lore.kernel.org
 help / color / Atom feed
* [RFC PATCH 0/3] Fix proposal for the Micron shallow erase issue
@ 2019-12-31 19:26 Miquel Raynal
  2019-12-31 19:26 ` [RFC PATCH 1/3] mtd: rawnand: Add the nand_chip->erase hook Miquel Raynal
                   ` (3 more replies)
  0 siblings, 4 replies; 10+ messages in thread
From: Miquel Raynal @ 2019-12-31 19:26 UTC (permalink / raw)
  To: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus, linux-mtd
  Cc: Miquel Raynal, Zoltan Szubbocsev, Thomas Petazzoni,
	Boris Brezillon, tglx, Piotr Wojtaszczyk, Bean Huo

Hello,

After a first proposal by Thomas Gleixner and then another proposal by
Bean Huo (Micron), this is an attempt to mainline the fix for Micron's
"shallow erase" issue. IMHO this is a "pretty way", not so invasive,
with a limited performance penalty.

It has only be *compile-tested* and this is just to know if the
approach is fine or not, then I will optimize, maybe rewrite a bit and
forcibly (ask to) test it.

Happy new year!
Miquèl


Miquel Raynal (3):
  mtd: rawnand: Add the nand_chip->erase hook
  mtd: rawnand: Add the nand_chip->write_oob hook
  mtd: rawnand: micron: Address the shallow erase issue

 data_buf                           | 29099 +++++++++++++++++++++++++++
 databuf                            | 29099 +++++++++++++++++++++++++++
 drivers/mtd/nand/raw/internals.h   |     2 +
 drivers/mtd/nand/raw/nand_base.c   |    14 +-
 drivers/mtd/nand/raw/nand_micron.c |   121 +
 include/linux/mtd/rawnand.h        |     6 +
 6 files changed, 58340 insertions(+), 1 deletion(-)
 create mode 100644 data_buf
 create mode 100644 databuf

-- 
2.20.1


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

^ permalink raw reply	[flat|nested] 10+ messages in thread

* [RFC PATCH 1/3] mtd: rawnand: Add the nand_chip->erase hook
  2019-12-31 19:26 [RFC PATCH 0/3] Fix proposal for the Micron shallow erase issue Miquel Raynal
@ 2019-12-31 19:26 ` Miquel Raynal
  2019-12-31 19:26 ` [RFC PATCH 2/3] mtd: rawnand: Add the nand_chip->write_oob hook Miquel Raynal
                   ` (2 subsequent siblings)
  3 siblings, 0 replies; 10+ messages in thread
From: Miquel Raynal @ 2019-12-31 19:26 UTC (permalink / raw)
  To: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus, linux-mtd
  Cc: Miquel Raynal, Zoltan Szubbocsev, Thomas Petazzoni,
	Boris Brezillon, tglx, Piotr Wojtaszczyk, Bean Huo

In order to solve an issue with Micron NANDs, we must be able to
overload the erase operation. With this in mind, we create a ->erase
hook in the nand_chip structure which points by default to the
currently in use nand_erase_nand() helper.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
 drivers/mtd/nand/raw/nand_base.c | 6 +++++-
 include/linux/mtd/rawnand.h      | 3 +++
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index f64e3b6605c6..1b1d86391e9d 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -4153,7 +4153,9 @@ static int nand_write_oob(struct mtd_info *mtd, loff_t to,
  */
 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
 {
-	return nand_erase_nand(mtd_to_nand(mtd), instr, 0);
+	struct nand_chip *chip = mtd_to_nand(mtd);
+
+	return chip->erase(chip, instr, 0);
 }
 
 /**
@@ -4373,6 +4375,8 @@ static void nand_set_defaults(struct nand_chip *chip)
 
 	if (!chip->buf_align)
 		chip->buf_align = 1;
+
+	chip->erase = nand_erase_nand;
 }
 
 /* Sanitize ONFI strings so we can safely print them */
diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
index 4ab9bccfcde0..aa956949b226 100644
--- a/include/linux/mtd/rawnand.h
+++ b/include/linux/mtd/rawnand.h
@@ -1020,6 +1020,7 @@ struct nand_legacy {
  *			avoid using them.
  * @setup_read_retry:	[FLASHSPECIFIC] flash (vendor) specific function for
  *			setting the read-retry mode. Mostly needed for MLC NAND.
+ * @erase:		Raw NAND erase operation.
  * @ecc:		[BOARDSPECIFIC] ECC control structure
  * @buf_align:		minimum buffer alignment required by a platform
  * @oob_poi:		"poison value buffer," used for laying out OOB data
@@ -1085,6 +1086,8 @@ struct nand_chip {
 	struct nand_legacy legacy;
 
 	int (*setup_read_retry)(struct nand_chip *chip, int retry_mode);
+	int (*erase)(struct nand_chip *chip, struct erase_info *instr,
+		     int allowbbt);
 
 	unsigned int options;
 	unsigned int bbt_options;
-- 
2.20.1


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

^ permalink raw reply	[flat|nested] 10+ messages in thread

* [RFC PATCH 2/3] mtd: rawnand: Add the nand_chip->write_oob hook
  2019-12-31 19:26 [RFC PATCH 0/3] Fix proposal for the Micron shallow erase issue Miquel Raynal
  2019-12-31 19:26 ` [RFC PATCH 1/3] mtd: rawnand: Add the nand_chip->erase hook Miquel Raynal
@ 2019-12-31 19:26 ` Miquel Raynal
  2019-12-31 19:26 ` [RFC PATCH 3/3] mtd: rawnand: micron: Address the shallow erase issue Miquel Raynal
  2020-01-02 18:41 ` [RFC PATCH 0/3] Fix proposal for the Micron " Florian Fainelli
  3 siblings, 0 replies; 10+ messages in thread
From: Miquel Raynal @ 2019-12-31 19:26 UTC (permalink / raw)
  To: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus, linux-mtd
  Cc: Miquel Raynal, Zoltan Szubbocsev, Thomas Petazzoni,
	Boris Brezillon, tglx, Piotr Wojtaszczyk, Bean Huo

With the same approach as for the ->erase hook, in order to solve an
issue with Micron NANDs, we must be able to overload the write
operation. With this in mind, we create a ->write_oob hook in the
nand_chip structure which points by default to the
currently in use nand_write_oob() helper, renamed
nand_write_oob_nand() for the parallel with the nand_erase_nand()
one.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
 drivers/mtd/nand/raw/internals.h | 2 ++
 drivers/mtd/nand/raw/nand_base.c | 8 ++++++++
 include/linux/mtd/rawnand.h      | 3 +++
 3 files changed, 13 insertions(+)

diff --git a/drivers/mtd/nand/raw/internals.h b/drivers/mtd/nand/raw/internals.h
index cba6fe7dd8c4..55cf26e691ee 100644
--- a/drivers/mtd/nand/raw/internals.h
+++ b/drivers/mtd/nand/raw/internals.h
@@ -80,6 +80,8 @@ int nand_bbm_get_next_page(struct nand_chip *chip, int page);
 int nand_markbad_bbm(struct nand_chip *chip, loff_t ofs);
 int nand_erase_nand(struct nand_chip *chip, struct erase_info *instr,
 		    int allowbbt);
+int nand_write_oob_nand(struct nand_chip *chip, loff_t to,
+			struct mtd_oob_ops *ops);
 int onfi_fill_data_interface(struct nand_chip *chip,
 			     enum nand_data_interface_type type,
 			     int timing_mode);
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index 1b1d86391e9d..b0ed556d4d12 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -4116,6 +4116,13 @@ static int nand_write_oob(struct mtd_info *mtd, loff_t to,
 			  struct mtd_oob_ops *ops)
 {
 	struct nand_chip *chip = mtd_to_nand(mtd);
+
+	return chip->write_oob(chip, to, ops);
+}
+
+int nand_write_oob_nand(struct nand_chip *chip, loff_t to,
+			struct mtd_oob_ops *ops)
+{
 	int ret;
 
 	ops->retlen = 0;
@@ -4377,6 +4384,7 @@ static void nand_set_defaults(struct nand_chip *chip)
 		chip->buf_align = 1;
 
 	chip->erase = nand_erase_nand;
+	chip->write_oob = nand_write_oob_nand;
 }
 
 /* Sanitize ONFI strings so we can safely print them */
diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
index aa956949b226..c6ca1e71341d 100644
--- a/include/linux/mtd/rawnand.h
+++ b/include/linux/mtd/rawnand.h
@@ -1021,6 +1021,7 @@ struct nand_legacy {
  * @setup_read_retry:	[FLASHSPECIFIC] flash (vendor) specific function for
  *			setting the read-retry mode. Mostly needed for MLC NAND.
  * @erase:		Raw NAND erase operation.
+ * @write_oob:		Raw NAND write operation.
  * @ecc:		[BOARDSPECIFIC] ECC control structure
  * @buf_align:		minimum buffer alignment required by a platform
  * @oob_poi:		"poison value buffer," used for laying out OOB data
@@ -1088,6 +1089,8 @@ struct nand_chip {
 	int (*setup_read_retry)(struct nand_chip *chip, int retry_mode);
 	int (*erase)(struct nand_chip *chip, struct erase_info *instr,
 		     int allowbbt);
+	int (*write_oob)(struct nand_chip *chip, loff_t to,
+			 struct mtd_oob_ops *ops);
 
 	unsigned int options;
 	unsigned int bbt_options;
-- 
2.20.1


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

^ permalink raw reply	[flat|nested] 10+ messages in thread

* [RFC PATCH 3/3] mtd: rawnand: micron: Address the shallow erase issue
  2019-12-31 19:26 [RFC PATCH 0/3] Fix proposal for the Micron shallow erase issue Miquel Raynal
  2019-12-31 19:26 ` [RFC PATCH 1/3] mtd: rawnand: Add the nand_chip->erase hook Miquel Raynal
  2019-12-31 19:26 ` [RFC PATCH 2/3] mtd: rawnand: Add the nand_chip->write_oob hook Miquel Raynal
@ 2019-12-31 19:26 ` Miquel Raynal
  2020-01-02 18:41 ` [RFC PATCH 0/3] Fix proposal for the Micron " Florian Fainelli
  3 siblings, 0 replies; 10+ messages in thread
From: Miquel Raynal @ 2019-12-31 19:26 UTC (permalink / raw)
  To: Richard Weinberger, Vignesh Raghavendra, Tudor Ambarus, linux-mtd
  Cc: Miquel Raynal, Zoltan Szubbocsev, Thomas Petazzoni,
	Boris Brezillon, tglx, Piotr Wojtaszczyk, Bean Huo

With recent SLC NANDs, Micron admits that a "shallow erase" issue may
be observable. It is actually the chip itself not doing a correct
erase operation because of its internal machinery stating that the
pages have not been programmed. Micron told us that there is a way to
workaround this issue: ensure that all the odd pages in the 16 first
ones of each block to erase have been fully written.

To avoid a very big performance drawback by re-writting all the pages
for each erase operation, the fix proposed here overloads the ->erase
and ->write_oob hooks to count the pages actually written at runtime
and avoid re-writting them if not needed.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
 data_buf                           | 29099 +++++++++++++++++++++++++++
 databuf                            | 29099 +++++++++++++++++++++++++++
 drivers/mtd/nand/raw/nand_micron.c |   121 +
 3 files changed, 58319 insertions(+)
 create mode 100644 data_buf
 create mode 100644 databuf

diff --git a/data_buf b/data_buf
new file mode 100644
index 000000000000..778fac847dd4
--- /dev/null
+++ b/data_buf
@@ -0,0 +1,29099 @@
+Documentation/ABI/testing/sysfs-firmware-opal-psr:		with chip-id X. This file gives the ratio (0-100)
+Documentation/PCI/pci.rst:Since each CPU architecture implements different chip-sets and PCI devices
+Documentation/PCI/pci.rst:or chip-sets may support Memory-Write-Invalidate.  Alternatively,
+Documentation/PCI/pci.rst:address by the arch/chip-set specific kernel support.
+Documentation/PCI/pci.rst:capability registers. Many architectures, chip-sets, or BIOSes do NOT
+Documentation/PCI/pci.rst:corruption, hangs, and on some chip-sets a hard crash.
+Documentation/core-api/genericirq.rst:and only need to add the chip-level specific code. The separation is
+Documentation/core-api/genericirq.rst:        desc->irq_data.chip->irq_unmask(data);
+Documentation/core-api/genericirq.rst:            desc->irq_data.chip->irq_mask(data);
+Documentation/core-api/genericirq.rst:        chip->irq_ack(data);
+Documentation/core-api/genericirq.rst:        if (chip->irq_mask_ack) {
+Documentation/core-api/genericirq.rst:            chip->irq_mask_ack(data);
+Documentation/core-api/genericirq.rst:            chip->irq_mask(data);
+Documentation/core-api/genericirq.rst:            chip->irq_ack(data);
+Documentation/core-api/genericirq.rst:    desc->irq_data.chip->irq_mask_ack();
+Documentation/core-api/genericirq.rst:    desc->irq_data.chip->irq_unmask();
+Documentation/core-api/genericirq.rst:    desc->irq_data.chip->irq_eoi();
+Documentation/core-api/genericirq.rst:        desc->irq_data.chip->irq_mask_ack();
+Documentation/core-api/genericirq.rst:    desc->irq_data.chip->irq_ack();
+Documentation/core-api/genericirq.rst:            desc->irq_data.chip->irq_unmask();
+Documentation/core-api/genericirq.rst:    if (desc->irq_data.chip->irq_ack)
+Documentation/core-api/genericirq.rst:        desc->irq_data.chip->irq_ack();
+Documentation/core-api/genericirq.rst:    if (desc->irq_data.chip->irq_eoi)
+Documentation/core-api/genericirq.rst:        desc->irq_data.chip->irq_eoi();
+Documentation/core-api/genericirq.rst:The chip-level hardware descriptor structure :c:type:`irq_chip` contains all
+Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml:  amlogic,has-chip-id:
+Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml:          amlogic,has-chip-id;
+Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt:  - compatible: Should contain a chip-specific compatible string,
+Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-scfg.txt:  - compatible: Should contain a chip-specific compatible string,
+Documentation/devicetree/bindings/arm/sunxi.yaml:          - const: nextthing,chip-pro
+Documentation/devicetree/bindings/arm/syna.txt:chip: chip-control@ea0000 {
+Documentation/devicetree/bindings/bus/imx-weim.txt:			integer values for each chip-select line in use:
+Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt:   for each chip-select line in use (only one entry is supported, see below
+Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt:Note that the GMI controller does not have any internal chip-select address
+Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt:decoding, because of that chip-selects either need to be managed via software
+Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt:or by employing external chip-select decoding logic.
+Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt:If external chip-select logic is used to support multiple devices it is assumed
+Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt:child device is supported which represents the active chip-select line, see
+Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt:The chip-select number is decoded from the child nodes second address cell of
+Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt:'ranges' property, if 'ranges' property is not present or empty chip-select will
+Documentation/devicetree/bindings/bus/nvidia,tegra20-gmi.txt:chip-select (CS4), in this example external address decoding is provided:
+Documentation/devicetree/bindings/c6x/emifa.txt:- #address-cells: must be 2 (chip-select + offset)
+Documentation/devicetree/bindings/clock/qoriq-clock.txt:- compatible: Should contain a chip-specific clock block compatible
+Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt:			 rockchip-dfi.txt
+Documentation/devicetree/bindings/display/msm/gpu.txt:  with the chip-id.
+Documentation/devicetree/bindings/display/rockchip/rockchip-drm.txt:  Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt
+Documentation/devicetree/bindings/fpga/fpga-region.txt:			onchip-memory {
+Documentation/devicetree/bindings/fsi/fsi.txt:    chip-id = <0>;
+Documentation/devicetree/bindings/fsi/fsi.txt:	    chip-id = <0>;
+Documentation/devicetree/bindings/iio/potentiometer/max5481.txt:	reg = <0>; /* chip-select */
+Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml:          - const: arm,arm1176jzf-devchip-gic
+Documentation/devicetree/bindings/media/i2c/tda1997x.txt:pairs which map a chip-specific VP output register to a 4-bit pin group. If
+Documentation/devicetree/bindings/memory-controllers/arm,pl172.txt:Child chip-select (cs) nodes contain the memory devices nodes connected to
+Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt:- reg:			Contains the chip-select id, the offset and the length
+Documentation/devicetree/bindings/memory-controllers/fsl/ddr.txt:- compatible	: Should include "fsl,chip-memory-controller" where
+Documentation/devicetree/bindings/memory-controllers/mvebu-devbus.txt:                        integer values for each chip-select line in use:
+Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt: - gpmc,num-cs:		The maximum number of chip-select lines that controller
+Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt:			integer values for each chip-select line in use:
+Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt: - gpmc,cycle2cycle-delay-ns:	Delay between chip-select pulses
+Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt:GPMC chip-select settings properties for child nodes. All are optional.
+Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt:			chip-select in bytes. The GPMC supports 8-bit
+Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt:Child chip-select (cs) nodes contain the memory devices nodes connected to
+Documentation/devicetree/bindings/memory-controllers/ti/emif.txt:  calibration resistor per chip-select.
+Documentation/devicetree/bindings/mfd/arizona.txt:  - compatible : One of the following chip-specific strings:
+Documentation/devicetree/bindings/mfd/hi6421.txt:- compatible    : One of the following chip-specific strings:
+Documentation/devicetree/bindings/mfd/madera.txt:  - compatible : One of the following chip-specific strings:
+Documentation/devicetree/bindings/mfd/wm831x.txt:  - compatible : One of the following chip-specific strings:
+Documentation/devicetree/bindings/mips/mscc.txt:- compatible: Should be "mscc,ocelot-chip-regs", "simple-mfd", "syscon"
+Documentation/devicetree/bindings/mips/mscc.txt:		compatible = "mscc,ocelot-chip-regs", "simple-mfd", "syscon";
+Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt:- #address-cells   : <1> - subnodes give the chip-select number
+Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt:* NAND chip-select
+Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt:to represent enabled chip-selects which (may) contain NAND flash chips. Their
+Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt:- reg                       : a single integer representing the chip-select
+Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt:                              chip-select. See nand-controller.yaml
+Documentation/devicetree/bindings/mtd/diskonchip.txt: - compatible: should be "m-systems,diskonchip-g3"
+Documentation/devicetree/bindings/mtd/diskonchip.txt:		compatible = "m-systems,diskonchip-g3";
+Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt:- fsl,upm-wait-flags : add chip-dependent short delays after running the
+Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt:- chip-delay : chip dependent delay for transferring data from array to
+Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt:	chip-delay = <25>; // in micro-seconds
+Documentation/devicetree/bindings/mtd/gpio-control-nand.txt:- chip-delay : chip dependent delay for transferring data from array to
+Documentation/devicetree/bindings/mtd/gpmc-nor.txt:- reg:			Chip-select, base address (relative to chip-select)
+Documentation/devicetree/bindings/mtd/gpmc-nor.txt:			typically 0 as this is the start of the chip-select.
+Documentation/devicetree/bindings/mtd/marvell-nand.txt:- num-cs: Number of chip-select lines to use, all boards blindly set 1
+Documentation/devicetree/bindings/mtd/orion-nand.txt:- chip-delay : Chip dependent delay for transferring data from array to read
+Documentation/devicetree/bindings/mtd/orion-nand.txt:	chip-delay = <25>;
+Documentation/devicetree/bindings/mtd/qcom_nandc.txt:- #address-cells:	<1> - subnodes give the chip-select number
+Documentation/devicetree/bindings/mtd/qcom_nandc.txt:* NAND chip-select
+Documentation/devicetree/bindings/mtd/qcom_nandc.txt:chip-selects which (may) contain NAND flash chips. Their properties are as
+Documentation/devicetree/bindings/mtd/qcom_nandc.txt:- reg:			a single integer representing the chip-select
+Documentation/devicetree/bindings/mtd/spi-nand.txt:- reg: should encode the chip-select line used to access the NAND chip
+Documentation/devicetree/bindings/mux/mux-controller.txt:mux-ctrl-specifier typically encodes the chip-relative mux controller number.
+Documentation/devicetree/bindings/net/gpmc-eth.txt:- reg:			Chip-select, base address (relative to chip-select)
+Documentation/devicetree/bindings/net/gpmc-eth.txt:			is the start of the chip-select.
+Documentation/devicetree/bindings/net/microchip,lan78xx.txt:  are defined in "include/dt-bindings/net/microchip-lan78xx.h".
+Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt:- compatible: "rockchip,rockchip-efuse"
+Documentation/devicetree/bindings/pci/layerscape-pci.txt:which is used to describe the PLL settings at the time of chip-reset.
+Documentation/devicetree/bindings/pci/rockchip-pcie-ep.txt:  (see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt
+Documentation/devicetree/bindings/pci/rockchip-pcie-host.txt:  (see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt
+Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt:   - utmi-pads: The reset of the PHY containing the chip-wide UTMI pad control
+Documentation/devicetree/bindings/power/reset/ocelot-reset.txt: - compatible: "mscc,ocelot-chip-reset"
+Documentation/devicetree/bindings/power/reset/ocelot-reset.txt:		compatible = "mscc,ocelot-chip-reset";
+Documentation/devicetree/bindings/powerpc/4xx/reboot.txt:			reset-type = <2>;	/* Use chip-reset */
+Documentation/devicetree/bindings/powerpc/fsl/interlaken-lac.txt:The Interlaken is a narrow, high speed channelized chip-to-chip interface. To
+Documentation/devicetree/bindings/powerpc/opal/sensor-groups.txt:- ibm,chip-id : Chip ID
+Documentation/devicetree/bindings/pwm/pwm.txt:pwm-specifier typically encodes the chip-relative PWM number and the PWM
+Documentation/devicetree/bindings/soc/fsl/rcpm.txt:  - compatible : Must contain a chip-specific RCPM block compatible string
+Documentation/devicetree/bindings/sound/rockchip-max98090.txt:- compatible: "rockchip,rockchip-audio-max98090"
+Documentation/devicetree/bindings/sound/rockchip-max98090.txt:	compatible = "rockchip,rockchip-audio-max98090";
+Documentation/devicetree/bindings/sound/rockchip-max98090.txt:	compatible = "rockchip,rockchip-audio-max98090";
+Documentation/devicetree/bindings/sound/rockchip-max98090.txt:	compatible = "rockchip,rockchip-audio-max98090";
+Documentation/devicetree/bindings/sound/rockchip-rt5645.txt:- compatible: "rockchip,rockchip-audio-rt5645"
+Documentation/devicetree/bindings/sound/rockchip-rt5645.txt:	compatible = "rockchip,rockchip-audio-rt5645";
+Documentation/devicetree/bindings/spi/spi-orion.txt:	chip-select lines 0 through 7 respectively.
+Documentation/devicetree/bindings/spi/spi-orion.txt:and its chip-selects that are used in the direct mode instead of PIO
+Documentation/devicetree/bindings/usb/cdns-usb3.txt: - cdns,on-chip-buff-size : size of memory intended as internal memory for endpoints
+Documentation/devicetree/bindings/usb/rockchip,dwc3.txt:Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt - USB2.0 PHY
+Documentation/devicetree/bindings/usb/rockchip,dwc3.txt:Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt     - Type-C PHY
+Documentation/driver-api/edac.rst:*sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
+Documentation/driver-api/edac.rst:accessed. Common chip-select rows for single channel are 64 bits, for
+Documentation/driver-api/edac.rst:A Single-ranked stick has 1 chip-select row of memory. Motherboards
+Documentation/driver-api/edac.rst:commonly drive two chip-select pins to a memory stick. A single-ranked
+Documentation/driver-api/edac.rst:A double-ranked stick has two chip-select rows which access different
+Documentation/driver-api/edac.rst:A double-sided stick has two chip-select rows which access different sets
+Documentation/driver-api/edac.rst:all of the memory sticks spanned by a chip-select row.  A single socket
+Documentation/driver-api/edac.rst:set has two chip-select rows and if double-sided sticks are used these
+Documentation/driver-api/edac.rst:will occupy those chip-select rows.
+Documentation/driver-api/edac.rst:between chip-select rows and socket sets.
+Documentation/driver-api/gpio/legacy.rst:this is highly chip-specific and nonportable.  One platform might not need
+Documentation/driver-api/pwm.rst:number of PWM devices provided by the chip and the chip-specific
+Documentation/hwmon/sysfs-interface.rst:completely chip-independent. It assumes that all the kernel drivers
+Documentation/hwmon/sysfs-interface.rst:For this reason, even if we aim at a chip-independent libsensors, it will
+Documentation/hwmon/sysfs-interface.rst:to cause an alarm) is chip-dependent.
+Documentation/hwmon/sysfs-interface.rst:		Number of trip points is chip-dependent. Use this for chips
+Documentation/hwmon/sysfs-interface.rst:		Number of trip points is chip-dependent. Use this for chips
+Documentation/hwmon/tmp103.rst:wafer chip-scale package (WCSP). The TMP103 is capable of reading
+Documentation/hwmon/tmp401.rst:* Minimum and Maximum temperature measured since power-on, chip-reset
+Documentation/hwmon/w83791d.rst:chip-specific options are documented here.
+Documentation/i2c/fault-codes.rst:	or SMBus (or chip-specific) protocol specifications.  One
+Documentation/media/uapi/v4l/user-func.rst:    vidioc-dbg-g-chip-info
+Documentation/media/uapi/v4l/vidioc-dbg-g-chip-info.rst:      - See :ref:`name-chip-match-types` for a list of possible types.
+Documentation/media/uapi/v4l/vidioc-dbg-g-chip-info.rst:.. _name-chip-match-types:
+Documentation/media/uapi/v4l/vidioc-dbg-g-register.rst:      - See :ref:`chip-match-types` for a list of possible types.
+Documentation/media/uapi/v4l/vidioc-dbg-g-register.rst:.. _chip-match-types:
+Documentation/networking/z8530drv.txt:	  specified within one chip-definition only.
+Documentation/sh/new-machine.txt:                    `-- cchip-specific files
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:      /* definition of the chip-specific record */
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:      /* chip-specific destructor
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:      /* chip-specific constructor
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:              /* allocate a chip-specific data with zero filled */
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:              chip->card = card;
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:                      card->shortname, chip->port, chip->irq);
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:          card->shortname, chip->port, chip->irq);
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:card->private_data for the chip-specific data. Note that these data are
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:example will show an implementation of chip-specific data.
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:pointer, or the irq number, is stored in the chip-specific record.
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:  chip->card = card;
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:In this section, we'll complete the chip-specific constructor,
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:              if (chip->irq >= 0)
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:                      free_irq(chip->irq, chip);
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:              pci_release_regions(chip->pci);
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:              pci_disable_device(chip->pci);
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:      /* chip-specific constructor */
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:              chip->card = card;
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:              chip->pci = pci;
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:              chip->irq = -1;
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:              chip->port = pci_resource_start(pci, 0);
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:              chip->irq = pci->irq;
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:              card->sync_irq = chip->irq;
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:  chip->port = pci_resource_start(pci, 0);
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:The returned value, ``chip->res_port``, is allocated via
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:  chip->irq = pci->irq;
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:``chip->irq`` should be defined only when :c:func:`request_irq()`
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:passed to the interrupt handler. Usually, the chip-specific record is
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:          card->irq = chip->irq;
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:  if (chip->irq >= 0)
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:          free_irq(chip->irq, chip);
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:``chip->irq`` with a negative value (e.g. -1), so that you can check
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:  pci_release_regions(chip->pci);
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:chip->res_port, the release procedure looks like:
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:  release_and_free_resource(chip->res_port);
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:And finally, release the chip-specific record.
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:When the chip-data is assigned to the card using
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:  chip->iobase_phys = pci_resource_start(pci, 0);
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:  chip->iobase_virt = ioremap_nocache(chip->iobase_phys,
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:          if (chip->iobase_virt)
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:                  iounmap(chip->iobase_virt);
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:          pci_release_regions(chip->pci);
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:  chip->iobase_virt = pci_iomap(pci, 0, 0);
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:                                   chip->buffer_size,
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:                                   chip->period_size);
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:              err = snd_pcm_new(chip->card, "My Chip", 0, 1, 1, &pcm);
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:              chip->pcm = pcm;
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:                                             &chip->pci->dev,
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:          err = snd_pcm_new(chip->card, "My Chip", 0, 1, 1, &pcm);
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:          chip->pcm = pcm;
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:                                 &chip->pci->dev,
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:              kfree(chip->my_private_pcm_data);
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:              chip->my_private_pcm_data = kmalloc(...);
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:          if (chip->model == VERY_OLD_ONE)
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:              spin_lock(&chip->lock);
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:                      spin_unlock(&chip->lock);
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:                      snd_pcm_period_elapsed(chip->substream);
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:                      spin_lock(&chip->lock);
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:              spin_unlock(&chip->lock);
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:              spin_lock(&chip->lock);
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:                      if (last_ptr < chip->last_ptr)
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:                                       - chip->last_ptr;
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:                              size = last_ptr - chip->last_ptr;
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:                      chip->last_ptr = last_ptr;
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:                      chip->size += size;
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:                      if (chip->size >= runtime->period_size) {
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:                              chip->size %= runtime->period_size;
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:                              spin_unlock(&chip->lock);
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:                              spin_lock(&chip->lock);
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:              spin_unlock(&chip->lock);
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:              if (chip->current_value !=
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:              err = snd_ac97_bus(chip->card, 0, &ops, NULL, &bus);
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:              return snd_ac97_mixer(bus, &ac97, &chip->ac97);
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:  snd_ac97_mixer(bus, &ac97, &chip->ac97);
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:where chip->ac97 is a pointer to a newly created ``ac97_t``
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:  err = snd_rawmidi_new(chip->card, "MyMIDI", 0, outs, ins, &rmidi);
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:          snd_iprintf(buffer, "Port = %ld\n", chip->port);
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:          snd_ac97_suspend(chip->ac97);
+Documentation/sound/kernel-api/writing-an-alsa-driver.rst:          snd_ac97_resume(chip->ac97);
+Documentation/spi/spi-summary.rst:is wired, plus chip-specific constraints like an important delay that's
+MAINTAINERS:F:	include/linux/platform_data/microchip-ksz.h
+MAINTAINERS:F:	Documentation/devicetree/bindings/pci/rockchip-pcie*
+MAINTAINERS:F:	Documentation/devicetree/bindings/media/rockchip-rga.txt
+MAINTAINERS:F:	Documentation/devicetree/bindings/media/rockchip-vpu.txt
+MAINTAINERS:F:	include/dt-bindings/net/microchip-lan78xx.h
+arch/alpha/kernel/core_polaris.c: * POLARIS chip-specific code
+arch/alpha/kernel/core_titan.c:	port = &pachip->g_port;
+arch/alpha/kernel/core_titan.c:		port = &pachip->a_port;
+arch/alpha/kernel/core_titan.c:	titan_pchip1_present = TITAN_cchip->csc.csr & 1L<<14;
+arch/alpha/kernel/core_titan.c:	printk("%s: CSR_CSC 0x%lx\n", __func__, TITAN_cchip->csc.csr);
+arch/alpha/kernel/core_titan.c:	printk("%s: CSR_MTR 0x%lx\n", __func__, TITAN_cchip->mtr.csr);
+arch/alpha/kernel/core_titan.c:	printk("%s: CSR_MISC 0x%lx\n", __func__, TITAN_cchip->misc.csr);
+arch/alpha/kernel/core_titan.c:	printk("%s: CSR_DIM0 0x%lx\n", __func__, TITAN_cchip->dim0.csr);
+arch/alpha/kernel/core_titan.c:	printk("%s: CSR_DIM1 0x%lx\n", __func__, TITAN_cchip->dim1.csr);
+arch/alpha/kernel/core_titan.c:	printk("%s: CSR_DIR0 0x%lx\n", __func__, TITAN_cchip->dir0.csr);
+arch/alpha/kernel/core_titan.c:	printk("%s: CSR_DIR1 0x%lx\n", __func__, TITAN_cchip->dir1.csr);
+arch/alpha/kernel/core_titan.c:	printk("%s: CSR_DRIR 0x%lx\n", __func__, TITAN_cchip->drir.csr);
+arch/alpha/kernel/core_titan.c:	printk("%s: CSR_DSC 0x%lx\n", __func__, TITAN_dchip->dsc.csr);
+arch/alpha/kernel/core_titan.c:	printk("%s: CSR_STR 0x%lx\n", __func__, TITAN_dchip->str.csr);
+arch/alpha/kernel/core_titan.c:	printk("%s: CSR_DREV 0x%lx\n", __func__, TITAN_dchip->drev.csr);
+arch/alpha/kernel/core_tsunami.c:	csr = &pchip->tlbia.csr;
+arch/alpha/kernel/core_tsunami.c:		csr = &pchip->tlbiv.csr;
+arch/alpha/kernel/core_tsunami.c:	TSUNAMI_cchip->misc.csr |= (1L << 28); /* clear NXM... */
+arch/alpha/kernel/core_tsunami.c:	if (TSUNAMI_cchip->misc.csr & (1L << 28)) {
+arch/alpha/kernel/core_tsunami.c:		int source = (TSUNAMI_cchip->misc.csr >> 29) & 7;
+arch/alpha/kernel/core_tsunami.c:		TSUNAMI_cchip->misc.csr |= (1L << 28); /* ...and unlock NXS. */
+arch/alpha/kernel/core_tsunami.c:	if (tsunami_probe_read(&pchip->pctl.csr) == 0)
+arch/alpha/kernel/core_tsunami.c:	saved_config[index].wsba[0] = pchip->wsba[0].csr;
+arch/alpha/kernel/core_tsunami.c:	saved_config[index].wsm[0] = pchip->wsm[0].csr;
+arch/alpha/kernel/core_tsunami.c:	saved_config[index].tba[0] = pchip->tba[0].csr;
+arch/alpha/kernel/core_tsunami.c:	saved_config[index].wsba[1] = pchip->wsba[1].csr;
+arch/alpha/kernel/core_tsunami.c:	saved_config[index].wsm[1] = pchip->wsm[1].csr;
+arch/alpha/kernel/core_tsunami.c:	saved_config[index].tba[1] = pchip->tba[1].csr;
+arch/alpha/kernel/core_tsunami.c:	saved_config[index].wsba[2] = pchip->wsba[2].csr;
+arch/alpha/kernel/core_tsunami.c:	saved_config[index].wsm[2] = pchip->wsm[2].csr;
+arch/alpha/kernel/core_tsunami.c:	saved_config[index].tba[2] = pchip->tba[2].csr;
+arch/alpha/kernel/core_tsunami.c:	saved_config[index].wsba[3] = pchip->wsba[3].csr;
+arch/alpha/kernel/core_tsunami.c:	saved_config[index].wsm[3] = pchip->wsm[3].csr;
+arch/alpha/kernel/core_tsunami.c:	saved_config[index].tba[3] = pchip->tba[3].csr;
+arch/alpha/kernel/core_tsunami.c:	pchip->wsba[0].csr = hose->sg_isa->dma_base | 3;
+arch/alpha/kernel/core_tsunami.c:	pchip->wsm[0].csr  = (hose->sg_isa->size - 1) & 0xfff00000;
+arch/alpha/kernel/core_tsunami.c:	pchip->tba[0].csr  = virt_to_phys(hose->sg_isa->ptes);
+arch/alpha/kernel/core_tsunami.c:	pchip->wsba[1].csr = hose->sg_pci->dma_base | 3;
+arch/alpha/kernel/core_tsunami.c:	pchip->wsm[1].csr  = (hose->sg_pci->size - 1) & 0xfff00000;
+arch/alpha/kernel/core_tsunami.c:	pchip->tba[1].csr  = virt_to_phys(hose->sg_pci->ptes);
+arch/alpha/kernel/core_tsunami.c:	pchip->wsba[2].csr = 0x80000000 | 1;
+arch/alpha/kernel/core_tsunami.c:	pchip->wsm[2].csr  = (0x80000000 - 1) & 0xfff00000;
+arch/alpha/kernel/core_tsunami.c:	pchip->tba[2].csr  = 0;
+arch/alpha/kernel/core_tsunami.c:	pchip->wsba[3].csr = 0;
+arch/alpha/kernel/core_tsunami.c:	pchip->pctl.csr |= pctl_m_mwin;
+arch/alpha/kernel/core_tsunami.c:	printk("%s: CSR_CSC 0x%lx\n", __func__, TSUNAMI_cchip->csc.csr);
+arch/alpha/kernel/core_tsunami.c:	printk("%s: CSR_MISC 0x%lx\n", __func__, TSUNAMI_cchip->misc.csr);
+arch/alpha/kernel/core_tsunami.c:	printk("%s: CSR_DIM0 0x%lx\n", __func__, TSUNAMI_cchip->dim0.csr);
+arch/alpha/kernel/core_tsunami.c:	printk("%s: CSR_DIM1 0x%lx\n", __func__, TSUNAMI_cchip->dim1.csr);
+arch/alpha/kernel/core_tsunami.c:	printk("%s: CSR_DIR0 0x%lx\n", __func__, TSUNAMI_cchip->dir0.csr);
+arch/alpha/kernel/core_tsunami.c:	printk("%s: CSR_DIR1 0x%lx\n", __func__, TSUNAMI_cchip->dir1.csr);
+arch/alpha/kernel/core_tsunami.c:	printk("%s: CSR_DRIR 0x%lx\n", __func__, TSUNAMI_cchip->drir.csr);
+arch/alpha/kernel/core_tsunami.c:	printk("%s: CSR_DSC 0x%lx\n", __func__, TSUNAMI_dchip->dsc.csr);
+arch/alpha/kernel/core_tsunami.c:	printk("%s: CSR_STR 0x%lx\n", __func__, TSUNAMI_dchip->str.csr);
+arch/alpha/kernel/core_tsunami.c:	printk("%s: CSR_DREV 0x%lx\n", __func__, TSUNAMI_dchip->drev.csr);
+arch/alpha/kernel/core_tsunami.c:	if (TSUNAMI_cchip->csc.csr & 1L<<14)
+arch/alpha/kernel/core_tsunami.c:	pchip->wsba[0].csr = saved_config[index].wsba[0];
+arch/alpha/kernel/core_tsunami.c:	pchip->wsm[0].csr = saved_config[index].wsm[0];
+arch/alpha/kernel/core_tsunami.c:	pchip->tba[0].csr = saved_config[index].tba[0];
+arch/alpha/kernel/core_tsunami.c:	pchip->wsba[1].csr = saved_config[index].wsba[1];
+arch/alpha/kernel/core_tsunami.c:	pchip->wsm[1].csr = saved_config[index].wsm[1];
+arch/alpha/kernel/core_tsunami.c:	pchip->tba[1].csr = saved_config[index].tba[1];
+arch/alpha/kernel/core_tsunami.c:	pchip->wsba[2].csr = saved_config[index].wsba[2];
+arch/alpha/kernel/core_tsunami.c:	pchip->wsm[2].csr = saved_config[index].wsm[2];
+arch/alpha/kernel/core_tsunami.c:	pchip->tba[2].csr = saved_config[index].tba[2];
+arch/alpha/kernel/core_tsunami.c:	pchip->wsba[3].csr = saved_config[index].wsba[3];
+arch/alpha/kernel/core_tsunami.c:	pchip->wsm[3].csr = saved_config[index].wsm[3];
+arch/alpha/kernel/core_tsunami.c:	pchip->tba[3].csr = saved_config[index].tba[3];
+arch/alpha/kernel/core_tsunami.c:	if (TSUNAMI_cchip->csc.csr & 1L<<14)
+arch/alpha/kernel/core_tsunami.c:	pchip->perror.csr;
+arch/alpha/kernel/core_tsunami.c:	pchip->perror.csr = 0x040;
+arch/alpha/kernel/core_tsunami.c:	pchip->perror.csr;
+arch/alpha/kernel/core_tsunami.c:	if (TSUNAMI_cchip->csc.csr & 1L<<14)
+arch/alpha/kernel/irq.c:	if (!chip->irq_set_affinity || irq_user_affinity[irq])
+arch/alpha/kernel/irq.c:	chip->irq_set_affinity(data, cpumask_of(cpu), false);
+arch/alpha/kernel/sys_dp264.c:	dim0 = &cchip->dim0.csr;
+arch/alpha/kernel/sys_dp264.c:	dim1 = &cchip->dim1.csr;
+arch/alpha/kernel/sys_dp264.c:	dim2 = &cchip->dim2.csr;
+arch/alpha/kernel/sys_dp264.c:	dim3 = &cchip->dim3.csr;
+arch/alpha/kernel/sys_dp264.c:	if (bcpu == 0) dimB = &cchip->dim0.csr;
+arch/alpha/kernel/sys_dp264.c:	else if (bcpu == 1) dimB = &cchip->dim1.csr;
+arch/alpha/kernel/sys_dp264.c:	else if (bcpu == 2) dimB = &cchip->dim2.csr;
+arch/alpha/kernel/sys_dp264.c:	else dimB = &cchip->dim3.csr;
+arch/alpha/kernel/sys_dp264.c:	pld = TSUNAMI_cchip->dir0.csr;
+arch/alpha/kernel/sys_titan.c:	dim0 = &cchip->dim0.csr;
+arch/alpha/kernel/sys_titan.c:	dim1 = &cchip->dim1.csr;
+arch/alpha/kernel/sys_titan.c:	dim2 = &cchip->dim2.csr;
+arch/alpha/kernel/sys_titan.c:	dim3 = &cchip->dim3.csr;
+arch/alpha/kernel/sys_titan.c:	dimB = &cchip->dim0.csr;
+arch/alpha/kernel/sys_titan.c:	if (bcpu == 1) dimB = &cchip->dim1.csr;
+arch/alpha/kernel/sys_titan.c:	else if (bcpu == 2) dimB = &cchip->dim2.csr;
+arch/alpha/kernel/sys_titan.c:	else if (bcpu == 3) dimB = &cchip->dim3.csr;
+arch/arm/boot/dts/Makefile:	sun5i-gr8-chip-pro.dtb \
+arch/arm/boot/dts/arm-realview-pb1176.dts:			compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic";
+arch/arm/boot/dts/arm-realview-pb1176.dts:			compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic";
+arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts:		chip-id = <0>;
+arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts:		chip-id = <0>;
+arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts:		chip-id = <1>;
+arch/arm/boot/dts/bcm283x-rpi-lan7515.dtsi:#include <dt-bindings/net/microchip-lan78xx.h>
+arch/arm/boot/dts/berlin2.dtsi:		chip: chip-control@ea0000 {
+arch/arm/boot/dts/berlin2cd.dtsi:		chip: chip-control@ea0000 {
+arch/arm/boot/dts/berlin2q.dtsi:		chip: chip-control@ea0000 {
+arch/arm/boot/dts/da850.dtsi:		cfgchip: chip-controller@1417c {
+arch/arm/boot/dts/ibm-power9-dual.dtsi:		chip-id = <0>;
+arch/arm/boot/dts/ibm-power9-dual.dtsi:		chip-id = <1>;
+arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi:/* Quad/Dual SoMs have 3 chip-select signals */
+arch/arm/boot/dts/kirkwood-db.dtsi:	chip-delay = <25>;
+arch/arm/boot/dts/kirkwood-dnskw.dtsi:	chip-delay = <35>;
+arch/arm/boot/dts/kirkwood-goflexnet.dts:	chip-delay = <40>;
+arch/arm/boot/dts/kirkwood-km_common.dtsi:	chip-delay = <25>;
+arch/arm/boot/dts/kirkwood-nas2big.dts:	chip-delay = <50>;
+arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi:	chip-delay = <35>;
+arch/arm/boot/dts/kirkwood-openblocks_a6.dts:	chip-delay = <25>;
+arch/arm/boot/dts/kirkwood-openblocks_a7.dts:	chip-delay = <25>;
+arch/arm/boot/dts/kirkwood-pogo_e02.dts:	chip-delay = <40>;
+arch/arm/boot/dts/kirkwood-pogoplug-series-4.dts:	chip-delay = <40>;
+arch/arm/boot/dts/kirkwood.dtsi:			chip-delay = <25>;
+arch/arm/boot/dts/kirkwood.dtsi:			/* set partition map and/or chip-delay in board dts */
+arch/arm/boot/dts/rk3036.dtsi:		compatible = "rockchip,rockchip-spi";
+arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi:		compatible = "rockchip,rockchip-audio-max98090";
+arch/arm/boot/dts/rk3288-veyron-mickey.dts:		compatible = "rockchip,rockchip-audio-max98090";
+arch/arm/boot/dts/sun5i-gr8-chip-pro.dts:	compatible = "nextthing,chip-pro", "nextthing,gr8";
+arch/arm/boot/dts/sun5i-gr8-chip-pro.dts:			label = "chip-pro:white:status";
+arch/arm/boot/dts/uniphier-ld4.dtsi:		/* chip-internal connection for DMD */
+arch/arm/boot/dts/uniphier-pro4.dtsi:		/* chip-internal connection for DMD */
+arch/arm/boot/dts/uniphier-pro4.dtsi:		/* chip-internal connection for HDMI */
+arch/arm/boot/dts/uniphier-pro5.dtsi:		/* chip-internal connection for DMD */
+arch/arm/boot/dts/uniphier-pro5.dtsi:		/* chip-internal connection for HDMI */
+arch/arm/boot/dts/uniphier-pxs2.dtsi:		/* chip-internal connection for DMD */
+arch/arm/boot/dts/uniphier-pxs2.dtsi:		/* chip-internal connection for STM */
+arch/arm/boot/dts/uniphier-pxs2.dtsi:		/* chip-internal connection for HDMI */
+arch/arm/boot/dts/uniphier-sld8.dtsi:		/* chip-internal connection for DMD */
+arch/arm/common/locomo.c:	desc->irq_data.chip->irq_ack(&desc->irq_data);
+arch/arm/common/locomo.c:	req = locomo_readl(lchip->base + LOCOMO_ICR) & 0x0f00;
+arch/arm/common/locomo.c:		irq = lchip->irq_base;
+arch/arm/common/locomo.c:	r = locomo_readl(lchip->base + LOCOMO_ICR);
+arch/arm/common/locomo.c:	r &= ~(0x0010 << (d->irq - lchip->irq_base));
+arch/arm/common/locomo.c:	locomo_writel(r, lchip->base + LOCOMO_ICR);
+arch/arm/common/locomo.c:	r = locomo_readl(lchip->base + LOCOMO_ICR);
+arch/arm/common/locomo.c:	r |= (0x0010 << (d->irq - lchip->irq_base));
+arch/arm/common/locomo.c:	locomo_writel(r, lchip->base + LOCOMO_ICR);
+arch/arm/common/locomo.c:	int irq = lchip->irq_base;
+arch/arm/common/locomo.c:	irq_set_irq_type(lchip->irq, IRQ_TYPE_EDGE_FALLING);
+arch/arm/common/locomo.c:	irq_set_chained_handler_and_data(lchip->irq, locomo_handler, lchip);
+arch/arm/common/locomo.c:	for ( ; irq <= lchip->irq_base + 3; irq++) {
+arch/arm/common/locomo.c:	if (lchip->dev->dma_mask) {
+arch/arm/common/locomo.c:		dev->dma_mask = *lchip->dev->dma_mask;
+arch/arm/common/locomo.c:	dev->dev.parent  = lchip->dev;
+arch/arm/common/locomo.c:	dev->dev.coherent_dma_mask = lchip->dev->coherent_dma_mask;
+arch/arm/common/locomo.c:		dev->mapbase = lchip->base + info->offset;
+arch/arm/common/locomo.c:	dev->irq[0] = (lchip->irq_base == NO_IRQ) ?
+arch/arm/common/locomo.c:			NO_IRQ : lchip->irq_base + info->irq[0];
+arch/arm/common/locomo.c:	lchip->saved_state = save;
+arch/arm/common/locomo.c:	spin_lock_irqsave(&lchip->lock, flags);
+arch/arm/common/locomo.c:	save->LCM_GPO     = locomo_readl(lchip->base + LOCOMO_GPO);	/* GPIO */
+arch/arm/common/locomo.c:	locomo_writel(0x00, lchip->base + LOCOMO_GPO);
+arch/arm/common/locomo.c:	save->LCM_SPICT   = locomo_readl(lchip->base + LOCOMO_SPI + LOCOMO_SPICT);	/* SPI */
+arch/arm/common/locomo.c:	locomo_writel(0x40, lchip->base + LOCOMO_SPI + LOCOMO_SPICT);
+arch/arm/common/locomo.c:	save->LCM_GPE     = locomo_readl(lchip->base + LOCOMO_GPE);	/* GPIO */
+arch/arm/common/locomo.c:	locomo_writel(0x00, lchip->base + LOCOMO_GPE);
+arch/arm/common/locomo.c:	save->LCM_ASD     = locomo_readl(lchip->base + LOCOMO_ASD);	/* ADSTART */
+arch/arm/common/locomo.c:	locomo_writel(0x00, lchip->base + LOCOMO_ASD);
+arch/arm/common/locomo.c:	save->LCM_SPIMD   = locomo_readl(lchip->base + LOCOMO_SPI + LOCOMO_SPIMD);	/* SPI */
+arch/arm/common/locomo.c:	locomo_writel(0x3C14, lchip->base + LOCOMO_SPI + LOCOMO_SPIMD);
+arch/arm/common/locomo.c:	locomo_writel(0x00, lchip->base + LOCOMO_PAIF);
+arch/arm/common/locomo.c:	locomo_writel(0x00, lchip->base + LOCOMO_DAC);
+arch/arm/common/locomo.c:	locomo_writel(0x00, lchip->base + LOCOMO_BACKLIGHT + LOCOMO_TC);
+arch/arm/common/locomo.c:	if ((locomo_readl(lchip->base + LOCOMO_LED + LOCOMO_LPT0) & 0x88) && (locomo_readl(lchip->base + LOCOMO_LED + LOCOMO_LPT1) & 0x88))
+arch/arm/common/locomo.c:		locomo_writel(0x00, lchip->base + LOCOMO_C32K); 	/* CLK32 off */
+arch/arm/common/locomo.c:		locomo_writel(0xc1, lchip->base + LOCOMO_C32K); 	/* CLK32 on */
+arch/arm/common/locomo.c:	locomo_writel(0x00, lchip->base + LOCOMO_TADC);		/* 18MHz clock off*/
+arch/arm/common/locomo.c:	locomo_writel(0x00, lchip->base + LOCOMO_AUDIO + LOCOMO_ACC);			/* 22MHz/24MHz clock off */
+arch/arm/common/locomo.c:	locomo_writel(0x00, lchip->base + LOCOMO_FRONTLIGHT + LOCOMO_ALS);			/* FL */
+arch/arm/common/locomo.c:	spin_unlock_irqrestore(&lchip->lock, flags);
+arch/arm/common/locomo.c:	save = lchip->saved_state;
+arch/arm/common/locomo.c:	spin_lock_irqsave(&lchip->lock, flags);
+arch/arm/common/locomo.c:	locomo_writel(save->LCM_GPO, lchip->base + LOCOMO_GPO);
+arch/arm/common/locomo.c:	locomo_writel(save->LCM_SPICT, lchip->base + LOCOMO_SPI + LOCOMO_SPICT);
+arch/arm/common/locomo.c:	locomo_writel(save->LCM_GPE, lchip->base + LOCOMO_GPE);
+arch/arm/common/locomo.c:	locomo_writel(save->LCM_ASD, lchip->base + LOCOMO_ASD);
+arch/arm/common/locomo.c:	locomo_writel(save->LCM_SPIMD, lchip->base + LOCOMO_SPI + LOCOMO_SPIMD);
+arch/arm/common/locomo.c:	locomo_writel(0x00, lchip->base + LOCOMO_C32K);
+arch/arm/common/locomo.c:	locomo_writel(0x90, lchip->base + LOCOMO_TADC);
+arch/arm/common/locomo.c:	locomo_writel(0, lchip->base + LOCOMO_KEYBOARD + LOCOMO_KSC);
+arch/arm/common/locomo.c:	r = locomo_readl(lchip->base + LOCOMO_KEYBOARD + LOCOMO_KIC);
+arch/arm/common/locomo.c:	locomo_writel(r, lchip->base + LOCOMO_KEYBOARD + LOCOMO_KIC);
+arch/arm/common/locomo.c:	locomo_writel(0x1, lchip->base + LOCOMO_KEYBOARD + LOCOMO_KCMD);
+arch/arm/common/locomo.c:	spin_unlock_irqrestore(&lchip->lock, flags);
+arch/arm/common/locomo.c:	lchip->saved_state = NULL;
+arch/arm/common/locomo.c:	spin_lock_init(&lchip->lock);
+arch/arm/common/locomo.c:	lchip->dev = me;
+arch/arm/common/locomo.c:	dev_set_drvdata(lchip->dev, lchip);
+arch/arm/common/locomo.c:	lchip->phys = mem->start;
+arch/arm/common/locomo.c:	lchip->irq = irq;
+arch/arm/common/locomo.c:	lchip->irq_base = (pdata) ? pdata->irq_base : NO_IRQ;
+arch/arm/common/locomo.c:	lchip->base = ioremap(mem->start, PAGE_SIZE);
+arch/arm/common/locomo.c:	if (!lchip->base) {
+arch/arm/common/locomo.c:	locomo_writel(0, lchip->base + LOCOMO_ICR);
+arch/arm/common/locomo.c:	locomo_writel(0, lchip->base + LOCOMO_KEYBOARD + LOCOMO_KIC);
+arch/arm/common/locomo.c:	locomo_writel(0, lchip->base + LOCOMO_GPO);
+arch/arm/common/locomo.c:			, lchip->base + LOCOMO_GPE);
+arch/arm/common/locomo.c:			, lchip->base + LOCOMO_GPD);
+arch/arm/common/locomo.c:	locomo_writel(0, lchip->base + LOCOMO_GIE);
+arch/arm/common/locomo.c:	locomo_writel(0, lchip->base + LOCOMO_FRONTLIGHT + LOCOMO_ALS);
+arch/arm/common/locomo.c:	locomo_writel(0, lchip->base + LOCOMO_FRONTLIGHT + LOCOMO_ALD);
+arch/arm/common/locomo.c:	locomo_writel(0, lchip->base + LOCOMO_LTINT);
+arch/arm/common/locomo.c:	locomo_writel(0, lchip->base + LOCOMO_SPI + LOCOMO_SPIIE);
+arch/arm/common/locomo.c:	locomo_writel(6 + 8 + 320 + 30 - 10, lchip->base + LOCOMO_ASD);
+arch/arm/common/locomo.c:	r = locomo_readl(lchip->base + LOCOMO_ASD);
+arch/arm/common/locomo.c:	locomo_writel(r, lchip->base + LOCOMO_ASD);
+arch/arm/common/locomo.c:	locomo_writel(6 + 8 + 320 + 30 - 10 - 128 + 4, lchip->base + LOCOMO_HSD);
+arch/arm/common/locomo.c:	r = locomo_readl(lchip->base + LOCOMO_HSD);
+arch/arm/common/locomo.c:	locomo_writel(r, lchip->base + LOCOMO_HSD);
+arch/arm/common/locomo.c:	locomo_writel(128 / 8, lchip->base + LOCOMO_HSC);
+arch/arm/common/locomo.c:	locomo_writel(0x80, lchip->base + LOCOMO_TADC);
+arch/arm/common/locomo.c:	r = locomo_readl(lchip->base + LOCOMO_TADC);
+arch/arm/common/locomo.c:	locomo_writel(r, lchip->base + LOCOMO_TADC);
+arch/arm/common/locomo.c:	r = locomo_readl(lchip->base + LOCOMO_DAC);
+arch/arm/common/locomo.c:	locomo_writel(r, lchip->base + LOCOMO_DAC);
+arch/arm/common/locomo.c:	r = locomo_readl(lchip->base + LOCOMO_VER);
+arch/arm/common/locomo.c:	if (lchip->irq != NO_IRQ && lchip->irq_base != NO_IRQ)
+arch/arm/common/locomo.c:	device_for_each_child(lchip->dev, NULL, locomo_remove_child);
+arch/arm/common/locomo.c:	if (lchip->irq != NO_IRQ) {
+arch/arm/common/locomo.c:		irq_set_chained_handler_and_data(lchip->irq, NULL, NULL);
+arch/arm/common/locomo.c:	iounmap(lchip->base);
+arch/arm/common/locomo.c:	spin_lock_irqsave(&lchip->lock, flags);
+arch/arm/common/locomo.c:	r = locomo_readl(lchip->base + LOCOMO_GPD);
+arch/arm/common/locomo.c:	locomo_writel(r, lchip->base + LOCOMO_GPD);
+arch/arm/common/locomo.c:	r = locomo_readl(lchip->base + LOCOMO_GPE);
+arch/arm/common/locomo.c:	locomo_writel(r, lchip->base + LOCOMO_GPE);
+arch/arm/common/locomo.c:	spin_unlock_irqrestore(&lchip->lock, flags);
+arch/arm/common/locomo.c:	spin_lock_irqsave(&lchip->lock, flags);
+arch/arm/common/locomo.c:	ret = locomo_readl(lchip->base + LOCOMO_GPL);
+arch/arm/common/locomo.c:	spin_unlock_irqrestore(&lchip->lock, flags);
+arch/arm/common/locomo.c:	spin_lock_irqsave(&lchip->lock, flags);
+arch/arm/common/locomo.c:	ret = locomo_readl(lchip->base + LOCOMO_GPO);
+arch/arm/common/locomo.c:	spin_unlock_irqrestore(&lchip->lock, flags);
+arch/arm/common/locomo.c:	spin_lock_irqsave(&lchip->lock, flags);
+arch/arm/common/locomo.c:	r = locomo_readl(lchip->base + LOCOMO_GPO);
+arch/arm/common/locomo.c:	locomo_writel(r, lchip->base + LOCOMO_GPO);
+arch/arm/common/locomo.c:	spin_unlock_irqrestore(&lchip->lock, flags);
+arch/arm/common/locomo.c:	void *mapbase = lchip->base;
+arch/arm/common/locomo.c:	spin_lock_irqsave(&lchip->lock, flags);
+arch/arm/common/locomo.c:	spin_unlock_irqrestore(&lchip->lock, flags);
+arch/arm/common/locomo.c:	spin_lock_irqsave(&lchip->lock, flags);
+arch/arm/common/locomo.c:	locomo_writel(bpwf, lchip->base + LOCOMO_FRONTLIGHT + LOCOMO_ALS);
+arch/arm/common/locomo.c:	locomo_writel(duty, lchip->base + LOCOMO_FRONTLIGHT + LOCOMO_ALD);
+arch/arm/common/locomo.c:	locomo_writel(bpwf | LOCOMO_ALC_EN, lchip->base + LOCOMO_FRONTLIGHT + LOCOMO_ALS);
+arch/arm/common/locomo.c:	spin_unlock_irqrestore(&lchip->lock, flags);
+arch/arm/common/sa1111.c:	return irq_create_mapping(sachip->irqdomain, hwirq);
+arch/arm/common/sa1111.c:	void __iomem *mapbase = sachip->base + SA1111_INTC;
+arch/arm/common/sa1111.c:	desc->irq_data.chip->irq_ack(&desc->irq_data);
+arch/arm/common/sa1111.c:	irqdomain = sachip->irqdomain;
+arch/arm/common/sa1111.c:	desc->irq_data.chip->irq_unmask(&desc->irq_data);
+arch/arm/common/sa1111.c:	void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
+arch/arm/common/sa1111.c:	void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
+arch/arm/common/sa1111.c:	void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
+arch/arm/common/sa1111.c:	void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
+arch/arm/common/sa1111.c:	void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
+arch/arm/common/sa1111.c:	void __iomem *irqbase = sachip->base + SA1111_INTC;
+arch/arm/common/sa1111.c:	request_mem_region(sachip->phys + SA1111_INTC, 512, "irq");
+arch/arm/common/sa1111.c:		dev_err(sachip->dev, "unable to allocate %u irqs: %d\n",
+arch/arm/common/sa1111.c:	sachip->irq_base = ret;
+arch/arm/common/sa1111.c:	sachip->irqdomain = irq_domain_add_linear(NULL, SA1111_IRQ_NR,
+arch/arm/common/sa1111.c:	if (!sachip->irqdomain) {
+arch/arm/common/sa1111.c:		irq_free_descs(sachip->irq_base, SA1111_IRQ_NR);
+arch/arm/common/sa1111.c:	irq_domain_associate_many(sachip->irqdomain,
+arch/arm/common/sa1111.c:				  sachip->irq_base + IRQ_GPAIN0,
+arch/arm/common/sa1111.c:	irq_domain_associate_many(sachip->irqdomain,
+arch/arm/common/sa1111.c:				  sachip->irq_base + AUDXMTDMADONEA,
+arch/arm/common/sa1111.c:	irq_set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING);
+arch/arm/common/sa1111.c:	irq_set_chained_handler_and_data(sachip->irq, sa1111_irq_handler,
+arch/arm/common/sa1111.c:	dev_info(sachip->dev, "Providing IRQ%u-%u\n",
+arch/arm/common/sa1111.c:		sachip->irq_base, sachip->irq_base + SA1111_IRQ_NR - 1);
+arch/arm/common/sa1111.c:	struct irq_domain *domain = sachip->irqdomain;
+arch/arm/common/sa1111.c:	void __iomem *irqbase = sachip->base + SA1111_INTC;
+arch/arm/common/sa1111.c:	irq_set_chained_handler_and_data(sachip->irq, NULL, NULL);
+arch/arm/common/sa1111.c:	release_mem_region(sachip->phys + SA1111_INTC, 512);
+arch/arm/common/sa1111.c:	void __iomem *reg = sachip->base + SA1111_GPIO;
+arch/arm/common/sa1111.c:	spin_lock_irqsave(&sachip->lock, flags);
+arch/arm/common/sa1111.c:	spin_unlock_irqrestore(&sachip->lock, flags);
+arch/arm/common/sa1111.c:	spin_lock_irqsave(&sachip->lock, flags);
+arch/arm/common/sa1111.c:	spin_unlock_irqrestore(&sachip->lock, flags);
+arch/arm/common/sa1111.c:	spin_lock_irqsave(&sachip->lock, flags);
+arch/arm/common/sa1111.c:	spin_unlock_irqrestore(&sachip->lock, flags);
+arch/arm/common/sa1111.c:	void __iomem *reg = sachip->base + SA1111_GPIO;
+arch/arm/common/sa1111.c:	spin_lock_irqsave(&sachip->lock, flags);
+arch/arm/common/sa1111.c:	spin_unlock_irqrestore(&sachip->lock, flags);
+arch/arm/common/sa1111.c:	sachip->gc.label = "sa1111";
+arch/arm/common/sa1111.c:	sachip->gc.parent = sachip->dev;
+arch/arm/common/sa1111.c:	sachip->gc.owner = THIS_MODULE;
+arch/arm/common/sa1111.c:	sachip->gc.get_direction = sa1111_gpio_get_direction;
+arch/arm/common/sa1111.c:	sachip->gc.direction_input = sa1111_gpio_direction_input;
+arch/arm/common/sa1111.c:	sachip->gc.direction_output = sa1111_gpio_direction_output;
+arch/arm/common/sa1111.c:	sachip->gc.get = sa1111_gpio_get;
+arch/arm/common/sa1111.c:	sachip->gc.set = sa1111_gpio_set;
+arch/arm/common/sa1111.c:	sachip->gc.set_multiple = sa1111_gpio_set_multiple;
+arch/arm/common/sa1111.c:	sachip->gc.to_irq = sa1111_gpio_to_irq;
+arch/arm/common/sa1111.c:	sachip->gc.base = -1;
+arch/arm/common/sa1111.c:	sachip->gc.ngpio = 18;
+arch/arm/common/sa1111.c:	return devm_gpiochip_add_data(sachip->dev, &sachip->gc, sachip);
+arch/arm/common/sa1111.c:	spin_lock_irqsave(&sachip->lock, flags);
+arch/arm/common/sa1111.c:	clk_enable(sachip->clk);
+arch/arm/common/sa1111.c:	r = readl_relaxed(sachip->base + SA1111_SKCR);
+arch/arm/common/sa1111.c:	writel_relaxed(r, sachip->base + SA1111_SKCR);
+arch/arm/common/sa1111.c:	writel_relaxed(r, sachip->base + SA1111_SKCR);
+arch/arm/common/sa1111.c:	writel_relaxed(r, sachip->base + SA1111_SKCR);
+arch/arm/common/sa1111.c:	writel_relaxed(0, sachip->base + SA1111_SKPCR);
+arch/arm/common/sa1111.c:	spin_unlock_irqrestore(&sachip->lock, flags);
+arch/arm/common/sa1111.c:	writel_relaxed(smcr, sachip->base + SA1111_SMCR);
+arch/arm/common/sa1111.c:	if (sachip->dev->dma_mask)
+arch/arm/common/sa1111.c:		*sachip->dev->dma_mask &= sa1111_dma_mask[drac >> 2];
+arch/arm/common/sa1111.c:	sachip->dev->coherent_dma_mask &= sa1111_dma_mask[drac >> 2];
+arch/arm/common/sa1111.c:	dev->dev.parent  = sachip->dev;
+arch/arm/common/sa1111.c:	dev->res.start   = sachip->phys + info->offset;
+arch/arm/common/sa1111.c:	dev->mapbase     = sachip->base + info->offset;
+arch/arm/common/sa1111.c:	if (info->dma && sachip->dev->dma_mask) {
+arch/arm/common/sa1111.c:		dev->dma_mask = *sachip->dev->dma_mask;
+arch/arm/common/sa1111.c:		dev->dev.coherent_dma_mask = sachip->dev->coherent_dma_mask;
+arch/arm/common/sa1111.c:		dev_err(sachip->dev, "failed to allocate resource for %s\n",
+arch/arm/common/sa1111.c:	sachip->clk = devm_clk_get(me, "SA1111_CLK");
+arch/arm/common/sa1111.c:	if (IS_ERR(sachip->clk))
+arch/arm/common/sa1111.c:		return PTR_ERR(sachip->clk);
+arch/arm/common/sa1111.c:	ret = clk_prepare(sachip->clk);
+arch/arm/common/sa1111.c:	spin_lock_init(&sachip->lock);
+arch/arm/common/sa1111.c:	sachip->dev = me;
+arch/arm/common/sa1111.c:	dev_set_drvdata(sachip->dev, sachip);
+arch/arm/common/sa1111.c:	sachip->pdata = pd;
+arch/arm/common/sa1111.c:	sachip->phys = mem->start;
+arch/arm/common/sa1111.c:	sachip->irq = irq;
+arch/arm/common/sa1111.c:	sachip->base = ioremap(mem->start, PAGE_SIZE * 2);
+arch/arm/common/sa1111.c:	if (!sachip->base) {
+arch/arm/common/sa1111.c:	id = readl_relaxed(sachip->base + SA1111_SKID);
+arch/arm/common/sa1111.c:	val = readl_relaxed(sachip->base + SA1111_SKPCR);
+arch/arm/common/sa1111.c:	writel_relaxed(val | SKPCR_DCLKEN, sachip->base + SA1111_SKPCR);
+arch/arm/common/sa1111.c:	clk_disable(sachip->clk);
+arch/arm/common/sa1111.c:	iounmap(sachip->base);
+arch/arm/common/sa1111.c:	clk_unprepare(sachip->clk);
+arch/arm/common/sa1111.c:	device_for_each_child(sachip->dev, NULL, sa1111_remove_one);
+arch/arm/common/sa1111.c:	clk_disable(sachip->clk);
+arch/arm/common/sa1111.c:	clk_unprepare(sachip->clk);
+arch/arm/common/sa1111.c:	iounmap(sachip->base);
+arch/arm/common/sa1111.c:	sachip->saved_state = save;
+arch/arm/common/sa1111.c:	spin_lock_irqsave(&sachip->lock, flags);
+arch/arm/common/sa1111.c:	base = sachip->base;
+arch/arm/common/sa1111.c:	writel_relaxed(0, sachip->base + SA1111_SKPWM0);
+arch/arm/common/sa1111.c:	writel_relaxed(0, sachip->base + SA1111_SKPWM1);
+arch/arm/common/sa1111.c:	base = sachip->base + SA1111_INTC;
+arch/arm/common/sa1111.c:	val = readl_relaxed(sachip->base + SA1111_SKCR);
+arch/arm/common/sa1111.c:	writel_relaxed(val | SKCR_SLEEP, sachip->base + SA1111_SKCR);
+arch/arm/common/sa1111.c:	clk_disable(sachip->clk);
+arch/arm/common/sa1111.c:	spin_unlock_irqrestore(&sachip->lock, flags);
+arch/arm/common/sa1111.c:	save = sachip->saved_state;
+arch/arm/common/sa1111.c:	id = readl_relaxed(sachip->base + SA1111_SKID);
+arch/arm/common/sa1111.c:	spin_lock_irqsave(&sachip->lock, flags);
+arch/arm/common/sa1111.c:	writel_relaxed(0, sachip->base + SA1111_INTC + SA1111_INTEN0);
+arch/arm/common/sa1111.c:	writel_relaxed(0, sachip->base + SA1111_INTC + SA1111_INTEN1);
+arch/arm/common/sa1111.c:	base = sachip->base;
+arch/arm/common/sa1111.c:	base = sachip->base + SA1111_INTC;
+arch/arm/common/sa1111.c:	spin_unlock_irqrestore(&sachip->lock, flags);
+arch/arm/common/sa1111.c:	sachip->saved_state = NULL;
+arch/arm/common/sa1111.c:		kfree(sachip->saved_state);
+arch/arm/common/sa1111.c:		sachip->saved_state = NULL;
+arch/arm/common/sa1111.c:	skcdr = readl_relaxed(sachip->base + SA1111_SKCDR);
+arch/arm/common/sa1111.c:	spin_lock_irqsave(&sachip->lock, flags);
+arch/arm/common/sa1111.c:	val = readl_relaxed(sachip->base + SA1111_SKCR);
+arch/arm/common/sa1111.c:	writel_relaxed(val, sachip->base + SA1111_SKCR);
+arch/arm/common/sa1111.c:	spin_unlock_irqrestore(&sachip->lock, flags);
+arch/arm/common/sa1111.c:	writel_relaxed(div - 1, sachip->base + SA1111_SKAUD);
+arch/arm/common/sa1111.c:	div = readl_relaxed(sachip->base + SA1111_SKAUD) + 1;
+arch/arm/common/sa1111.c:	if (sachip->pdata && sachip->pdata->enable)
+arch/arm/common/sa1111.c:		ret = sachip->pdata->enable(sachip->pdata->data, sadev->devid);
+arch/arm/common/sa1111.c:		spin_lock_irqsave(&sachip->lock, flags);
+arch/arm/common/sa1111.c:		val = readl_relaxed(sachip->base + SA1111_SKPCR);
+arch/arm/common/sa1111.c:		writel_relaxed(val | sadev->skpcr_mask, sachip->base + SA1111_SKPCR);
+arch/arm/common/sa1111.c:		spin_unlock_irqrestore(&sachip->lock, flags);
+arch/arm/common/sa1111.c:	spin_lock_irqsave(&sachip->lock, flags);
+arch/arm/common/sa1111.c:	val = readl_relaxed(sachip->base + SA1111_SKPCR);
+arch/arm/common/sa1111.c:	writel_relaxed(val & ~sadev->skpcr_mask, sachip->base + SA1111_SKPCR);
+arch/arm/common/sa1111.c:	spin_unlock_irqrestore(&sachip->lock, flags);
+arch/arm/common/sa1111.c:	if (sachip->pdata && sachip->pdata->disable)
+arch/arm/common/sa1111.c:		sachip->pdata->disable(sachip->pdata->data, sadev->devid);
+arch/arm/kernel/machine_kexec.c:		if (chip->irq_eoi && irqd_irq_inprogress(&desc->irq_data))
+arch/arm/kernel/machine_kexec.c:			chip->irq_eoi(&desc->irq_data);
+arch/arm/kernel/machine_kexec.c:		if (chip->irq_mask)
+arch/arm/kernel/machine_kexec.c:			chip->irq_mask(&desc->irq_data);
+arch/arm/kernel/machine_kexec.c:		if (chip->irq_disable && !irqd_irq_disabled(&desc->irq_data))
+arch/arm/kernel/machine_kexec.c:			chip->irq_disable(&desc->irq_data);
+arch/arm/mach-ep93xx/snappercl15.c:#define NAND_CTRL_ADDR(chip) 	(chip->legacy.IO_ADDR_W + 0x40)
+arch/arm/mach-ep93xx/snappercl15.c:			     chip->legacy.IO_ADDR_W);
+arch/arm/mach-ep93xx/ts72xx.c:		void __iomem *addr = chip->legacy.IO_ADDR_R;
+arch/arm/mach-ep93xx/ts72xx.c:		__raw_writeb(cmd, chip->legacy.IO_ADDR_W);
+arch/arm/mach-ep93xx/ts72xx.c:	void __iomem *addr = chip->legacy.IO_ADDR_R;
+arch/arm/mach-imx/3ds_debugboard.c:	desc->irq_data.chip->irq_mask(&desc->irq_data);
+arch/arm/mach-imx/3ds_debugboard.c:	desc->irq_data.chip->irq_ack(&desc->irq_data);
+arch/arm/mach-imx/3ds_debugboard.c:	desc->irq_data.chip->irq_unmask(&desc->irq_data);
+arch/arm/mach-imx/mach-mx27ads.c:	vchip->owner		= THIS_MODULE;
+arch/arm/mach-imx/mach-mx27ads.c:	vchip->label		= "LCD";
+arch/arm/mach-imx/mach-mx27ads.c:	vchip->base		= MX27ADS_LCD_GPIO;
+arch/arm/mach-imx/mach-mx27ads.c:	vchip->ngpio		= 1;
+arch/arm/mach-imx/mach-mx27ads.c:	vchip->direction_output	= vgpio_dir_out;
+arch/arm/mach-imx/mach-mx27ads.c:	vchip->set		= vgpio_set;
+arch/arm/mach-imx/mach-mx35_3ds.c:	return !strcmp(chip->label, data);
+arch/arm/mach-imx/mach-mx35_3ds.c:				chip->base + GPIO_MC9S08DZ60_LCD_ENABLE;
+arch/arm/mach-imx/mach-qong.c:		writeb(cmd, nand_chip->legacy.IO_ADDR_W + (1 << 24));
+arch/arm/mach-imx/mach-qong.c:		writeb(cmd, nand_chip->legacy.IO_ADDR_W + (1 << 23));
+arch/arm/mach-omap1/ams-delta-fiq.c:			if (!WARN_ON_ONCE(!irq_chip->irq_unmask))
+arch/arm/mach-omap1/ams-delta-fiq.c:				irq_chip->irq_unmask(d);
+arch/arm/mach-omap1/ams-delta-fiq.c:	irq_chip = chip->irq.chip;
+arch/arm/mach-omap1/ams-delta-fiq.c:		       chip->label);
+arch/arm/mach-omap1/board-ams-delta.c:	return !strcmp(label, chip->label);
+arch/arm/mach-omap1/usb.c:/* These routines should handle the standard chip-specific modes
+arch/arm/mach-omap2/prm_common.c:	if (chip->irq_ack)
+arch/arm/mach-omap2/prm_common.c:		chip->irq_ack(&desc->irq_data);
+arch/arm/mach-omap2/prm_common.c:	if (chip->irq_eoi)
+arch/arm/mach-omap2/prm_common.c:		chip->irq_eoi(&desc->irq_data);
+arch/arm/mach-omap2/prm_common.c:	chip->irq_unmask(&desc->irq_data);
+arch/arm/mach-orion5x/ts78xx-setup.c:	void __iomem *io_base = chip->legacy.IO_ADDR_W;
+arch/arm/mach-orion5x/ts78xx-setup.c:	void __iomem *io_base = chip->legacy.IO_ADDR_R;
+arch/arm/mach-pxa/balloon3.c:		if (chip->irq_ack)
+arch/arm/mach-pxa/balloon3.c:			chip->irq_ack(d);
+arch/arm/mach-pxa/cm-x2xx-pci.c:	desc->irq_data.chip->irq_ack(&desc->irq_data);
+arch/arm/mach-pxa/littleton.c:	GPIO17_GPIO,	/* SFRM as chip-select */
+arch/arm/mach-pxa/lpd270.c:		desc->irq_data.chip->irq_ack(&desc->irq_data);
+arch/arm/mach-pxa/pcm990-baseboard.c:		desc->irq_data.chip->irq_ack(&desc->irq_data);
+arch/arm/mach-pxa/viper.c:		desc->irq_data.chip->irq_ack(&desc->irq_data);
+arch/arm/mach-pxa/zeus.c:		desc->irq_data.chip->irq_ack(&desc->irq_data);
+arch/arm/mach-rockchip/platsmp.c:	.name = "rockchip-pmu",
+arch/arm/mach-rpc/ecard.c:			desc->irq_data.chip->irq_mask(&desc->irq_data);
+arch/arm/mach-rpc/ecard.c:	desc->irq_data.chip->irq_mask(&desc->irq_data);
+arch/arm/mach-rpc/ecard.c:	desc->irq_data.chip->irq_unmask(&desc->irq_data);
+arch/arm/mach-s3c24xx/bast-irq.c:	desc->irq_data.chip->irq_ack(&desc->irq_data);
+arch/arm/mach-s3c24xx/bast-irq.c:		desc->irq_data.chip->irq_ack(&desc->irq_data);
+arch/arm/mach-s3c24xx/include/mach/map.h:/* physical addresses of all the chip-select areas */
+arch/arm/mach-s3c24xx/iotiming-s3c2410.c: * is actually being handled as a chip-select.
+arch/arm/mach-sa1100/neponset.c:		desc->irq_data.chip->irq_ack(&desc->irq_data);
+arch/arm/mach-sa1100/neponset.c:			desc->irq_data.chip->irq_mask(&desc->irq_data);
+arch/arm/mach-sa1100/neponset.c:			desc->irq_data.chip->irq_ack(&desc->irq_data);
+arch/arm/mach-sa1100/neponset.c:			desc->irq_data.chip->irq_unmask(&desc->irq_data);
+arch/arm/mach-u300/core.c:	for ( ; chip->chipid; chip++) {
+arch/arm/mach-u300/core.c:		if (chip->chipid == (val & 0xFF00U)) {
+arch/arm/mach-u300/core.c:			chipname = chip->name;
+arch/arm/plat-orion/gpio.c:	return ochip->base + GPIO_OUT_OFF;
+arch/arm/plat-orion/gpio.c:	return ochip->base + GPIO_IO_CONF_OFF;
+arch/arm/plat-orion/gpio.c:	return ochip->base + GPIO_BLINK_EN_OFF;
+arch/arm/plat-orion/gpio.c:	return ochip->base + GPIO_IN_POL_OFF;
+arch/arm/plat-orion/gpio.c:	return ochip->base + GPIO_DATA_IN_OFF;
+arch/arm/plat-orion/gpio.c:	return ochip->base + GPIO_EDGE_CAUSE_OFF;
+arch/arm/plat-orion/gpio.c:	return ochip->base + ochip->mask_offset + GPIO_EDGE_MASK_OFF;
+arch/arm/plat-orion/gpio.c:	return ochip->base + ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
+arch/arm/plat-orion/gpio.c:	if (pin >= ochip->chip.ngpio)
+arch/arm/plat-orion/gpio.c:	if ((mode & GPIO_INPUT_OK) && !test_bit(pin, &ochip->valid_input))
+arch/arm/plat-orion/gpio.c:	if ((mode & GPIO_OUTPUT_OK) && !test_bit(pin, &ochip->valid_output))
+arch/arm/plat-orion/gpio.c:	spin_lock_irqsave(&ochip->lock, flags);
+arch/arm/plat-orion/gpio.c:	spin_unlock_irqrestore(&ochip->lock, flags);
+arch/arm/plat-orion/gpio.c:	spin_lock_irqsave(&ochip->lock, flags);
+arch/arm/plat-orion/gpio.c:	spin_unlock_irqrestore(&ochip->lock, flags);
+arch/arm/plat-orion/gpio.c:	spin_lock_irqsave(&ochip->lock, flags);
+arch/arm/plat-orion/gpio.c:	spin_unlock_irqrestore(&ochip->lock, flags);
+arch/arm/plat-orion/gpio.c:	return irq_create_mapping(ochip->domain,
+arch/arm/plat-orion/gpio.c:				  ochip->secondary_irq_base + pin);
+arch/arm/plat-orion/gpio.c:		struct gpio_chip *chip = &ochip->chip;
+arch/arm/plat-orion/gpio.c:		if (pin >= chip->base && pin < chip->base + chip->ngpio)
+arch/arm/plat-orion/gpio.c:	pin -= ochip->chip.base;
+arch/arm/plat-orion/gpio.c:	pin -= ochip->chip.base;
+arch/arm/plat-orion/gpio.c:		__set_bit(pin, &ochip->valid_input);
+arch/arm/plat-orion/gpio.c:		__clear_bit(pin, &ochip->valid_input);
+arch/arm/plat-orion/gpio.c:		__set_bit(pin, &ochip->valid_output);
+arch/arm/plat-orion/gpio.c:		__clear_bit(pin, &ochip->valid_output);
+arch/arm/plat-orion/gpio.c:	spin_lock_irqsave(&ochip->lock, flags);
+arch/arm/plat-orion/gpio.c:	spin_unlock_irqrestore(&ochip->lock, flags);
+arch/arm/plat-orion/gpio.c:	pin = d->hwirq - ochip->secondary_irq_base;
+arch/arm/plat-orion/gpio.c:	for (i = 0; i < ochip->chip.ngpio; i++) {
+arch/arm/plat-orion/gpio.c:		irq = ochip->secondary_irq_base + i;
+arch/arm/plat-orion/gpio.c:	for (i = 0; i < chip->ngpio; i++) {
+arch/arm/plat-orion/gpio.c:		seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label);
+arch/arm/plat-orion/gpio.c:	ochip->chip.label = kstrdup(gc_label, GFP_KERNEL);
+arch/arm/plat-orion/gpio.c:	ochip->chip.request = orion_gpio_request;
+arch/arm/plat-orion/gpio.c:	ochip->chip.direction_input = orion_gpio_direction_input;
+arch/arm/plat-orion/gpio.c:	ochip->chip.get = orion_gpio_get;
+arch/arm/plat-orion/gpio.c:	ochip->chip.direction_output = orion_gpio_direction_output;
+arch/arm/plat-orion/gpio.c:	ochip->chip.set = orion_gpio_set;
+arch/arm/plat-orion/gpio.c:	ochip->chip.to_irq = orion_gpio_to_irq;
+arch/arm/plat-orion/gpio.c:	ochip->chip.base = gpio_base;
+arch/arm/plat-orion/gpio.c:	ochip->chip.ngpio = ngpio;
+arch/arm/plat-orion/gpio.c:	ochip->chip.can_sleep = 0;
+arch/arm/plat-orion/gpio.c:	ochip->chip.of_node = np;
+arch/arm/plat-orion/gpio.c:	ochip->chip.dbg_show = orion_gpio_dbg_show;
+arch/arm/plat-orion/gpio.c:	spin_lock_init(&ochip->lock);
+arch/arm/plat-orion/gpio.c:	ochip->base = (void __iomem *)base;
+arch/arm/plat-orion/gpio.c:	ochip->valid_input = 0;
+arch/arm/plat-orion/gpio.c:	ochip->valid_output = 0;
+arch/arm/plat-orion/gpio.c:	ochip->mask_offset = mask_offset;
+arch/arm/plat-orion/gpio.c:	ochip->secondary_irq_base = secondary_irq_base;
+arch/arm/plat-orion/gpio.c:	gpiochip_add_data(&ochip->chip, ochip);
+arch/arm/plat-orion/gpio.c:				    ochip->base, handle_level_irq);
+arch/arm/plat-orion/gpio.c:	ct->regs.mask = ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
+arch/arm/plat-orion/gpio.c:	ct->chip.name = ochip->chip.label;
+arch/arm/plat-orion/gpio.c:	ct->regs.mask = ochip->mask_offset + GPIO_EDGE_MASK_OFF;
+arch/arm/plat-orion/gpio.c:	ct->chip.name = ochip->chip.label;
+arch/arm/plat-orion/gpio.c:	ochip->domain = irq_domain_add_legacy(np,
+arch/arm/plat-orion/gpio.c:					      ochip->chip.ngpio,
+arch/arm/plat-orion/gpio.c:					      ochip->secondary_irq_base,
+arch/arm/plat-orion/gpio.c:					      ochip->secondary_irq_base,
+arch/arm/plat-orion/gpio.c:	if (!ochip->domain)
+arch/arm/plat-orion/gpio.c:		      ochip->chip.label);
+arch/arm/plat-samsung/gpio-samsung.c:	void __iomem *reg = chip->base + 0x08;
+arch/arm/plat-samsung/gpio-samsung.c:	void __iomem *reg = chip->base + 0x08;
+arch/arm/plat-samsung/gpio-samsung.c:	void __iomem *reg = chip->base + 0x08;
+arch/arm/plat-samsung/gpio-samsung.c:	void __iomem *reg = chip->base + 0x08;
+arch/arm/plat-samsung/gpio-samsung.c:	void __iomem *reg = chip->base;
+arch/arm/plat-samsung/gpio-samsung.c:	con = __raw_readl(chip->base);
+arch/arm/plat-samsung/gpio-samsung.c:	void __iomem *reg = chip->base;
+arch/arm/plat-samsung/gpio-samsung.c:	if (off < 8 && chip->chip.ngpio > 8)
+arch/arm/plat-samsung/gpio-samsung.c:	void __iomem *reg = chip->base;
+arch/arm/plat-samsung/gpio-samsung.c:	if (off < 8 && chip->chip.ngpio > 8)
+arch/arm/plat-samsung/gpio-samsung.c:	void __iomem *reg = chip->base;
+arch/arm/plat-samsung/gpio-samsung.c:	con = __raw_readl(chip->base);
+arch/arm/plat-samsung/gpio-samsung.c:	void __iomem *base = ourchip->base;
+arch/arm/plat-samsung/gpio-samsung.c:	void __iomem *base = ourchip->base;
+arch/arm/plat-samsung/gpio-samsung.c:	void __iomem *base = ourchip->base;
+arch/arm/plat-samsung/gpio-samsung.c:	if (ourchip->bitmap_gpio_int & BIT(offset))
+arch/arm/plat-samsung/gpio-samsung.c:	void __iomem *base = ourchip->base;
+arch/arm/plat-samsung/gpio-samsung.c: * the data register at ourchip->base + 0x04.
+arch/arm/plat-samsung/gpio-samsung.c:	void __iomem *base = ourchip->base;
+arch/arm/plat-samsung/gpio-samsung.c:	void __iomem *base = ourchip->base;
+arch/arm/plat-samsung/gpio-samsung.c:	void __iomem *base = ourchip->base;
+arch/arm/plat-samsung/gpio-samsung.c:	void __iomem *base = ourchip->base;
+arch/arm/plat-samsung/gpio-samsung.c:	val = __raw_readl(ourchip->base + 0x04);
+arch/arm/plat-samsung/gpio-samsung.c:	gpn = chip->chip.base;
+arch/arm/plat-samsung/gpio-samsung.c:	for (i = 0; i < chip->chip.ngpio; i++, gpn++) {
+arch/arm/plat-samsung/gpio-samsung.c:	struct gpio_chip *gc = &chip->chip;
+arch/arm/plat-samsung/gpio-samsung.c:	BUG_ON(!chip->base);
+arch/arm/plat-samsung/gpio-samsung.c:	spin_lock_init(&chip->lock);
+arch/arm/plat-samsung/gpio-samsung.c:	if (chip->pm != NULL) {
+arch/arm/plat-samsung/gpio-samsung.c:		if (!chip->pm->save || !chip->pm->resume)
+arch/arm/plat-samsung/gpio-samsung.c:	struct gpio_chip *gc = &chip->chip;
+arch/arm/plat-samsung/gpio-samsung.c:		if (chip->chip.base >= S3C_GPIO_END)
+arch/arm/plat-samsung/gpio-samsung.c:		if (!chip->config)
+arch/arm/plat-samsung/gpio-samsung.c:			chip->config = &s3c24xx_gpiocfg_default;
+arch/arm/plat-samsung/gpio-samsung.c:		if (!chip->pm)
+arch/arm/plat-samsung/gpio-samsung.c:			chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
+arch/arm/plat-samsung/gpio-samsung.c:		if ((base != NULL) && (chip->base == NULL))
+arch/arm/plat-samsung/gpio-samsung.c:			chip->base = base + ((i) * 0x10);
+arch/arm/plat-samsung/gpio-samsung.c:		chip->chip.direction_input = samsung_gpiolib_2bit_input;
+arch/arm/plat-samsung/gpio-samsung.c:		chip->chip.direction_output = samsung_gpiolib_2bit_output;
+arch/arm/plat-samsung/gpio-samsung.c:		if (!chip->config)
+arch/arm/plat-samsung/gpio-samsung.c:			chip->config = &samsung_gpio_cfgs[7];
+arch/arm/plat-samsung/gpio-samsung.c:		if (!chip->pm)
+arch/arm/plat-samsung/gpio-samsung.c:			chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
+arch/arm/plat-samsung/gpio-samsung.c:		if ((base != NULL) && (chip->base == NULL))
+arch/arm/plat-samsung/gpio-samsung.c:			chip->base = base + ((i) * offset);
+arch/arm/plat-samsung/gpio-samsung.c:		chip->chip.direction_input = samsung_gpiolib_4bit_input;
+arch/arm/plat-samsung/gpio-samsung.c:		chip->chip.direction_output = samsung_gpiolib_4bit_output;
+arch/arm/plat-samsung/gpio-samsung.c:		if (!chip->config)
+arch/arm/plat-samsung/gpio-samsung.c:			chip->config = &samsung_gpio_cfgs[2];
+arch/arm/plat-samsung/gpio-samsung.c:		if (!chip->pm)
+arch/arm/plat-samsung/gpio-samsung.c:			chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
+arch/arm/plat-samsung/gpio-samsung.c:		if ((base != NULL) && (chip->base == NULL))
+arch/arm/plat-samsung/gpio-samsung.c:			chip->base = base + ((i) * 0x20);
+arch/arm/plat-samsung/gpio-samsung.c:		chip->bitmap_gpio_int = 0;
+arch/arm/plat-samsung/gpio-samsung.c:		chip->chip.direction_input = samsung_gpiolib_4bit2_input;
+arch/arm/plat-samsung/gpio-samsung.c:		chip->chip.direction_output = samsung_gpiolib_4bit2_output;
+arch/arm/plat-samsung/gpio-samsung.c:		if (!chip->config)
+arch/arm/plat-samsung/gpio-samsung.c:			chip->config = &samsung_gpio_cfgs[2];
+arch/arm/plat-samsung/gpio-samsung.c:		if (!chip->pm)
+arch/arm/plat-samsung/gpio-samsung.c:			chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
+arch/arm/plat-samsung/gpio-samsung.c:	return samsung_chip->irq_base + offset;
+arch/arm/plat-samsung/gpio-samsung.c:	offset = pin - chip->chip.base;
+arch/arm/plat-samsung/gpio-samsung.c:		offset = pin - chip->chip.base;
+arch/arm/plat-samsung/gpio-samsung.c:	offset = pin - chip->chip.base;
+arch/arm/plat-samsung/gpio-samsung.c:		offset = pin - chip->chip.base;
+arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h:	return (chip->config->set_config)(chip, off, config);
+arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h:	return (chip->config->get_config)(chip, off);
+arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h:	return (chip->config->set_pull)(chip, off, pull);
+arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h:	return chip->config->get_pull(chip, off);
+arch/arm/plat-samsung/include/plat/gpio-core.h: * This helper returns the irq number calculated from the chip->irq_base and
+arch/arm/plat-samsung/include/plat/gpio-core.h:	return ((pin - chip->chip.base) < chip->chip.ngpio) ? chip : NULL;
+arch/arm/plat-samsung/pm-gpio.c:	chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON);
+arch/arm/plat-samsung/pm-gpio.c:	chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT);
+arch/arm/plat-samsung/pm-gpio.c:	void __iomem *base = chip->base;
+arch/arm/plat-samsung/pm-gpio.c:	u32 gps_gpcon = chip->pm_save[0];
+arch/arm/plat-samsung/pm-gpio.c:	u32 gps_gpdat = chip->pm_save[1];
+arch/arm/plat-samsung/pm-gpio.c:		  chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
+arch/arm/plat-samsung/pm-gpio.c:	chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON);
+arch/arm/plat-samsung/pm-gpio.c:	chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT);
+arch/arm/plat-samsung/pm-gpio.c:	chip->pm_save[2] = __raw_readl(chip->base + OFFS_UP);
+arch/arm/plat-samsung/pm-gpio.c:	void __iomem *base = chip->base;
+arch/arm/plat-samsung/pm-gpio.c:	u32 gps_gpcon = chip->pm_save[0];
+arch/arm/plat-samsung/pm-gpio.c:	u32 gps_gpdat = chip->pm_save[1];
+arch/arm/plat-samsung/pm-gpio.c:	__raw_writel(chip->pm_save[2], base + OFFS_UP);
+arch/arm/plat-samsung/pm-gpio.c:		  chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
+arch/arm/plat-samsung/pm-gpio.c:	chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON);
+arch/arm/plat-samsung/pm-gpio.c:	chip->pm_save[2] = __raw_readl(chip->base + OFFS_DAT);
+arch/arm/plat-samsung/pm-gpio.c:	chip->pm_save[3] = __raw_readl(chip->base + OFFS_UP);
+arch/arm/plat-samsung/pm-gpio.c:	if (chip->chip.ngpio > 8)
+arch/arm/plat-samsung/pm-gpio.c:		chip->pm_save[0] = __raw_readl(chip->base - 4);
+arch/arm/plat-samsung/pm-gpio.c:	void __iomem *con = chip->base + (index * 4);
+arch/arm/plat-samsung/pm-gpio.c:	u32 gps_gpcon = chip->pm_save[index + 1];
+arch/arm/plat-samsung/pm-gpio.c:	void __iomem *base = chip->base;
+arch/arm/plat-samsung/pm-gpio.c:	u32 gps_gpdat = chip->pm_save[2];
+arch/arm/plat-samsung/pm-gpio.c:	if (chip->chip.ngpio > 8) {
+arch/arm/plat-samsung/pm-gpio.c:	__raw_writel(chip->pm_save[2], base + OFFS_DAT);
+arch/arm/plat-samsung/pm-gpio.c:	__raw_writel(chip->pm_save[1], base + OFFS_CON);
+arch/arm/plat-samsung/pm-gpio.c:	if (chip->chip.ngpio > 8)
+arch/arm/plat-samsung/pm-gpio.c:		__raw_writel(chip->pm_save[0], base - 4);
+arch/arm/plat-samsung/pm-gpio.c:	__raw_writel(chip->pm_save[2], base + OFFS_DAT);
+arch/arm/plat-samsung/pm-gpio.c:	__raw_writel(chip->pm_save[3], base + OFFS_UP);
+arch/arm/plat-samsung/pm-gpio.c:	if (chip->chip.ngpio > 8) {
+arch/arm/plat-samsung/pm-gpio.c:			  chip->chip.label, old_gpcon[0], old_gpcon[1],
+arch/arm/plat-samsung/pm-gpio.c:			  chip->chip.label, old_gpcon[1],
+arch/arm/plat-samsung/pm-gpio.c:	struct samsung_gpio_pm *pm = ourchip->pm;
+arch/arm/plat-samsung/pm-gpio.c:		S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label);
+arch/arm/plat-samsung/pm-gpio.c:			  ourchip->chip.label,
+arch/arm/plat-samsung/pm-gpio.c:			  ourchip->pm_save[0],
+arch/arm/plat-samsung/pm-gpio.c:			  ourchip->pm_save[1],
+arch/arm/plat-samsung/pm-gpio.c:			  ourchip->pm_save[2],
+arch/arm/plat-samsung/pm-gpio.c:			  ourchip->pm_save[3]);
+arch/arm/plat-samsung/pm-gpio.c:		gpio_nr += ourchip->chip.ngpio;
+arch/arm/plat-samsung/pm-gpio.c:	struct samsung_gpio_pm *pm = ourchip->pm;
+arch/arm/plat-samsung/pm-gpio.c:		S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label);
+arch/arm/plat-samsung/pm-gpio.c:		gpio_nr += ourchip->chip.ngpio;
+arch/arm64/boot/dts/amlogic/meson-axg.dtsi:				amlogic,has-chip-id;
+arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi:				amlogic,has-chip-id;
+arch/arm64/boot/dts/amlogic/meson-gx.dtsi:				amlogic,has-chip-id;
+arch/arm64/boot/dts/rockchip/rk3328-a1.dts:		chip_en: chip-en {
+arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi:	rockchip-key {
+arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi:		/* chip-internal connection for HDMI */
+arch/arm64/kernel/machine_kexec.c:		    chip->irq_eoi)
+arch/arm64/kernel/machine_kexec.c:			chip->irq_eoi(&desc->irq_data);
+arch/arm64/kernel/machine_kexec.c:		if (chip->irq_mask)
+arch/arm64/kernel/machine_kexec.c:			chip->irq_mask(&desc->irq_data);
+arch/arm64/kernel/machine_kexec.c:		if (chip->irq_disable && !irqd_irq_disabled(&desc->irq_data))
+arch/arm64/kernel/machine_kexec.c:			chip->irq_disable(&desc->irq_data);
+arch/ia64/kernel/iosapic.c:			       chip->name, irq_type->name);
+arch/ia64/kernel/irq.c:			if (chip && chip->irq_disable &&
+arch/ia64/kernel/irq.c:				chip->irq_enable && chip->irq_set_affinity) {
+arch/ia64/kernel/irq.c:				chip->irq_disable(data);
+arch/ia64/kernel/irq.c:				chip->irq_set_affinity(data,
+arch/ia64/kernel/irq.c:				chip->irq_enable(data);
+arch/ia64/kernel/irq.c:				WARN_ON((!chip || !chip->irq_disable ||
+arch/ia64/kernel/irq.c:					 !chip->irq_enable ||
+arch/ia64/kernel/irq.c:					 !chip->irq_set_affinity));
+arch/ia64/kernel/smpboot.c:				data->chip->irq_disable(data);
+arch/ia64/kernel/smpboot.c:				data->chip->irq_set_affinity(data, mask, false);
+arch/ia64/kernel/smpboot.c:				data->chip->irq_enable(data);
+arch/microblaze/mm/init.c: * MMU_init_hw does the chip-specific initialization of the MMU hardware.
+arch/mips/bcm63xx/gpio.c:	if (gpio >= chip->ngpio)
+arch/mips/bcm63xx/gpio.c:	if (gpio >= chip->ngpio)
+arch/mips/bcm63xx/gpio.c:	if (gpio >= chip->ngpio)
+arch/mips/boot/dts/mscc/ocelot.dtsi:			compatible = "mscc,ocelot-chip-reset";
+arch/mips/cavium-octeon/octeon-irq.c:	data->chip->irq_ack(data);
+arch/mips/cavium-octeon/octeon-irq.c:	data->chip->irq_enable(data);
+arch/mips/loongson64/irq.c:	chip->irq_set_affinity = plat_set_irq_affinity;
+arch/mips/pmcs-msp71xx/msp_setup.c:	/* No chip-specific reset code, just jump to the ROM reset vector */
+arch/mips/rb532/devices.c:		writeb(cmd, chip->legacy.IO_ADDR_W);
+arch/mips/rb532/gpio.c:	rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOILEVEL);
+arch/mips/rb532/gpio.c:	rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOISTAT);
+arch/mips/rb532/gpio.c:       rb532_set_bit(1, gpio, rb532_gpio_chip->regbase + GPIOFUNC);
+arch/mips/rb532/gpio.c:	rb532_gpio_chip->regbase = ioremap_nocache(r->start, resource_size(r));
+arch/mips/rb532/gpio.c:	if (!rb532_gpio_chip->regbase) {
+arch/mips/rb532/gpio.c:	gpiochip_add_data(&rb532_gpio_chip->chip, rb532_gpio_chip);
+arch/mips/vr41xx/common/irq.c:		if (chip->irq_mask_ack)
+arch/mips/vr41xx/common/irq.c:			chip->irq_mask_ack(idata);
+arch/mips/vr41xx/common/irq.c:			chip->irq_mask(idata);
+arch/mips/vr41xx/common/irq.c:			chip->irq_ack(idata);
+arch/mips/vr41xx/common/irq.c:		if (!irqd_irq_disabled(idata) && chip->irq_unmask)
+arch/mips/vr41xx/common/irq.c:			chip->irq_unmask(idata);
+arch/powerpc/boot/dts/icon.dts:			reset-type = <2>;	/* Use chip-reset */
+arch/powerpc/boot/dts/katmai.dts:			reset-type = <2>;	/* Use chip-reset */
+arch/powerpc/boot/dts/tqm8548-bigflash.dts:			chip-delay = <25>; // in micro-seconds
+arch/powerpc/boot/dts/tqm8548.dts:			chip-delay = <25>; // in micro-seconds
+arch/powerpc/kernel/prom.c: * of_get_ibm_chip_id - Returns the IBM "chip-id" of a device
+arch/powerpc/kernel/prom.c: * This looks for a property "ibm,chip-id" in the node or any
+arch/powerpc/kernel/prom.c:		 * cell in chip-id, we only read the first one here.
+arch/powerpc/kernel/prom.c:		if (!of_property_read_u32(np, "ibm,chip-id", &chip_id)) {
+arch/powerpc/kernel/prom.c: * cpu_to_chip_id - Return the cpus chip-id
+arch/powerpc/kernel/prom.c: * Return the value of the ibm,chip-id property corresponding to the given
+arch/powerpc/kernel/prom.c: * logical cpu number. If the chip-id can not be found, returns -1.
+arch/powerpc/kexec/core.c:		if (chip->irq_eoi && irqd_irq_inprogress(&desc->irq_data))
+arch/powerpc/kexec/core.c:			chip->irq_eoi(&desc->irq_data);
+arch/powerpc/kexec/core.c:		if (chip->irq_mask)
+arch/powerpc/kexec/core.c:			chip->irq_mask(&desc->irq_data);
+arch/powerpc/kexec/core.c:		if (chip->irq_disable && !irqd_irq_disabled(&desc->irq_data))
+arch/powerpc/kexec/core.c:			chip->irq_disable(&desc->irq_data);
+arch/powerpc/mm/nohash/40x.c: * MMU_init_hw does the chip-specific initialization of the MMU hardware.
+arch/powerpc/mm/nohash/8xx.c: * MMU_init_hw does the chip-specific initialization of the MMU hardware.
+arch/powerpc/mm/nohash/fsl_booke.c: * MMU_init_hw does the chip-specific initialization of the MMU hardware.
+arch/powerpc/platforms/4xx/gpio.c:	spin_lock_irqsave(&chip->lock, flags);
+arch/powerpc/platforms/4xx/gpio.c:	spin_unlock_irqrestore(&chip->lock, flags);
+arch/powerpc/platforms/4xx/gpio.c:	spin_lock_irqsave(&chip->lock, flags);
+arch/powerpc/platforms/4xx/gpio.c:	spin_unlock_irqrestore(&chip->lock, flags);
+arch/powerpc/platforms/4xx/gpio.c:	spin_lock_irqsave(&chip->lock, flags);
+arch/powerpc/platforms/4xx/gpio.c:	spin_unlock_irqrestore(&chip->lock, flags);
+arch/powerpc/platforms/4xx/uic.c:		chip->irq_mask(idata);
+arch/powerpc/platforms/4xx/uic.c:		chip->irq_mask_ack(idata);
+arch/powerpc/platforms/4xx/uic.c:		chip->irq_ack(idata);
+arch/powerpc/platforms/4xx/uic.c:	if (!irqd_irq_disabled(idata) && chip->irq_unmask)
+arch/powerpc/platforms/4xx/uic.c:		chip->irq_unmask(idata);
+arch/powerpc/platforms/52xx/media5200.c:	chip->irq_mask(&desc->irq_data);
+arch/powerpc/platforms/52xx/media5200.c:	chip->irq_ack(&desc->irq_data);
+arch/powerpc/platforms/52xx/media5200.c:		chip->irq_unmask(&desc->irq_data);
+arch/powerpc/platforms/85xx/common.c:	chip->irq_eoi(&desc->irq_data);
+arch/powerpc/platforms/85xx/mpc85xx_ds.c:	chip->irq_eoi(&desc->irq_data);
+arch/powerpc/platforms/85xx/socrates_fpga_pic.c:	chip->irq_eoi(&desc->irq_data);
+arch/powerpc/platforms/86xx/pic.c:	chip->irq_eoi(&desc->irq_data);
+arch/powerpc/platforms/cell/axon_msi.c:	chip->irq_eoi(&desc->irq_data);
+arch/powerpc/platforms/cell/interrupt.c:	chip->irq_eoi(&desc->irq_data);
+arch/powerpc/platforms/cell/spider-pic.c:	chip->irq_eoi(&desc->irq_data);
+arch/powerpc/platforms/chrp/setup.c:	chip->irq_eoi(&desc->irq_data);
+arch/powerpc/platforms/embedded6xx/hlwd-pic.c:	chip->irq_mask(&desc->irq_data); /* IRQ_LEVEL */
+arch/powerpc/platforms/embedded6xx/hlwd-pic.c:	chip->irq_ack(&desc->irq_data); /* IRQ_LEVEL */
+arch/powerpc/platforms/embedded6xx/hlwd-pic.c:	if (!irqd_irq_disabled(&desc->irq_data) && chip->irq_unmask)
+arch/powerpc/platforms/embedded6xx/hlwd-pic.c:		chip->irq_unmask(&desc->irq_data);
+arch/powerpc/platforms/embedded6xx/mvme5100.c:	chip->irq_eoi(&desc->irq_data);
+arch/powerpc/platforms/pasemi/setup.c:	chip->irq_eoi(&desc->irq_data);
+arch/powerpc/platforms/powernv/opal-imc.c:	nr_chips = of_property_count_u32_elems(node, "chip-id");
+arch/powerpc/platforms/powernv/opal-imc.c:	if (of_property_read_u32_array(node, "chip-id", chipid_arr, nr_chips))
+arch/powerpc/platforms/powernv/opal-sensor-groups.c:		if (!of_property_read_u32(node, "ibm,chip-id", &chipid))
+arch/powerpc/platforms/powernv/pci-ioda.c:	return chip->irq_eoi == pnv_ioda2_msi_eoi;
+arch/powerpc/platforms/powernv/rng.c:		pr_warn("No ibm,chip-id found for %pOF.\n", dn);
+arch/powerpc/platforms/pseries/setup.c:	chip->irq_eoi(&desc->irq_data);
+arch/powerpc/sysdev/ge/ge_pic.c:	chip->irq_eoi(&desc->irq_data);
+arch/powerpc/sysdev/mpic.c:	chip->irq_eoi(&desc->irq_data);
+arch/powerpc/sysdev/tsi108_pci.c:	chip->irq_eoi(&desc->irq_data);
+arch/powerpc/sysdev/xics/xics-common.c:		if (!chip || !chip->irq_set_affinity)
+arch/powerpc/sysdev/xilinx_intc.c:	chip->irq_unmask(&desc->irq_data);
+arch/powerpc/sysdev/xive/spapr.c:	 * No chip-id for the sPAPR backend. This has an impact how we
+arch/s390/kernel/irq.c:		seq_printf(p, " %8s", desc->irq_data.chip->name);
+arch/sh/boards/mach-migor/setup.c:		writeb(cmd, chip->legacy.IO_ADDR_W + 0x00400000);
+arch/sh/boards/mach-migor/setup.c:		writeb(cmd, chip->legacy.IO_ADDR_W + 0x00800000);
+arch/sh/boards/mach-migor/setup.c:		writeb(cmd, chip->legacy.IO_ADDR_W);
+arch/sh/boards/mach-se/7343/irq.c:	chip->irq_mask_ack(data);
+arch/sh/boards/mach-se/7343/irq.c:	chip->irq_unmask(data);
+arch/sh/boards/mach-se/7722/irq.c:	chip->irq_mask_ack(data);
+arch/sh/boards/mach-se/7722/irq.c:	chip->irq_unmask(data);
+arch/sh/boards/mach-x3proto/gpio.c:	if (gpio < chip->ngpio)
+arch/sh/boards/mach-x3proto/gpio.c:	chip->irq_mask_ack(data);
+arch/sh/boards/mach-x3proto/gpio.c:	chip->irq_unmask(data);
+arch/sparc/kernel/irq_32.c: * up via the irq_chip->startup() method which gets invoked by
+arch/sparc/kernel/irq_64.c:			if (data->chip->irq_set_affinity)
+arch/sparc/kernel/irq_64.c:				data->chip->irq_set_affinity(data,
+arch/sparc/kernel/leon_pci_grpci1.c:		desc->irq_data.chip->irq_eoi(&desc->irq_data);
+arch/sparc/kernel/leon_pci_grpci2.c:		desc->irq_data.chip->irq_eoi(&desc->irq_data);
+arch/x86/Kconfig.cpu:	  - "Winchip-C6" for original IDT Winchip.
+arch/x86/Kconfig.cpu:	  - "Winchip-2" for IDT Winchips with 3dNow! capabilities.
+arch/x86/Kconfig.cpu:	bool "Winchip-C6"
+arch/x86/Kconfig.cpu:	bool "Winchip-2/Winchip-2A/Winchip-3"
+arch/x86/Kconfig.cpu:	  Select this for an IDT Winchip-2, 2A or 3.  Linux and GCC
+arch/x86/Makefile_32.cpu:cflags-$(CONFIG_MWINCHIPC6)	+= $(call cc-option,-march=winchip-c6,-march=i586)
+arch/x86/kernel/apic/io_apic.c:	ret = parent->chip->irq_set_affinity(parent, mask, force);
+arch/x86/kernel/irq.c:			if (chip->irq_retrigger) {
+arch/x86/kernel/irq.c:				chip->irq_retrigger(data);
+arch/x86/kvm/x86.c:	switch (chip->chip_id) {
+arch/x86/kvm/x86.c:		memcpy(&chip->chip.pic, &pic->pics[0],
+arch/x86/kvm/x86.c:		memcpy(&chip->chip.pic, &pic->pics[1],
+arch/x86/kvm/x86.c:		kvm_get_ioapic(kvm, &chip->chip.ioapic);
+arch/x86/kvm/x86.c:	switch (chip->chip_id) {
+arch/x86/kvm/x86.c:		memcpy(&pic->pics[0], &chip->chip.pic,
+arch/x86/kvm/x86.c:		memcpy(&pic->pics[1], &chip->chip.pic,
+arch/x86/kvm/x86.c:		kvm_set_ioapic(kvm, &chip->chip.ioapic);
+arch/x86/platform/uv/uv_irq.c:	ret = parent->chip->irq_set_affinity(parent, mask, force);
+drivers/acpi/arm64/iort.c:	its_msi_chip->fw_node = fw_node;
+drivers/acpi/arm64/iort.c:	its_msi_chip->translation_id = trans_id;
+drivers/acpi/arm64/iort.c:	its_msi_chip->base_addr = base;
+drivers/acpi/arm64/iort.c:	list_add(&its_msi_chip->list, &iort_msi_chip_list);
+drivers/acpi/arm64/iort.c:		if (its_msi_chip->translation_id == trans_id) {
+drivers/acpi/arm64/iort.c:			list_del(&its_msi_chip->list);
+drivers/acpi/arm64/iort.c:		if (its_msi_chip->translation_id == trans_id) {
+drivers/acpi/arm64/iort.c:			fw_node = its_msi_chip->fw_node;
+drivers/acpi/arm64/iort.c:		if (its_msi_chip->translation_id == its_id) {
+drivers/acpi/arm64/iort.c:			*base = its_msi_chip->base_addr;
+drivers/ata/sata_mv.c:	 * Handle chip-reported errors, or continue on to handle PIO.
+drivers/base/platform-msi.c:	if (!chip->irq_mask)
+drivers/base/platform-msi.c:		chip->irq_mask = irq_chip_mask_parent;
+drivers/base/platform-msi.c:	if (!chip->irq_unmask)
+drivers/base/platform-msi.c:		chip->irq_unmask = irq_chip_unmask_parent;
+drivers/base/platform-msi.c:	if (!chip->irq_eoi)
+drivers/base/platform-msi.c:		chip->irq_eoi = irq_chip_eoi_parent;
+drivers/base/platform-msi.c:	if (!chip->irq_set_affinity)
+drivers/base/platform-msi.c:		chip->irq_set_affinity = msi_domain_set_affinity;
+drivers/base/platform-msi.c:	if (!chip->irq_write_msi_msg)
+drivers/base/platform-msi.c:		chip->irq_write_msi_msg = platform_msi_write_msg;
+drivers/base/platform-msi.c:		    !(chip->flags & IRQCHIP_SUPPORTS_LEVEL_MSI)))
+drivers/base/regmap/regmap-irq.c:	return &data->chip->irqs[irq];
+drivers/base/regmap/regmap-irq.c:	if (d->chip->mask_writeonly)
+drivers/base/regmap/regmap-irq.c:	if (d->chip->runtime_pm) {
+drivers/base/regmap/regmap-irq.c:		for (i = 0; i < d->chip->num_regs; i++) {
+drivers/base/regmap/regmap-irq.c:			reg = d->chip->status_base +
+drivers/base/regmap/regmap-irq.c:	for (i = 0; i < d->chip->num_regs; i++) {
+drivers/base/regmap/regmap-irq.c:		if (!d->chip->mask_base)
+drivers/base/regmap/regmap-irq.c:		reg = d->chip->mask_base +
+drivers/base/regmap/regmap-irq.c:		if (d->chip->mask_invert) {
+drivers/base/regmap/regmap-irq.c:		} else if (d->chip->unmask_base) {
+drivers/base/regmap/regmap-irq.c:			unmask_offset = d->chip->unmask_base -
+drivers/base/regmap/regmap-irq.c:							d->chip->mask_base;
+drivers/base/regmap/regmap-irq.c:		reg = d->chip->wake_base +
+drivers/base/regmap/regmap-irq.c:			if (d->chip->wake_invert)
+drivers/base/regmap/regmap-irq.c:		if (!d->chip->init_ack_masked)
+drivers/base/regmap/regmap-irq.c:		if (d->mask_buf[i] && (d->chip->ack_base || d->chip->use_ack)) {
+drivers/base/regmap/regmap-irq.c:			reg = d->chip->ack_base +
+drivers/base/regmap/regmap-irq.c:			if (d->chip->ack_invert)
+drivers/base/regmap/regmap-irq.c:	if (!d->chip->type_in_mask) {
+drivers/base/regmap/regmap-irq.c:		for (i = 0; i < d->chip->num_type_reg; i++) {
+drivers/base/regmap/regmap-irq.c:			reg = d->chip->type_base +
+drivers/base/regmap/regmap-irq.c:			if (d->chip->type_invert)
+drivers/base/regmap/regmap-irq.c:	if (d->chip->runtime_pm)
+drivers/base/regmap/regmap-irq.c:	if (d->chip->type_in_mask && type)
+drivers/base/regmap/regmap-irq.c:	if (d->chip->clear_on_unmask)
+drivers/base/regmap/regmap-irq.c:	if (!chip->sub_reg_offsets) {
+drivers/base/regmap/regmap-irq.c:		ret = regmap_read(map, chip->status_base +
+drivers/base/regmap/regmap-irq.c:		subreg = &chip->sub_reg_offsets[b];
+drivers/base/regmap/regmap-irq.c:			ret = regmap_read(map, chip->status_base + offset,
+drivers/base/regmap/regmap-irq.c:	if (chip->handle_pre_irq)
+drivers/base/regmap/regmap-irq.c:		chip->handle_pre_irq(chip->irq_drv_data);
+drivers/base/regmap/regmap-irq.c:	if (chip->runtime_pm) {
+drivers/base/regmap/regmap-irq.c:	if (chip->num_main_regs) {
+drivers/base/regmap/regmap-irq.c:		size = chip->num_regs * sizeof(unsigned int);
+drivers/base/regmap/regmap-irq.c:		max_main_bits = (chip->num_main_status_bits) ?
+drivers/base/regmap/regmap-irq.c:				 chip->num_main_status_bits : chip->num_regs;
+drivers/base/regmap/regmap-irq.c:		for (i = 0; i < chip->num_main_regs; i++) {
+drivers/base/regmap/regmap-irq.c:			ret = regmap_read(map, chip->main_status +
+drivers/base/regmap/regmap-irq.c:		for (i = 0; i < chip->num_main_regs; i++) {
+drivers/base/regmap/regmap-irq.c:		ret = regmap_bulk_read(map, chip->status_base,
+drivers/base/regmap/regmap-irq.c:				       chip->num_regs);
+drivers/base/regmap/regmap-irq.c:		for (i = 0; i < data->chip->num_regs; i++) {
+drivers/base/regmap/regmap-irq.c:		for (i = 0; i < data->chip->num_regs; i++) {
+drivers/base/regmap/regmap-irq.c:			ret = regmap_read(map, chip->status_base +
+drivers/base/regmap/regmap-irq.c:	for (i = 0; i < data->chip->num_regs; i++) {
+drivers/base/regmap/regmap-irq.c:		if (data->status_buf[i] && (chip->ack_base || chip->use_ack)) {
+drivers/base/regmap/regmap-irq.c:			reg = chip->ack_base +
+drivers/base/regmap/regmap-irq.c:	for (i = 0; i < chip->num_irqs; i++) {
+drivers/base/regmap/regmap-irq.c:		if (data->status_buf[chip->irqs[i].reg_offset /
+drivers/base/regmap/regmap-irq.c:				     map->reg_stride] & chip->irqs[i].mask) {
+drivers/base/regmap/regmap-irq.c:	if (chip->runtime_pm)
+drivers/base/regmap/regmap-irq.c:	if (chip->handle_post_irq)
+drivers/base/regmap/regmap-irq.c:		chip->handle_post_irq(chip->irq_drv_data);
+drivers/base/regmap/regmap-irq.c:	if (chip->num_regs <= 0)
+drivers/base/regmap/regmap-irq.c:	if (chip->clear_on_unmask && (chip->ack_base || chip->use_ack))
+drivers/base/regmap/regmap-irq.c:	for (i = 0; i < chip->num_irqs; i++) {
+drivers/base/regmap/regmap-irq.c:		if (chip->irqs[i].reg_offset % map->reg_stride)
+drivers/base/regmap/regmap-irq.c:		if (chip->irqs[i].reg_offset / map->reg_stride >=
+drivers/base/regmap/regmap-irq.c:		    chip->num_regs)
+drivers/base/regmap/regmap-irq.c:		irq_base = irq_alloc_descs(irq_base, 0, chip->num_irqs, 0);
+drivers/base/regmap/regmap-irq.c:	if (chip->num_main_regs) {
+drivers/base/regmap/regmap-irq.c:		d->main_status_buf = kcalloc(chip->num_main_regs,
+drivers/base/regmap/regmap-irq.c:	d->status_buf = kcalloc(chip->num_regs, sizeof(unsigned int),
+drivers/base/regmap/regmap-irq.c:	d->mask_buf = kcalloc(chip->num_regs, sizeof(unsigned int),
+drivers/base/regmap/regmap-irq.c:	d->mask_buf_def = kcalloc(chip->num_regs, sizeof(unsigned int),
+drivers/base/regmap/regmap-irq.c:	if (chip->wake_base) {
+drivers/base/regmap/regmap-irq.c:		d->wake_buf = kcalloc(chip->num_regs, sizeof(unsigned int),
+drivers/base/regmap/regmap-irq.c:	num_type_reg = chip->type_in_mask ? chip->num_regs : chip->num_type_reg;
+drivers/base/regmap/regmap-irq.c:	d->irq_chip.name = chip->name;
+drivers/base/regmap/regmap-irq.c:	if (chip->irq_reg_stride)
+drivers/base/regmap/regmap-irq.c:		d->irq_reg_stride = chip->irq_reg_stride;
+drivers/base/regmap/regmap-irq.c:	if (chip->type_reg_stride)
+drivers/base/regmap/regmap-irq.c:		d->type_reg_stride = chip->type_reg_stride;
+drivers/base/regmap/regmap-irq.c:		d->status_reg_buf = kmalloc_array(chip->num_regs,
+drivers/base/regmap/regmap-irq.c:	for (i = 0; i < chip->num_irqs; i++)
+drivers/base/regmap/regmap-irq.c:		d->mask_buf_def[chip->irqs[i].reg_offset / map->reg_stride]
+drivers/base/regmap/regmap-irq.c:			|= chip->irqs[i].mask;
+drivers/base/regmap/regmap-irq.c:	for (i = 0; i < chip->num_regs; i++) {
+drivers/base/regmap/regmap-irq.c:		if (!chip->mask_base)
+drivers/base/regmap/regmap-irq.c:		reg = chip->mask_base +
+drivers/base/regmap/regmap-irq.c:		if (chip->mask_invert)
+drivers/base/regmap/regmap-irq.c:		else if (d->chip->unmask_base) {
+drivers/base/regmap/regmap-irq.c:			unmask_offset = d->chip->unmask_base -
+drivers/base/regmap/regmap-irq.c:					d->chip->mask_base;
+drivers/base/regmap/regmap-irq.c:		if (!chip->init_ack_masked)
+drivers/base/regmap/regmap-irq.c:		reg = chip->status_base +
+drivers/base/regmap/regmap-irq.c:		if (d->status_buf[i] && (chip->ack_base || chip->use_ack)) {
+drivers/base/regmap/regmap-irq.c:			reg = chip->ack_base +
+drivers/base/regmap/regmap-irq.c:			if (chip->ack_invert)
+drivers/base/regmap/regmap-irq.c:		for (i = 0; i < chip->num_regs; i++) {
+drivers/base/regmap/regmap-irq.c:			reg = chip->wake_base +
+drivers/base/regmap/regmap-irq.c:			if (chip->wake_invert)
+drivers/base/regmap/regmap-irq.c:	if (chip->num_type_reg && !chip->type_in_mask) {
+drivers/base/regmap/regmap-irq.c:		for (i = 0; i < chip->num_type_reg; ++i) {
+drivers/base/regmap/regmap-irq.c:			reg = chip->type_base +
+drivers/base/regmap/regmap-irq.c:			if (d->chip->type_invert)
+drivers/base/regmap/regmap-irq.c:						  chip->num_irqs, irq_base, 0,
+drivers/base/regmap/regmap-irq.c:						  chip->num_irqs,
+drivers/base/regmap/regmap-irq.c:				   chip->name, d);
+drivers/base/regmap/regmap-irq.c:			irq, chip->name, ret);
+drivers/base/regmap/regmap-irq.c:	for (hwirq = 0; hwirq < d->chip->num_irqs; hwirq++) {
+drivers/base/regmap/regmap-irq.c:		if (!d->chip->irqs[hwirq].mask)
+drivers/base/regmap/regmap-irq.c:	if (!data->chip->irqs[irq].mask)
+drivers/bcma/driver_gpio.c:	chip->label		= "bcma_gpio";
+drivers/bcma/driver_gpio.c:	chip->owner		= THIS_MODULE;
+drivers/bcma/driver_gpio.c:	chip->request		= bcma_gpio_request;
+drivers/bcma/driver_gpio.c:	chip->free		= bcma_gpio_free;
+drivers/bcma/driver_gpio.c:	chip->get		= bcma_gpio_get_value;
+drivers/bcma/driver_gpio.c:	chip->set		= bcma_gpio_set_value;
+drivers/bcma/driver_gpio.c:	chip->direction_input	= bcma_gpio_direction_input;
+drivers/bcma/driver_gpio.c:	chip->direction_output	= bcma_gpio_direction_output;
+drivers/bcma/driver_gpio.c:	chip->owner		= THIS_MODULE;
+drivers/bcma/driver_gpio.c:	chip->parent		= bus->dev;
+drivers/bcma/driver_gpio.c:	chip->of_node		= cc->core->dev.of_node;
+drivers/bcma/driver_gpio.c:		chip->ngpio	= 32;
+drivers/bcma/driver_gpio.c:		chip->ngpio	= 16;
+drivers/bcma/driver_gpio.c:		chip->base		= bus->num * BCMA_GPIO_MAX_PINS;
+drivers/bcma/driver_gpio.c:		chip->base		= -1;
+drivers/bus/fsl-mc/fsl-mc-msi.c:	if (!chip->irq_write_msi_msg)
+drivers/bus/fsl-mc/fsl-mc-msi.c:		chip->irq_write_msi_msg = fsl_mc_msi_write_msg;
+drivers/bus/tegra-gmi.c:	 * chip-select address decoding. Which means that we only have one
+drivers/bus/tegra-gmi.c:	 * chip-select line from the GMI controller.
+drivers/char/tpm/eventlog/acpi.c:	if (chip->flags & TPM_CHIP_FLAG_TPM2)
+drivers/char/tpm/eventlog/acpi.c:	log = &chip->log;
+drivers/char/tpm/eventlog/acpi.c:	if (!chip->acpi_dev_handle)
+drivers/char/tpm/eventlog/acpi.c:		dev_warn(&chip->dev, "%s: TCPA log area empty\n", __func__);
+drivers/char/tpm/eventlog/common.c:	get_device(&chip->dev);
+drivers/char/tpm/eventlog/common.c:	put_device(&chip->dev);
+drivers/char/tpm/eventlog/common.c:	if (chip->log.bios_event_log != NULL) {
+drivers/char/tpm/eventlog/common.c:		dev_dbg(&chip->dev,
+drivers/char/tpm/eventlog/common.c:	const char *name = dev_name(&chip->dev);
+drivers/char/tpm/eventlog/common.c:	chip->bios_dir[cnt] = securityfs_create_dir(name, NULL);
+drivers/char/tpm/eventlog/common.c:	if (IS_ERR(chip->bios_dir[cnt]))
+drivers/char/tpm/eventlog/common.c:	chip->bin_log_seqops.chip = chip;
+drivers/char/tpm/eventlog/common.c:		chip->bin_log_seqops.seqops =
+drivers/char/tpm/eventlog/common.c:		chip->bin_log_seqops.seqops =
+drivers/char/tpm/eventlog/common.c:	chip->bios_dir[cnt] =
+drivers/char/tpm/eventlog/common.c:				   0440, chip->bios_dir[0],
+drivers/char/tpm/eventlog/common.c:				   (void *)&chip->bin_log_seqops,
+drivers/char/tpm/eventlog/common.c:	if (IS_ERR(chip->bios_dir[cnt]))
+drivers/char/tpm/eventlog/common.c:	if (!(chip->flags & TPM_CHIP_FLAG_TPM2)) {
+drivers/char/tpm/eventlog/common.c:		chip->ascii_log_seqops.chip = chip;
+drivers/char/tpm/eventlog/common.c:		chip->ascii_log_seqops.seqops =
+drivers/char/tpm/eventlog/common.c:		chip->bios_dir[cnt] =
+drivers/char/tpm/eventlog/common.c:					       0440, chip->bios_dir[0],
+drivers/char/tpm/eventlog/common.c:					       (void *)&chip->ascii_log_seqops,
+drivers/char/tpm/eventlog/common.c:		if (IS_ERR(chip->bios_dir[cnt]))
+drivers/char/tpm/eventlog/common.c:	rc = PTR_ERR(chip->bios_dir[cnt]);
+drivers/char/tpm/eventlog/common.c:	chip->bios_dir[cnt] = NULL;
+drivers/char/tpm/eventlog/common.c:		if (chip->bios_dir[i]) {
+drivers/char/tpm/eventlog/common.c:			inode = d_inode(chip->bios_dir[i]);
+drivers/char/tpm/eventlog/common.c:			securityfs_remove(chip->bios_dir[i]);
+drivers/char/tpm/eventlog/efi.c:	if (!(chip->flags & TPM_CHIP_FLAG_TPM2))
+drivers/char/tpm/eventlog/efi.c:	log = &chip->log;
+drivers/char/tpm/eventlog/of.c:	log = &chip->log;
+drivers/char/tpm/eventlog/of.c:	if (chip->dev.parent && chip->dev.parent->of_node)
+drivers/char/tpm/eventlog/of.c:		np = chip->dev.parent->of_node;
+drivers/char/tpm/eventlog/of.c:		chip->flags |= TPM_CHIP_FLAG_ALWAYS_POWERED;
+drivers/char/tpm/eventlog/of.c:		dev_warn(&chip->dev, "%s: Event log area empty\n", __func__);
+drivers/char/tpm/eventlog/of.c:	if (chip->flags & TPM_CHIP_FLAG_TPM2)
+drivers/char/tpm/eventlog/tpm1.c:	struct tpm_bios_log *log = &chip->log;
+drivers/char/tpm/eventlog/tpm1.c:	struct tpm_bios_log *log = &chip->log;
+drivers/char/tpm/eventlog/tpm2.c:	struct tpm_bios_log *log = &chip->log;
+drivers/char/tpm/eventlog/tpm2.c:	struct tpm_bios_log *log = &chip->log;
+drivers/char/tpm/eventlog/tpm2.c:	struct tpm_bios_log *log = &chip->log;
+drivers/char/tpm/st33zp24/i2c.c:	struct st33zp24_dev *tpm_dev = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/st33zp24/i2c.c:	struct st33zp24_dev *tpm_dev = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/st33zp24/i2c.c:	struct st33zp24_dev *tpm_dev = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/st33zp24/spi.c:	struct st33zp24_dev *tpm_dev = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/st33zp24/spi.c:	struct st33zp24_dev *tpm_dev = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/st33zp24/spi.c:	struct st33zp24_dev *tpm_dev = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/st33zp24/st33zp24.c:	struct st33zp24_dev *tpm_dev = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/st33zp24/st33zp24.c:	struct st33zp24_dev *tpm_dev = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/st33zp24/st33zp24.c:	struct st33zp24_dev *tpm_dev = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/st33zp24/st33zp24.c:	struct st33zp24_dev *tpm_dev = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/st33zp24/st33zp24.c:	stop = jiffies + chip->timeout_a;
+drivers/char/tpm/st33zp24/st33zp24.c:	struct st33zp24_dev *tpm_dev = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/st33zp24/st33zp24.c:	struct st33zp24_dev *tpm_dev = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/st33zp24/st33zp24.c:	stop = jiffies + chip->timeout_d;
+drivers/char/tpm/st33zp24/st33zp24.c:	u8 status = chip->ops->status(chip);
+drivers/char/tpm/st33zp24/st33zp24.c:	if (check_cancel && chip->ops->req_canceled(chip, status)) {
+drivers/char/tpm/st33zp24/st33zp24.c:	struct st33zp24_dev *tpm_dev = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/st33zp24/st33zp24.c:	if (chip->flags & TPM_CHIP_FLAG_IRQ) {
+drivers/char/tpm/st33zp24/st33zp24.c:			status = chip->ops->status(chip);
+drivers/char/tpm/st33zp24/st33zp24.c:	struct st33zp24_dev *tpm_dev = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/st33zp24/st33zp24.c:			     chip->timeout_c,
+drivers/char/tpm/st33zp24/st33zp24.c:	struct st33zp24_dev *tpm_dev = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/st33zp24/st33zp24.c:	struct st33zp24_dev *tpm_dev = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/st33zp24/st33zp24.c:		    (chip, TPM_STS_COMMAND_READY, chip->timeout_b,
+drivers/char/tpm/st33zp24/st33zp24.c:	if (chip->flags & TPM_CHIP_FLAG_IRQ) {
+drivers/char/tpm/st33zp24/st33zp24.c:		dev_err(&chip->dev, "Unable to read header\n");
+drivers/char/tpm/st33zp24/st33zp24.c:		dev_err(&chip->dev, "Unable to read remainder of result\n");
+drivers/char/tpm/st33zp24/st33zp24.c:	dev_set_drvdata(&chip->dev, tpm_dev);
+drivers/char/tpm/st33zp24/st33zp24.c:	chip->timeout_a = msecs_to_jiffies(TIS_SHORT_TIMEOUT);
+drivers/char/tpm/st33zp24/st33zp24.c:	chip->timeout_b = msecs_to_jiffies(TIS_LONG_TIMEOUT);
+drivers/char/tpm/st33zp24/st33zp24.c:	chip->timeout_c = msecs_to_jiffies(TIS_SHORT_TIMEOUT);
+drivers/char/tpm/st33zp24/st33zp24.c:	chip->timeout_d = msecs_to_jiffies(TIS_SHORT_TIMEOUT);
+drivers/char/tpm/st33zp24/st33zp24.c:			dev_err(&chip->dev, "TPM SERIRQ signals %d not available\n",
+drivers/char/tpm/st33zp24/st33zp24.c:		chip->flags |= TPM_CHIP_FLAG_IRQ;
+drivers/char/tpm/st33zp24/st33zp24.c:	dev_info(&chip->dev, "TPM initialization fail\n");
+drivers/char/tpm/st33zp24/st33zp24.c:	struct st33zp24_dev *tpm_dev = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/st33zp24/st33zp24.c:	struct st33zp24_dev *tpm_dev = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/st33zp24/st33zp24.c:				TPM_STS_VALID, chip->timeout_b,
+drivers/char/tpm/tpm-chip.c:	if (!chip->ops->request_locality)
+drivers/char/tpm/tpm-chip.c:	rc = chip->ops->request_locality(chip, 0);
+drivers/char/tpm/tpm-chip.c:	chip->locality = rc;
+drivers/char/tpm/tpm-chip.c:	if (!chip->ops->relinquish_locality)
+drivers/char/tpm/tpm-chip.c:	rc = chip->ops->relinquish_locality(chip, chip->locality);
+drivers/char/tpm/tpm-chip.c:		dev_err(&chip->dev, "%s: : error %d\n", __func__, rc);
+drivers/char/tpm/tpm-chip.c:	chip->locality = -1;
+drivers/char/tpm/tpm-chip.c:	if (!chip->ops->cmd_ready)
+drivers/char/tpm/tpm-chip.c:	return chip->ops->cmd_ready(chip);
+drivers/char/tpm/tpm-chip.c:	if (!chip->ops->go_idle)
+drivers/char/tpm/tpm-chip.c:	return chip->ops->go_idle(chip);
+drivers/char/tpm/tpm-chip.c:	if (chip->ops->clk_enable)
+drivers/char/tpm/tpm-chip.c:		chip->ops->clk_enable(chip, true);
+drivers/char/tpm/tpm-chip.c:	if (chip->ops->clk_enable)
+drivers/char/tpm/tpm-chip.c:		chip->ops->clk_enable(chip, false);
+drivers/char/tpm/tpm-chip.c:	if (chip->locality == -1) {
+drivers/char/tpm/tpm-chip.c:	get_device(&chip->dev);
+drivers/char/tpm/tpm-chip.c:	down_read(&chip->ops_sem);
+drivers/char/tpm/tpm-chip.c:	if (!chip->ops)
+drivers/char/tpm/tpm-chip.c:	mutex_lock(&chip->tpm_mutex);
+drivers/char/tpm/tpm-chip.c:	mutex_unlock(&chip->tpm_mutex);
+drivers/char/tpm/tpm-chip.c:	up_read(&chip->ops_sem);
+drivers/char/tpm/tpm-chip.c:	put_device(&chip->dev);
+drivers/char/tpm/tpm-chip.c:	mutex_unlock(&chip->tpm_mutex);
+drivers/char/tpm/tpm-chip.c:	up_read(&chip->ops_sem);
+drivers/char/tpm/tpm-chip.c:	put_device(&chip->dev);
+drivers/char/tpm/tpm-chip.c:			get_device(&chip->dev);
+drivers/char/tpm/tpm-chip.c:	put_device(&chip->dev);
+drivers/char/tpm/tpm-chip.c:	idr_remove(&dev_nums_idr, chip->dev_num);
+drivers/char/tpm/tpm-chip.c:	kfree(chip->log.bios_event_log);
+drivers/char/tpm/tpm-chip.c:	kfree(chip->work_space.context_buf);
+drivers/char/tpm/tpm-chip.c:	kfree(chip->work_space.session_buf);
+drivers/char/tpm/tpm-chip.c:	kfree(chip->allocated_banks);
+drivers/char/tpm/tpm-chip.c:	put_device(&chip->dev);
+drivers/char/tpm/tpm-chip.c:	down_write(&chip->ops_sem);
+drivers/char/tpm/tpm-chip.c:	if (chip->flags & TPM_CHIP_FLAG_TPM2) {
+drivers/char/tpm/tpm-chip.c:	chip->ops = NULL;
+drivers/char/tpm/tpm-chip.c:	up_write(&chip->ops_sem);
+drivers/char/tpm/tpm-chip.c: * device number for it. Must be paired with put_device(&chip->dev).
+drivers/char/tpm/tpm-chip.c:	mutex_init(&chip->tpm_mutex);
+drivers/char/tpm/tpm-chip.c:	init_rwsem(&chip->ops_sem);
+drivers/char/tpm/tpm-chip.c:	chip->ops = ops;
+drivers/char/tpm/tpm-chip.c:	chip->dev_num = rc;
+drivers/char/tpm/tpm-chip.c:	device_initialize(&chip->dev);
+drivers/char/tpm/tpm-chip.c:	device_initialize(&chip->devs);
+drivers/char/tpm/tpm-chip.c:	chip->dev.class = tpm_class;
+drivers/char/tpm/tpm-chip.c:	chip->dev.class->shutdown_pre = tpm_class_shutdown;
+drivers/char/tpm/tpm-chip.c:	chip->dev.release = tpm_dev_release;
+drivers/char/tpm/tpm-chip.c:	chip->dev.parent = pdev;
+drivers/char/tpm/tpm-chip.c:	chip->dev.groups = chip->groups;
+drivers/char/tpm/tpm-chip.c:	chip->devs.parent = pdev;
+drivers/char/tpm/tpm-chip.c:	chip->devs.class = tpmrm_class;
+drivers/char/tpm/tpm-chip.c:	chip->devs.release = tpm_devs_release;
+drivers/char/tpm/tpm-chip.c:	if (chip->flags & TPM_CHIP_FLAG_TPM2)
+drivers/char/tpm/tpm-chip.c:		get_device(&chip->dev);
+drivers/char/tpm/tpm-chip.c:	if (chip->dev_num == 0)
+drivers/char/tpm/tpm-chip.c:		chip->dev.devt = MKDEV(MISC_MAJOR, TPM_MINOR);
+drivers/char/tpm/tpm-chip.c:		chip->dev.devt = MKDEV(MAJOR(tpm_devt), chip->dev_num);
+drivers/char/tpm/tpm-chip.c:	chip->devs.devt =
+drivers/char/tpm/tpm-chip.c:		MKDEV(MAJOR(tpm_devt), chip->dev_num + TPM_NUM_DEVICES);
+drivers/char/tpm/tpm-chip.c:	rc = dev_set_name(&chip->dev, "tpm%d", chip->dev_num);
+drivers/char/tpm/tpm-chip.c:	rc = dev_set_name(&chip->devs, "tpmrm%d", chip->dev_num);
+drivers/char/tpm/tpm-chip.c:		chip->flags |= TPM_CHIP_FLAG_VIRTUAL;
+drivers/char/tpm/tpm-chip.c:	cdev_init(&chip->cdev, &tpm_fops);
+drivers/char/tpm/tpm-chip.c:	cdev_init(&chip->cdevs, &tpmrm_fops);
+drivers/char/tpm/tpm-chip.c:	chip->cdev.owner = THIS_MODULE;
+drivers/char/tpm/tpm-chip.c:	chip->cdevs.owner = THIS_MODULE;
+drivers/char/tpm/tpm-chip.c:	chip->work_space.context_buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
+drivers/char/tpm/tpm-chip.c:	if (!chip->work_space.context_buf) {
+drivers/char/tpm/tpm-chip.c:	chip->work_space.session_buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
+drivers/char/tpm/tpm-chip.c:	if (!chip->work_space.session_buf) {
+drivers/char/tpm/tpm-chip.c:	chip->locality = -1;
+drivers/char/tpm/tpm-chip.c:	put_device(&chip->devs);
+drivers/char/tpm/tpm-chip.c:	put_device(&chip->dev);
+drivers/char/tpm/tpm-chip.c:				      &chip->dev);
+drivers/char/tpm/tpm-chip.c:	rc = cdev_device_add(&chip->cdev, &chip->dev);
+drivers/char/tpm/tpm-chip.c:		dev_err(&chip->dev,
+drivers/char/tpm/tpm-chip.c:			dev_name(&chip->dev), MAJOR(chip->dev.devt),
+drivers/char/tpm/tpm-chip.c:			MINOR(chip->dev.devt), rc);
+drivers/char/tpm/tpm-chip.c:	if (chip->flags & TPM_CHIP_FLAG_TPM2) {
+drivers/char/tpm/tpm-chip.c:		rc = cdev_device_add(&chip->cdevs, &chip->devs);
+drivers/char/tpm/tpm-chip.c:			dev_err(&chip->devs,
+drivers/char/tpm/tpm-chip.c:				dev_name(&chip->devs), MAJOR(chip->devs.devt),
+drivers/char/tpm/tpm-chip.c:				MINOR(chip->devs.devt), rc);
+drivers/char/tpm/tpm-chip.c:	idr_replace(&dev_nums_idr, chip, chip->dev_num);
+drivers/char/tpm/tpm-chip.c:	cdev_device_del(&chip->cdev, &chip->dev);
+drivers/char/tpm/tpm-chip.c:	idr_replace(&dev_nums_idr, NULL, chip->dev_num);
+drivers/char/tpm/tpm-chip.c:	down_write(&chip->ops_sem);
+drivers/char/tpm/tpm-chip.c:	if (chip->flags & TPM_CHIP_FLAG_TPM2) {
+drivers/char/tpm/tpm-chip.c:	chip->ops = NULL;
+drivers/char/tpm/tpm-chip.c:	up_write(&chip->ops_sem);
+drivers/char/tpm/tpm-chip.c:	if (chip->flags & (TPM_CHIP_FLAG_TPM2 | TPM_CHIP_FLAG_VIRTUAL))
+drivers/char/tpm/tpm-chip.c:	sysfs_remove_link(&chip->dev.parent->kobj, "ppi");
+drivers/char/tpm/tpm-chip.c:	for (i = chip->groups[0]->attrs; *i != NULL; ++i)
+drivers/char/tpm/tpm-chip.c:		sysfs_remove_link(&chip->dev.parent->kobj, (*i)->name);
+drivers/char/tpm/tpm-chip.c:	if (chip->flags & (TPM_CHIP_FLAG_TPM2 | TPM_CHIP_FLAG_VIRTUAL))
+drivers/char/tpm/tpm-chip.c:		    &chip->dev.parent->kobj, &chip->dev.kobj, "ppi");
+drivers/char/tpm/tpm-chip.c:	for (i = chip->groups[0]->attrs; *i != NULL; ++i) {
+drivers/char/tpm/tpm-chip.c:		    &chip->dev.parent->kobj, &chip->dev.kobj, (*i)->name);
+drivers/char/tpm/tpm-chip.c:	snprintf(chip->hwrng_name, sizeof(chip->hwrng_name),
+drivers/char/tpm/tpm-chip.c:		 "tpm-rng-%d", chip->dev_num);
+drivers/char/tpm/tpm-chip.c:	chip->hwrng.name = chip->hwrng_name;
+drivers/char/tpm/tpm-chip.c:	chip->hwrng.read = tpm_hwrng_read;
+drivers/char/tpm/tpm-chip.c:	return hwrng_register(&chip->hwrng);
+drivers/char/tpm/tpm-chip.c:	rc = (chip->flags & TPM_CHIP_FLAG_TPM2) ?
+drivers/char/tpm/tpm-chip.c:		hwrng_unregister(&chip->hwrng);
+drivers/char/tpm/tpm-chip.c:		hwrng_unregister(&chip->hwrng);
+drivers/char/tpm/tpm-chip.c:	if (chip->flags & TPM_CHIP_FLAG_TPM2)
+drivers/char/tpm/tpm-chip.c:		cdev_device_del(&chip->cdevs, &chip->devs);
+drivers/char/tpm/tpm-dev.c:	if (test_and_set_bit(0, &chip->is_open)) {
+drivers/char/tpm/tpm-dev.c:		dev_dbg(&chip->dev, "Another process owns this TPM\n");
+drivers/char/tpm/tpm-dev.c:	clear_bit(0, &chip->is_open);
+drivers/char/tpm/tpm-dev.c:	clear_bit(0, &priv->chip->is_open);
+drivers/char/tpm/tpm-interface.c:	if (chip->flags & TPM_CHIP_FLAG_TPM2)
+drivers/char/tpm/tpm-interface.c:		dev_err(&chip->dev,
+drivers/char/tpm/tpm-interface.c:	rc = chip->ops->send(chip, buf, count);
+drivers/char/tpm/tpm-interface.c:			dev_err(&chip->dev,
+drivers/char/tpm/tpm-interface.c:		dev_warn(&chip->dev,
+drivers/char/tpm/tpm-interface.c:	if (chip->flags & TPM_CHIP_FLAG_IRQ)
+drivers/char/tpm/tpm-interface.c:		u8 status = chip->ops->status(chip);
+drivers/char/tpm/tpm-interface.c:		if ((status & chip->ops->req_complete_mask) ==
+drivers/char/tpm/tpm-interface.c:		    chip->ops->req_complete_val)
+drivers/char/tpm/tpm-interface.c:		if (chip->ops->req_canceled(chip, status)) {
+drivers/char/tpm/tpm-interface.c:			dev_err(&chip->dev, "Operation Canceled\n");
+drivers/char/tpm/tpm-interface.c:	chip->ops->cancel(chip);
+drivers/char/tpm/tpm-interface.c:	dev_err(&chip->dev, "Operation Timed out\n");
+drivers/char/tpm/tpm-interface.c:	len = chip->ops->recv(chip, buf, bufsiz);
+drivers/char/tpm/tpm-interface.c:		dev_err(&chip->dev, "tpm_transmit: tpm_recv: error %d\n", rc);
+drivers/char/tpm/tpm-interface.c:				dev_err(&chip->dev, "in retry loop\n");
+drivers/char/tpm/tpm-interface.c:				dev_err(&chip->dev,
+drivers/char/tpm/tpm-interface.c:		dev_err(&chip->dev, "A TPM error (%d) occurred %s\n", err,
+drivers/char/tpm/tpm-interface.c:	if (chip->flags & TPM_CHIP_FLAG_HAVE_TIMEOUTS)
+drivers/char/tpm/tpm-interface.c:	if (chip->flags & TPM_CHIP_FLAG_TPM2)
+drivers/char/tpm/tpm-interface.c:	rc = (chip->flags & TPM_CHIP_FLAG_TPM2) != 0;
+drivers/char/tpm/tpm-interface.c:	if (chip->flags & TPM_CHIP_FLAG_TPM2)
+drivers/char/tpm/tpm-interface.c: * order of the banks in chip->allocated_banks.
+drivers/char/tpm/tpm-interface.c:	for (i = 0; i < chip->nr_allocated_banks; i++) {
+drivers/char/tpm/tpm-interface.c:		if (digests[i].alg_id != chip->allocated_banks[i].alg_id) {
+drivers/char/tpm/tpm-interface.c:	if (chip->flags & TPM_CHIP_FLAG_TPM2) {
+drivers/char/tpm/tpm-interface.c:	if (!(chip->ops->flags & TPM_OPS_AUTO_STARTUP))
+drivers/char/tpm/tpm-interface.c:	if (chip->flags & TPM_CHIP_FLAG_TPM2)
+drivers/char/tpm/tpm-interface.c:	if (chip->flags & TPM_CHIP_FLAG_ALWAYS_POWERED)
+drivers/char/tpm/tpm-interface.c:	if ((chip->flags & TPM_CHIP_FLAG_FIRMWARE_POWER_MANAGED) &&
+drivers/char/tpm/tpm-interface.c:		if (chip->flags & TPM_CHIP_FLAG_TPM2)
+drivers/char/tpm/tpm-interface.c:	if (chip->flags & TPM_CHIP_FLAG_TPM2)
+drivers/char/tpm/tpm-sysfs.c:	chip->ops->cancel(chip);
+drivers/char/tpm/tpm-sysfs.c:	if (chip->duration[TPM_LONG] == 0)
+drivers/char/tpm/tpm-sysfs.c:		       jiffies_to_usecs(chip->duration[TPM_SHORT]),
+drivers/char/tpm/tpm-sysfs.c:		       jiffies_to_usecs(chip->duration[TPM_MEDIUM]),
+drivers/char/tpm/tpm-sysfs.c:		       jiffies_to_usecs(chip->duration[TPM_LONG]),
+drivers/char/tpm/tpm-sysfs.c:		       chip->duration_adjusted
+drivers/char/tpm/tpm-sysfs.c:		       jiffies_to_usecs(chip->timeout_a),
+drivers/char/tpm/tpm-sysfs.c:		       jiffies_to_usecs(chip->timeout_b),
+drivers/char/tpm/tpm-sysfs.c:		       jiffies_to_usecs(chip->timeout_c),
+drivers/char/tpm/tpm-sysfs.c:		       jiffies_to_usecs(chip->timeout_d),
+drivers/char/tpm/tpm-sysfs.c:		       chip->timeout_adjusted
+drivers/char/tpm/tpm-sysfs.c:	if (chip->flags & TPM_CHIP_FLAG_TPM2)
+drivers/char/tpm/tpm-sysfs.c:	WARN_ON(chip->groups_cnt != 0);
+drivers/char/tpm/tpm-sysfs.c:	chip->groups[chip->groups_cnt++] = &tpm_dev_group;
+drivers/char/tpm/tpm1-cmd.c:		duration = chip->duration[duration_idx];
+drivers/char/tpm/tpm1-cmd.c:	dev_info(&chip->dev, "starting up the TPM manually\n");
+drivers/char/tpm/tpm1-cmd.c:		dev_err(&chip->dev, "A TPM error (%zd) occurred attempting to determine the timeouts\n",
+drivers/char/tpm/tpm1-cmd.c:	timeout_old[0] = jiffies_to_usecs(chip->timeout_a);
+drivers/char/tpm/tpm1-cmd.c:	timeout_old[1] = jiffies_to_usecs(chip->timeout_b);
+drivers/char/tpm/tpm1-cmd.c:	timeout_old[2] = jiffies_to_usecs(chip->timeout_c);
+drivers/char/tpm/tpm1-cmd.c:	timeout_old[3] = jiffies_to_usecs(chip->timeout_d);
+drivers/char/tpm/tpm1-cmd.c:	if (chip->ops->update_timeouts)
+drivers/char/tpm/tpm1-cmd.c:		chip->ops->update_timeouts(chip, timeout_eff);
+drivers/char/tpm/tpm1-cmd.c:	if (!chip->timeout_adjusted) {
+drivers/char/tpm/tpm1-cmd.c:			chip->timeout_adjusted = true;
+drivers/char/tpm/tpm1-cmd.c:			chip->timeout_adjusted = true;
+drivers/char/tpm/tpm1-cmd.c:	if (chip->timeout_adjusted) {
+drivers/char/tpm/tpm1-cmd.c:		dev_info(&chip->dev, HW_ERR "Adjusting reported timeouts: A %lu->%luus B %lu->%luus C %lu->%luus D %lu->%luus\n",
+drivers/char/tpm/tpm1-cmd.c:	chip->timeout_a = usecs_to_jiffies(timeout_eff[0]);
+drivers/char/tpm/tpm1-cmd.c:	chip->timeout_b = usecs_to_jiffies(timeout_eff[1]);
+drivers/char/tpm/tpm1-cmd.c:	chip->timeout_c = usecs_to_jiffies(timeout_eff[2]);
+drivers/char/tpm/tpm1-cmd.c:	chip->timeout_d = usecs_to_jiffies(timeout_eff[3]);
+drivers/char/tpm/tpm1-cmd.c:	chip->duration[TPM_SHORT] =
+drivers/char/tpm/tpm1-cmd.c:	chip->duration[TPM_MEDIUM] =
+drivers/char/tpm/tpm1-cmd.c:	chip->duration[TPM_LONG] =
+drivers/char/tpm/tpm1-cmd.c:	chip->duration[TPM_LONG_LONG] = 0; /* not used under 1.2 */
+drivers/char/tpm/tpm1-cmd.c:	if (chip->ops->update_durations)
+drivers/char/tpm/tpm1-cmd.c:		chip->ops->update_durations(chip, durations);
+drivers/char/tpm/tpm1-cmd.c:	if (chip->duration_adjusted) {
+drivers/char/tpm/tpm1-cmd.c:		dev_info(&chip->dev, HW_ERR "Adjusting reported durations.");
+drivers/char/tpm/tpm1-cmd.c:		chip->duration[TPM_SHORT] = durations[0];
+drivers/char/tpm/tpm1-cmd.c:		chip->duration[TPM_MEDIUM] = durations[1];
+drivers/char/tpm/tpm1-cmd.c:		chip->duration[TPM_LONG] = durations[2];
+drivers/char/tpm/tpm1-cmd.c:	if (chip->duration[TPM_SHORT] < (HZ / 100)) {
+drivers/char/tpm/tpm1-cmd.c:		chip->duration[TPM_SHORT] = HZ;
+drivers/char/tpm/tpm1-cmd.c:		chip->duration[TPM_MEDIUM] *= 1000;
+drivers/char/tpm/tpm1-cmd.c:		chip->duration[TPM_LONG] *= 1000;
+drivers/char/tpm/tpm1-cmd.c:		chip->duration_adjusted = true;
+drivers/char/tpm/tpm1-cmd.c:		dev_info(&chip->dev, "Adjusting TPM timeout parameters.");
+drivers/char/tpm/tpm1-cmd.c:	chip->flags |= TPM_CHIP_FLAG_HAVE_TIMEOUTS;
+drivers/char/tpm/tpm1-cmd.c:		chip->flags |= TPM_CHIP_FLAG_ALWAYS_POWERED;
+drivers/char/tpm/tpm1-cmd.c:		dev_info(&chip->dev, "TPM not ready (%d)\n", rc);
+drivers/char/tpm/tpm1-cmd.c:			dev_info(&chip->dev, HW_ERR "TPM command timed out during continue self test");
+drivers/char/tpm/tpm1-cmd.c:			dev_info(&chip->dev, "TPM is disabled/deactivated (0x%X)\n",
+drivers/char/tpm/tpm1-cmd.c:		dev_err(&chip->dev, "TPM self test failed\n");
+drivers/char/tpm/tpm1-cmd.c:		dev_err(&chip->dev, "Error (%d) sending savestate before suspend\n",
+drivers/char/tpm/tpm1-cmd.c:		dev_warn(&chip->dev, "TPM savestate took %dms\n",
+drivers/char/tpm/tpm1-cmd.c:	chip->allocated_banks = kcalloc(1, sizeof(*chip->allocated_banks),
+drivers/char/tpm/tpm1-cmd.c:	if (!chip->allocated_banks)
+drivers/char/tpm/tpm1-cmd.c:	chip->allocated_banks[0].alg_id = TPM_ALG_SHA1;
+drivers/char/tpm/tpm1-cmd.c:	chip->allocated_banks[0].digest_size = hash_digest_size[HASH_ALGO_SHA1];
+drivers/char/tpm/tpm1-cmd.c:	chip->allocated_banks[0].crypto_id = HASH_ALGO_SHA1;
+drivers/char/tpm/tpm1-cmd.c:	chip->nr_allocated_banks = 1;
+drivers/char/tpm/tpm2-cmd.c:	chip->timeout_a = msecs_to_jiffies(TPM2_TIMEOUT_A);
+drivers/char/tpm/tpm2-cmd.c:	chip->timeout_b = msecs_to_jiffies(TPM2_TIMEOUT_B);
+drivers/char/tpm/tpm2-cmd.c:	chip->timeout_c = msecs_to_jiffies(TPM2_TIMEOUT_C);
+drivers/char/tpm/tpm2-cmd.c:	chip->timeout_d = msecs_to_jiffies(TPM2_TIMEOUT_D);
+drivers/char/tpm/tpm2-cmd.c:	chip->duration[TPM_SHORT] = msecs_to_jiffies(TPM2_DURATION_SHORT);
+drivers/char/tpm/tpm2-cmd.c:	chip->duration[TPM_MEDIUM] = msecs_to_jiffies(TPM2_DURATION_MEDIUM);
+drivers/char/tpm/tpm2-cmd.c:	chip->duration[TPM_LONG] = msecs_to_jiffies(TPM2_DURATION_LONG);
+drivers/char/tpm/tpm2-cmd.c:	chip->duration[TPM_LONG_LONG] =
+drivers/char/tpm/tpm2-cmd.c:	chip->flags |= TPM_CHIP_FLAG_HAVE_TIMEOUTS;
+drivers/char/tpm/tpm2-cmd.c:		return chip->duration[index];
+drivers/char/tpm/tpm2-cmd.c:		for (i = 0; i < chip->nr_allocated_banks &&
+drivers/char/tpm/tpm2-cmd.c:		     chip->allocated_banks[i].alg_id != digest->alg_id; i++)
+drivers/char/tpm/tpm2-cmd.c:		if (i == chip->nr_allocated_banks)
+drivers/char/tpm/tpm2-cmd.c:		expected_digest_size = chip->allocated_banks[i].digest_size;
+drivers/char/tpm/tpm2-cmd.c:	tpm_buf_append_u32(&buf, chip->nr_allocated_banks);
+drivers/char/tpm/tpm2-cmd.c:	for (i = 0; i < chip->nr_allocated_banks; i++) {
+drivers/char/tpm/tpm2-cmd.c:			       chip->allocated_banks[i].digest_size);
+drivers/char/tpm/tpm2-cmd.c:		dev_warn(&chip->dev, "0x%08x was not flushed, out of memory\n",
+drivers/char/tpm/tpm2-cmd.c:			chip->flags |= TPM_CHIP_FLAG_TPM2;
+drivers/char/tpm/tpm2-cmd.c:	struct tpm_bank_info *bank = chip->allocated_banks + bank_index;
+drivers/char/tpm/tpm2-cmd.c:	chip->allocated_banks = kcalloc(nr_possible_banks,
+drivers/char/tpm/tpm2-cmd.c:					sizeof(*chip->allocated_banks),
+drivers/char/tpm/tpm2-cmd.c:	if (!chip->allocated_banks) {
+drivers/char/tpm/tpm2-cmd.c:			chip->allocated_banks[nr_alloc_banks].alg_id = hash_alg;
+drivers/char/tpm/tpm2-cmd.c:	chip->nr_allocated_banks = nr_alloc_banks;
+drivers/char/tpm/tpm2-cmd.c:	chip->cc_attrs_tbl = devm_kcalloc(&chip->dev, 4, nr_commands,
+drivers/char/tpm/tpm2-cmd.c:	if (!chip->cc_attrs_tbl) {
+drivers/char/tpm/tpm2-cmd.c:	chip->nr_commands = nr_commands;
+drivers/char/tpm/tpm2-cmd.c:		chip->cc_attrs_tbl[i] = be32_to_cpup(attrs);
+drivers/char/tpm/tpm2-cmd.c:		cc = chip->cc_attrs_tbl[i] & 0xFFFF;
+drivers/char/tpm/tpm2-cmd.c:			chip->cc_attrs_tbl[i] &=
+drivers/char/tpm/tpm2-cmd.c:			chip->cc_attrs_tbl[i] |= 1 << TPM2_CC_ATTR_CHANDLES;
+drivers/char/tpm/tpm2-cmd.c:	dev_info(&chip->dev, "starting up the TPM manually\n");
+drivers/char/tpm/tpm2-cmd.c:	for (i = 0; i < chip->nr_commands; i++)
+drivers/char/tpm/tpm2-cmd.c:		if (cc == (chip->cc_attrs_tbl[i] & GENMASK(15, 0)))
+drivers/char/tpm/tpm2-space.c:	mutex_lock(&chip->tpm_mutex);
+drivers/char/tpm/tpm2-space.c:	mutex_unlock(&chip->tpm_mutex);
+drivers/char/tpm/tpm2-space.c:		dev_warn(&chip->dev, "%s: failed with a system error %d\n",
+drivers/char/tpm/tpm2-space.c:		dev_warn(&chip->dev, "%s: failed with a TPM error 0x%04X\n",
+drivers/char/tpm/tpm2-space.c:		dev_warn(&chip->dev, "%s: failed with a system error %d\n",
+drivers/char/tpm/tpm2-space.c:		dev_warn(&chip->dev, "%s: failed with a TPM error 0x%04X\n",
+drivers/char/tpm/tpm2-space.c:		dev_warn(&chip->dev, "%s: out of backing storage\n", __func__);
+drivers/char/tpm/tpm2-space.c:	struct tpm_space *space = &chip->work_space;
+drivers/char/tpm/tpm2-space.c:	struct tpm_space *space = &chip->work_space;
+drivers/char/tpm/tpm2-space.c:			dev_err(&chip->dev, "context table is inconsistent");
+drivers/char/tpm/tpm2-space.c:			dev_warn(&chip->dev, "session restored to wrong handle\n");
+drivers/char/tpm/tpm2-space.c:	struct tpm_space *space = &chip->work_space;
+drivers/char/tpm/tpm2-space.c:	attrs = chip->cc_attrs_tbl[i];
+drivers/char/tpm/tpm2-space.c:	if (len < TPM_HEADER_SIZE || !chip->nr_commands)
+drivers/char/tpm/tpm2-space.c:		dev_dbg(&chip->dev, "0x%04X is an invalid command\n",
+drivers/char/tpm/tpm2-space.c:	attrs = chip->cc_attrs_tbl[i];
+drivers/char/tpm/tpm2-space.c:	dev_dbg(&chip->dev, "%s: insufficient command length %zu", __func__,
+drivers/char/tpm/tpm2-space.c:	memcpy(&chip->work_space.context_tbl, &space->context_tbl,
+drivers/char/tpm/tpm2-space.c:	memcpy(&chip->work_space.session_tbl, &space->session_tbl,
+drivers/char/tpm/tpm2-space.c:	memcpy(chip->work_space.context_buf, space->context_buf, PAGE_SIZE);
+drivers/char/tpm/tpm2-space.c:	memcpy(chip->work_space.session_buf, space->session_buf, PAGE_SIZE);
+drivers/char/tpm/tpm2-space.c:	chip->last_cc = cc;
+drivers/char/tpm/tpm2-space.c:	struct tpm_space *space = &chip->work_space;
+drivers/char/tpm/tpm2-space.c:	struct tpm_space *space = &chip->work_space;
+drivers/char/tpm/tpm2-space.c:	attrs = chip->cc_attrs_tbl[i];
+drivers/char/tpm/tpm2-space.c:		dev_err(&chip->dev, "%s: unknown handle 0x%08X\n",
+drivers/char/tpm/tpm2-space.c:	dev_warn(&chip->dev, "%s: out of slots for 0x%08X\n", __func__,
+drivers/char/tpm/tpm2-space.c:	struct tpm_space *space = &chip->work_space;
+drivers/char/tpm/tpm2-space.c:	struct tpm_space *space = &chip->work_space;
+drivers/char/tpm/tpm2-space.c:	rc = tpm2_map_response_header(chip, chip->last_cc, buf, *bufsiz);
+drivers/char/tpm/tpm2-space.c:	rc = tpm2_map_response_body(chip, chip->last_cc, buf, *bufsiz);
+drivers/char/tpm/tpm2-space.c:	memcpy(&space->context_tbl, &chip->work_space.context_tbl,
+drivers/char/tpm/tpm2-space.c:	memcpy(&space->session_tbl, &chip->work_space.session_tbl,
+drivers/char/tpm/tpm2-space.c:	memcpy(space->context_buf, chip->work_space.context_buf, PAGE_SIZE);
+drivers/char/tpm/tpm2-space.c:	memcpy(space->session_buf, chip->work_space.session_buf, PAGE_SIZE);
+drivers/char/tpm/tpm2-space.c:	dev_err(&chip->dev, "%s: error %d\n", __func__, rc);
+drivers/char/tpm/tpm_atmel.c:	struct tpm_atmel_priv *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_atmel.c:			dev_err(&chip->dev, "error reading header\n");
+drivers/char/tpm/tpm_atmel.c:		dev_err(&chip->dev,
+drivers/char/tpm/tpm_atmel.c:				dev_err(&chip->dev, "error reading data\n");
+drivers/char/tpm/tpm_atmel.c:			dev_err(&chip->dev, "error reading data\n");
+drivers/char/tpm/tpm_atmel.c:		dev_err(&chip->dev, "data available is stuck\n");
+drivers/char/tpm/tpm_atmel.c:	struct tpm_atmel_priv *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_atmel.c:	dev_dbg(&chip->dev, "tpm_atml_send:\n");
+drivers/char/tpm/tpm_atmel.c:		dev_dbg(&chip->dev, "%d 0x%x(%d)\n",  i, buf[i], buf[i]);
+drivers/char/tpm/tpm_atmel.c:	struct tpm_atmel_priv *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_atmel.c:	struct tpm_atmel_priv *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_atmel.c:	struct tpm_atmel_priv *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_atmel.c:	dev_set_drvdata(&chip->dev, priv);
+drivers/char/tpm/tpm_crb.c:	struct device *dev = &chip->dev;
+drivers/char/tpm/tpm_crb.c:	struct device *dev = &chip->dev;
+drivers/char/tpm/tpm_crb.c:	struct crb_priv *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_crb.c:	return __crb_request_locality(&chip->dev, priv, loc);
+drivers/char/tpm/tpm_crb.c:	struct crb_priv *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_crb.c:	return __crb_relinquish_locality(&chip->dev, priv, loc);
+drivers/char/tpm/tpm_crb.c:	struct crb_priv *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_crb.c:	struct crb_priv *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_crb.c:	obj = acpi_evaluate_dsm(chip->acpi_dev_handle,
+drivers/char/tpm/tpm_crb.c:	struct crb_priv *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_crb.c:		dev_err(&chip->dev, "invalid command count value %zd %d\n",
+drivers/char/tpm/tpm_crb.c:		rc = tpm_crb_smc_start(&chip->dev, priv->smc_func_id);
+drivers/char/tpm/tpm_crb.c:	struct crb_priv *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_crb.c:		dev_err(&chip->dev, "ACPI Start failed\n");
+drivers/char/tpm/tpm_crb.c:	struct crb_priv *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_crb.c:	dev_set_drvdata(&chip->dev, priv);
+drivers/char/tpm/tpm_crb.c:	chip->acpi_dev_handle = device->handle;
+drivers/char/tpm/tpm_crb.c:	chip->flags = TPM_CHIP_FLAG_TPM2;
+drivers/char/tpm/tpm_ftpm_tee.c:	struct ftpm_tee_private *pvt_data = dev_get_drvdata(chip->dev.parent);
+drivers/char/tpm/tpm_ftpm_tee.c:		dev_err(&chip->dev,
+drivers/char/tpm/tpm_ftpm_tee.c:	struct ftpm_tee_private *pvt_data = dev_get_drvdata(chip->dev.parent);
+drivers/char/tpm/tpm_ftpm_tee.c:		dev_err(&chip->dev,
+drivers/char/tpm/tpm_ftpm_tee.c:		dev_err(&chip->dev, "%s: tee_shm_get_va failed for transmit\n",
+drivers/char/tpm/tpm_ftpm_tee.c:		dev_err(&chip->dev, "%s: SUBMIT_COMMAND invoke error: 0x%x\n",
+drivers/char/tpm/tpm_ftpm_tee.c:		dev_err(&chip->dev, "%s: tee_shm_get_va failed for receive\n",
+drivers/char/tpm/tpm_ftpm_tee.c:		dev_err(&chip->dev, "%s: tpm response header too small\n",
+drivers/char/tpm/tpm_ftpm_tee.c:		dev_err(&chip->dev,
+drivers/char/tpm/tpm_ftpm_tee.c:	pvt_data->chip->flags |= TPM_CHIP_FLAG_TPM2;
+drivers/char/tpm/tpm_ftpm_tee.c:	put_device(&pvt_data->chip->dev);
+drivers/char/tpm/tpm_ftpm_tee.c:	put_device(&pvt_data->chip->dev);
+drivers/char/tpm/tpm_i2c_atmel.c:	struct priv_data *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_i2c_atmel.c:	struct i2c_client *client = to_i2c_client(chip->dev.parent);
+drivers/char/tpm/tpm_i2c_atmel.c:	dev_dbg(&chip->dev,
+drivers/char/tpm/tpm_i2c_atmel.c:	struct priv_data *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_i2c_atmel.c:	struct i2c_client *client = to_i2c_client(chip->dev.parent);
+drivers/char/tpm/tpm_i2c_atmel.c:		dev_dbg(&chip->dev,
+drivers/char/tpm/tpm_i2c_atmel.c:	dev_dbg(&chip->dev,
+drivers/char/tpm/tpm_i2c_atmel.c:	dev_err(&chip->dev, "TPM operation cancellation was requested, but is not supported");
+drivers/char/tpm/tpm_i2c_atmel.c:	struct priv_data *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_i2c_atmel.c:	struct i2c_client *client = to_i2c_client(chip->dev.parent);
+drivers/char/tpm/tpm_i2c_atmel.c:	dev_dbg(&chip->dev,
+drivers/char/tpm/tpm_i2c_atmel.c:	chip->timeout_a = msecs_to_jiffies(TPM_I2C_SHORT_TIMEOUT);
+drivers/char/tpm/tpm_i2c_atmel.c:	chip->timeout_b = msecs_to_jiffies(TPM_I2C_LONG_TIMEOUT);
+drivers/char/tpm/tpm_i2c_atmel.c:	chip->timeout_c = msecs_to_jiffies(TPM_I2C_SHORT_TIMEOUT);
+drivers/char/tpm/tpm_i2c_atmel.c:	chip->timeout_d = msecs_to_jiffies(TPM_I2C_SHORT_TIMEOUT);
+drivers/char/tpm/tpm_i2c_atmel.c:	dev_set_drvdata(&chip->dev, priv);
+drivers/char/tpm/tpm_i2c_infineon.c:	stop = jiffies + chip->timeout_a;
+drivers/char/tpm/tpm_i2c_infineon.c:	stop = jiffies + chip->timeout_d;
+drivers/char/tpm/tpm_i2c_infineon.c:		dev_err(&chip->dev, "Unable to read header\n");
+drivers/char/tpm/tpm_i2c_infineon.c:		dev_err(&chip->dev, "Unable to read remainder of result\n");
+drivers/char/tpm/tpm_i2c_infineon.c:	wait_for_stat(chip, TPM_STS_VALID, chip->timeout_c, &status);
+drivers/char/tpm/tpm_i2c_infineon.c:		dev_err(&chip->dev, "Error left over data\n");
+drivers/char/tpm/tpm_i2c_infineon.c:		     chip->timeout_b, &status) < 0) {
+drivers/char/tpm/tpm_i2c_infineon.c:			      chip->timeout_c, &status);
+drivers/char/tpm/tpm_i2c_infineon.c:	wait_for_stat(chip, TPM_STS_VALID, chip->timeout_c, &status);
+drivers/char/tpm/tpm_i2c_infineon.c:	chip->timeout_a = msecs_to_jiffies(TIS_SHORT_TIMEOUT);
+drivers/char/tpm/tpm_i2c_infineon.c:	chip->timeout_b = msecs_to_jiffies(TIS_LONG_TIMEOUT);
+drivers/char/tpm/tpm_i2c_infineon.c:	chip->timeout_c = msecs_to_jiffies(TIS_SHORT_TIMEOUT);
+drivers/char/tpm/tpm_i2c_infineon.c:	chip->timeout_d = msecs_to_jiffies(TIS_SHORT_TIMEOUT);
+drivers/char/tpm/tpm_i2c_nuvoton.c:	struct i2c_client *client = to_i2c_client(chip->dev.parent);
+drivers/char/tpm/tpm_i2c_nuvoton.c:		dev_err(&chip->dev, "%s() error return %d\n", __func__,
+drivers/char/tpm/tpm_i2c_nuvoton.c:	struct i2c_client *client = to_i2c_client(chip->dev.parent);
+drivers/char/tpm/tpm_i2c_nuvoton.c:		dev_err(&chip->dev,
+drivers/char/tpm/tpm_i2c_nuvoton.c:	unsigned long stop = jiffies + chip->timeout_d;
+drivers/char/tpm/tpm_i2c_nuvoton.c:	if ((chip->flags & TPM_CHIP_FLAG_IRQ) && queue) {
+drivers/char/tpm/tpm_i2c_nuvoton.c:		struct priv_data *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_i2c_nuvoton.c:	dev_err(&chip->dev, "%s(%02x, %02x) -> timeout\n", __func__, mask,
+drivers/char/tpm/tpm_i2c_nuvoton.c:	struct priv_data *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_i2c_nuvoton.c:					       chip->timeout_c,
+drivers/char/tpm/tpm_i2c_nuvoton.c:			dev_err(&chip->dev,
+drivers/char/tpm/tpm_i2c_nuvoton.c:			dev_err(&chip->dev,
+drivers/char/tpm/tpm_i2c_nuvoton.c:		dev_dbg(&chip->dev, "%s(%d):", __func__, bytes2read);
+drivers/char/tpm/tpm_i2c_nuvoton.c:	struct priv_data *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_i2c_nuvoton.c:	struct device *dev = chip->dev.parent;
+drivers/char/tpm/tpm_i2c_nuvoton.c:			chip, chip->timeout_c, &priv->read_queue);
+drivers/char/tpm/tpm_i2c_nuvoton.c:			    TPM_STS_VALID, chip->timeout_c,
+drivers/char/tpm/tpm_i2c_nuvoton.c:	dev_dbg(&chip->dev, "%s() -> %d\n", __func__, size);
+drivers/char/tpm/tpm_i2c_nuvoton.c:	struct priv_data *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_i2c_nuvoton.c:	struct device *dev = chip->dev.parent;
+drivers/char/tpm/tpm_i2c_nuvoton.c:					      chip->timeout_b, NULL)) {
+drivers/char/tpm/tpm_i2c_nuvoton.c:						       chip->timeout_c,
+drivers/char/tpm/tpm_i2c_nuvoton.c:					       chip->timeout_c, NULL);
+drivers/char/tpm/tpm_i2c_nuvoton.c:	struct priv_data *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_i2c_nuvoton.c:			chip->flags |= TPM_CHIP_FLAG_TPM2;
+drivers/char/tpm/tpm_i2c_nuvoton.c:			chip->flags |= TPM_CHIP_FLAG_TPM2;
+drivers/char/tpm/tpm_i2c_nuvoton.c:	chip->timeout_a = msecs_to_jiffies(TPM_I2C_SHORT_TIMEOUT);
+drivers/char/tpm/tpm_i2c_nuvoton.c:	chip->timeout_b = msecs_to_jiffies(TPM_I2C_LONG_TIMEOUT);
+drivers/char/tpm/tpm_i2c_nuvoton.c:	chip->timeout_c = msecs_to_jiffies(TPM_I2C_SHORT_TIMEOUT);
+drivers/char/tpm/tpm_i2c_nuvoton.c:	chip->timeout_d = msecs_to_jiffies(TPM_I2C_SHORT_TIMEOUT);
+drivers/char/tpm/tpm_i2c_nuvoton.c:	dev_set_drvdata(&chip->dev, priv);
+drivers/char/tpm/tpm_i2c_nuvoton.c:				      dev_name(&chip->dev),
+drivers/char/tpm/tpm_i2c_nuvoton.c:			chip->flags |= TPM_CHIP_FLAG_IRQ;
+drivers/char/tpm/tpm_i2c_nuvoton.c:						       chip->timeout_b,
+drivers/char/tpm/tpm_ibmvtpm.c:	struct ibmvtpm_dev *ibmvtpm = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_ibmvtpm.c:	struct ibmvtpm_dev *ibmvtpm = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_ibmvtpm.c:	struct ibmvtpm_dev *ibmvtpm = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_ibmvtpm.c:		ibmvtpm = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_ibmvtpm.c:	struct ibmvtpm_dev *ibmvtpm = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_ibmvtpm.c:	struct ibmvtpm_dev *ibmvtpm = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_ibmvtpm.c:	dev_set_drvdata(&chip->dev, ibmvtpm);
+drivers/char/tpm/tpm_infineon.c:			dev_err(&chip->dev, "Timeout in wait(STAT_XFE)\n");
+drivers/char/tpm/tpm_infineon.c:			dev_err(&chip->dev, "Timeout in wait(STAT_RDA)\n");
+drivers/char/tpm/tpm_infineon.c:	dev_info(&chip->dev, "Granting WTX (%02d / %02d)\n",
+drivers/char/tpm/tpm_infineon.c:	dev_info(&chip->dev, "Aborting WTX\n");
+drivers/char/tpm/tpm_infineon.c:		dev_err(&chip->dev,
+drivers/char/tpm/tpm_infineon.c:			dev_err(&chip->dev, "Error handling on vendor layer!\n");
+drivers/char/tpm/tpm_infineon.c:		dev_info(&chip->dev, "WTX-package received\n");
+drivers/char/tpm/tpm_infineon.c:		dev_info(&chip->dev, "WTX-abort acknowledged\n");
+drivers/char/tpm/tpm_infineon.c:		dev_err(&chip->dev, "ERROR-package received:\n");
+drivers/char/tpm/tpm_infineon.c:			dev_err(&chip->dev,
+drivers/char/tpm/tpm_infineon.c:		dev_err(&chip->dev, "Timeout while clearing FIFO\n");
+drivers/char/tpm/tpm_nsc.c:	struct tpm_nsc_priv *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_nsc.c:	struct tpm_nsc_priv *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_nsc.c:	dev_info(&chip->dev, "wait for ready failed\n");
+drivers/char/tpm/tpm_nsc.c:	struct tpm_nsc_priv *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_nsc.c:		dev_err(&chip->dev, "F0 timeout\n");
+drivers/char/tpm/tpm_nsc.c:		dev_err(&chip->dev, "not in normal mode (0x%x)\n",
+drivers/char/tpm/tpm_nsc.c:			dev_err(&chip->dev,
+drivers/char/tpm/tpm_nsc.c:		dev_err(&chip->dev, "F0 not set\n");
+drivers/char/tpm/tpm_nsc.c:		dev_err(&chip->dev,
+drivers/char/tpm/tpm_nsc.c:	struct tpm_nsc_priv *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_nsc.c:		dev_err(&chip->dev, "IBF timeout\n");
+drivers/char/tpm/tpm_nsc.c:		dev_err(&chip->dev, "IBR timeout\n");
+drivers/char/tpm/tpm_nsc.c:			dev_err(&chip->dev,
+drivers/char/tpm/tpm_nsc.c:		dev_err(&chip->dev, "IBF timeout\n");
+drivers/char/tpm/tpm_nsc.c:	struct tpm_nsc_priv *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_nsc.c:	struct tpm_nsc_priv *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_nsc.c:	struct tpm_nsc_priv *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_nsc.c:	dev_set_drvdata(&chip->dev, priv);
+drivers/char/tpm/tpm_ppi.c:	return scnprintf(buf, PAGE_SIZE, "%s\n", chip->ppi_version);
+drivers/char/tpm/tpm_ppi.c:	if (strcmp(chip->ppi_version, "1.2") < 0)
+drivers/char/tpm/tpm_ppi.c:	obj = tpm_eval_dsm(chip->acpi_dev_handle, TPM_PPI_FN_GETREQ,
+drivers/char/tpm/tpm_ppi.c:	if (acpi_check_dsm(chip->acpi_dev_handle, &tpm_ppi_guid,
+drivers/char/tpm/tpm_ppi.c:	if (strcmp(chip->ppi_version, "1.3") == 0) {
+drivers/char/tpm/tpm_ppi.c:	} else if (strcmp(chip->ppi_version, "1.2") < 0) {
+drivers/char/tpm/tpm_ppi.c:	obj = tpm_eval_dsm(chip->acpi_dev_handle, func, ACPI_TYPE_INTEGER,
+drivers/char/tpm/tpm_ppi.c:	if (strcmp(chip->ppi_version, "1.2") < 0)
+drivers/char/tpm/tpm_ppi.c:	obj = tpm_eval_dsm(chip->acpi_dev_handle, TPM_PPI_FN_GETACT,
+drivers/char/tpm/tpm_ppi.c:	obj = tpm_eval_dsm(chip->acpi_dev_handle, TPM_PPI_FN_GETRSP,
+drivers/char/tpm/tpm_ppi.c:	return show_ppi_operations(chip->acpi_dev_handle, buf, 0,
+drivers/char/tpm/tpm_ppi.c:	return show_ppi_operations(chip->acpi_dev_handle, buf, PPI_VS_REQ_START,
+drivers/char/tpm/tpm_ppi.c:	if (!chip->acpi_dev_handle)
+drivers/char/tpm/tpm_ppi.c:	if (!acpi_check_dsm(chip->acpi_dev_handle, &tpm_ppi_guid,
+drivers/char/tpm/tpm_ppi.c:	obj = acpi_evaluate_dsm_typed(chip->acpi_dev_handle, &tpm_ppi_guid,
+drivers/char/tpm/tpm_ppi.c:		strlcpy(chip->ppi_version, obj->string.pointer,
+drivers/char/tpm/tpm_ppi.c:			sizeof(chip->ppi_version));
+drivers/char/tpm/tpm_ppi.c:	chip->groups[chip->groups_cnt++] = &ppi_attr_grp;
+drivers/char/tpm/tpm_tis_core.c:	u8 status = chip->ops->status(chip);
+drivers/char/tpm/tpm_tis_core.c:	if (check_cancel && chip->ops->req_canceled(chip, status)) {
+drivers/char/tpm/tpm_tis_core.c:	status = chip->ops->status(chip);
+drivers/char/tpm/tpm_tis_core.c:	if (chip->flags & TPM_CHIP_FLAG_IRQ) {
+drivers/char/tpm/tpm_tis_core.c:			status = chip->ops->status(chip);
+drivers/char/tpm/tpm_tis_core.c:	struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_tis_core.c:	unsigned long stop = jiffies + chip->timeout_a;
+drivers/char/tpm/tpm_tis_core.c:	struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_tis_core.c:	struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_tis_core.c:	struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_tis_core.c:	stop = jiffies + chip->timeout_a;
+drivers/char/tpm/tpm_tis_core.c:	if (chip->flags & TPM_CHIP_FLAG_IRQ) {
+drivers/char/tpm/tpm_tis_core.c:	struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_tis_core.c:	stop = jiffies + chip->timeout_a;
+drivers/char/tpm/tpm_tis_core.c:	if (chip->flags & TPM_CHIP_FLAG_IRQ) {
+drivers/char/tpm/tpm_tis_core.c:	struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_tis_core.c:	struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_tis_core.c:	struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_tis_core.c:	if (chip->flags & TPM_CHIP_FLAG_TPM2)
+drivers/char/tpm/tpm_tis_core.c:		stop = jiffies + chip->timeout_a;
+drivers/char/tpm/tpm_tis_core.c:		stop = jiffies + chip->timeout_d;
+drivers/char/tpm/tpm_tis_core.c:	struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_tis_core.c:				 chip->timeout_c,
+drivers/char/tpm/tpm_tis_core.c:			dev_err(&chip->dev, "Unable to read burstcount\n");
+drivers/char/tpm/tpm_tis_core.c:	struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_tis_core.c:		dev_err(&chip->dev, "Unable to read header\n");
+drivers/char/tpm/tpm_tis_core.c:		dev_err(&chip->dev, "Unable to read remainder of result\n");
+drivers/char/tpm/tpm_tis_core.c:	if (wait_for_tpm_stat(chip, TPM_STS_VALID, chip->timeout_c,
+drivers/char/tpm/tpm_tis_core.c:		dev_err(&chip->dev, "Error left over data\n");
+drivers/char/tpm/tpm_tis_core.c:	struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_tis_core.c:		    (chip, TPM_STS_COMMAND_READY, chip->timeout_b,
+drivers/char/tpm/tpm_tis_core.c:			dev_err(&chip->dev, "Unable to read burstcount\n");
+drivers/char/tpm/tpm_tis_core.c:		if (wait_for_tpm_stat(chip, TPM_STS_VALID, chip->timeout_c,
+drivers/char/tpm/tpm_tis_core.c:	if (wait_for_tpm_stat(chip, TPM_STS_VALID, chip->timeout_c,
+drivers/char/tpm/tpm_tis_core.c:	struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_tis_core.c:	devm_free_irq(chip->dev.parent, priv->irq, chip);
+drivers/char/tpm/tpm_tis_core.c:	chip->flags &= ~TPM_CHIP_FLAG_IRQ;
+drivers/char/tpm/tpm_tis_core.c:	struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_tis_core.c:	if (chip->flags & TPM_CHIP_FLAG_IRQ) {
+drivers/char/tpm/tpm_tis_core.c:	struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_tis_core.c:	if (!(chip->flags & TPM_CHIP_FLAG_IRQ) || priv->irq_tested)
+drivers/char/tpm/tpm_tis_core.c:	chip->flags &= ~TPM_CHIP_FLAG_IRQ;
+drivers/char/tpm/tpm_tis_core.c:	chip->flags |= TPM_CHIP_FLAG_IRQ;
+drivers/char/tpm/tpm_tis_core.c:	struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_tis_core.c:	chip->duration_adjusted = false;
+drivers/char/tpm/tpm_tis_core.c:	if (chip->ops->clk_enable != NULL)
+drivers/char/tpm/tpm_tis_core.c:		chip->ops->clk_enable(chip, true);
+drivers/char/tpm/tpm_tis_core.c:		dev_warn(&chip->dev, "%s: failed to read did_vid. %d\n",
+drivers/char/tpm/tpm_tis_core.c:			chip->duration_adjusted = true;
+drivers/char/tpm/tpm_tis_core.c:	if (chip->ops->clk_enable != NULL)
+drivers/char/tpm/tpm_tis_core.c:		chip->ops->clk_enable(chip, false);
+drivers/char/tpm/tpm_tis_core.c:	struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_tis_core.c:	chip->timeout_adjusted = false;
+drivers/char/tpm/tpm_tis_core.c:	if (chip->ops->clk_enable != NULL)
+drivers/char/tpm/tpm_tis_core.c:		chip->ops->clk_enable(chip, true);
+drivers/char/tpm/tpm_tis_core.c:		dev_warn(&chip->dev, "%s: failed to read did_vid: %d\n",
+drivers/char/tpm/tpm_tis_core.c:		chip->timeout_adjusted = true;
+drivers/char/tpm/tpm_tis_core.c:	if (chip->ops->clk_enable != NULL)
+drivers/char/tpm/tpm_tis_core.c:		chip->ops->clk_enable(chip, false);
+drivers/char/tpm/tpm_tis_core.c:	struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_tis_core.c:		dev_info(&chip->dev, "Detected an iTPM.\n");
+drivers/char/tpm/tpm_tis_core.c:	struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_tis_core.c:	struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_tis_core.c:	if (chip->flags & TPM_CHIP_FLAG_TPM2)
+drivers/char/tpm/tpm_tis_core.c:	struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_tis_core.c:	if (devm_request_irq(chip->dev.parent, irq, tis_int_handler, flags,
+drivers/char/tpm/tpm_tis_core.c:			     dev_name(&chip->dev), chip) != 0) {
+drivers/char/tpm/tpm_tis_core.c:		dev_info(&chip->dev, "Unable to request irq: %d for probe\n",
+drivers/char/tpm/tpm_tis_core.c:	if (!(chip->flags & TPM_CHIP_FLAG_IRQ)) {
+drivers/char/tpm/tpm_tis_core.c:	struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_tis_core.c:	struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_tis_core.c: * path, since the chip->ops is set to NULL in tpm_chip_unregister().
+drivers/char/tpm/tpm_tis_core.c:	struct tpm_tis_data *data = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_tis_core.c:	chip->acpi_dev_handle = acpi_dev_handle;
+drivers/char/tpm/tpm_tis_core.c:	chip->hwrng.quality = priv->rng_quality;
+drivers/char/tpm/tpm_tis_core.c:	chip->timeout_a = msecs_to_jiffies(TIS_TIMEOUT_A_MAX);
+drivers/char/tpm/tpm_tis_core.c:	chip->timeout_b = msecs_to_jiffies(TIS_TIMEOUT_B_MAX);
+drivers/char/tpm/tpm_tis_core.c:	chip->timeout_c = msecs_to_jiffies(TIS_TIMEOUT_C_MAX);
+drivers/char/tpm/tpm_tis_core.c:	chip->timeout_d = msecs_to_jiffies(TIS_TIMEOUT_D_MAX);
+drivers/char/tpm/tpm_tis_core.c:	dev_set_drvdata(&chip->dev, priv);
+drivers/char/tpm/tpm_tis_core.c:	if (chip->ops->clk_enable != NULL)
+drivers/char/tpm/tpm_tis_core.c:		chip->ops->clk_enable(chip, true);
+drivers/char/tpm/tpm_tis_core.c:		 (chip->flags & TPM_CHIP_FLAG_TPM2) ? "2.0" : "1.2",
+drivers/char/tpm/tpm_tis_core.c:		chip->flags |= TPM_CHIP_FLAG_IRQ;
+drivers/char/tpm/tpm_tis_core.c:			if (!(chip->flags & TPM_CHIP_FLAG_IRQ))
+drivers/char/tpm/tpm_tis_core.c:				dev_err(&chip->dev, FW_BUG
+drivers/char/tpm/tpm_tis_core.c:	if ((chip->ops != NULL) && (chip->ops->clk_enable != NULL))
+drivers/char/tpm/tpm_tis_core.c:		chip->ops->clk_enable(chip, false);
+drivers/char/tpm/tpm_tis_core.c:	struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_tis_core.c:	if (chip->ops->clk_enable != NULL)
+drivers/char/tpm/tpm_tis_core.c:		chip->ops->clk_enable(chip, true);
+drivers/char/tpm/tpm_tis_core.c:	if (chip->ops->clk_enable != NULL)
+drivers/char/tpm/tpm_tis_core.c:		chip->ops->clk_enable(chip, false);
+drivers/char/tpm/tpm_tis_core.c:	if (chip->flags & TPM_CHIP_FLAG_IRQ)
+drivers/char/tpm/tpm_tis_core.c:	if (!(chip->flags & TPM_CHIP_FLAG_TPM2))
+drivers/char/tpm/tpm_tis_spi_cr50.c:	chip->flags |= TPM_CHIP_FLAG_FIRMWARE_POWER_MANAGED;
+drivers/char/tpm/tpm_tis_spi_cr50.c:	struct tpm_tis_data *data = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_vtpm_proxy.c:	struct proxy_dev *proxy_dev = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_vtpm_proxy.c:		dev_err(&chip->dev,
+drivers/char/tpm/tpm_vtpm_proxy.c:	if (chip->flags & TPM_CHIP_FLAG_TPM2) {
+drivers/char/tpm/tpm_vtpm_proxy.c:	struct proxy_dev *proxy_dev = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_vtpm_proxy.c:		dev_err(&chip->dev,
+drivers/char/tpm/tpm_vtpm_proxy.c:	struct proxy_dev *proxy_dev = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_vtpm_proxy.c:	struct proxy_dev *proxy_dev = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_vtpm_proxy.c:	struct proxy_dev *proxy_dev = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/tpm_vtpm_proxy.c:	if (chip->flags & TPM_CHIP_FLAG_TPM2)
+drivers/char/tpm/tpm_vtpm_proxy.c:	dev_set_drvdata(&chip->dev, proxy_dev);
+drivers/char/tpm/tpm_vtpm_proxy.c:	put_device(&proxy_dev->chip->dev); /* frees chip */
+drivers/char/tpm/tpm_vtpm_proxy.c:		proxy_dev->chip->flags |= TPM_CHIP_FLAG_TPM2;
+drivers/char/tpm/tpm_vtpm_proxy.c:	vtpm_new_dev->major = MAJOR(proxy_dev->chip->dev.devt);
+drivers/char/tpm/tpm_vtpm_proxy.c:	vtpm_new_dev->minor = MINOR(proxy_dev->chip->dev.devt);
+drivers/char/tpm/tpm_vtpm_proxy.c:	vtpm_new_dev->tpm_num = proxy_dev->chip->dev_num;
+drivers/char/tpm/xen-tpmfront.c:	u8 status = chip->ops->status(chip);
+drivers/char/tpm/xen-tpmfront.c:	if (check_cancel && chip->ops->req_canceled(chip, status)) {
+drivers/char/tpm/xen-tpmfront.c:	status = chip->ops->status(chip);
+drivers/char/tpm/xen-tpmfront.c:	if (chip->flags & TPM_CHIP_FLAG_IRQ) {
+drivers/char/tpm/xen-tpmfront.c:			status = chip->ops->status(chip);
+drivers/char/tpm/xen-tpmfront.c:	struct tpm_private *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/xen-tpmfront.c:	struct tpm_private *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/xen-tpmfront.c:	struct tpm_private *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/xen-tpmfront.c:	if (wait_for_tpm_stat(chip, VTPM_STATUS_IDLE, chip->timeout_c,
+drivers/char/tpm/xen-tpmfront.c:	struct tpm_private *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/xen-tpmfront.c:	if (wait_for_tpm_stat(chip, VTPM_STATUS_RESULT, chip->timeout_c,
+drivers/char/tpm/xen-tpmfront.c:	dev_set_drvdata(&chip->dev, priv);
+drivers/char/tpm/xen-tpmfront.c:	struct tpm_private *priv = dev_get_drvdata(&chip->dev);
+drivers/char/tpm/xen-tpmfront.c:	dev_set_drvdata(&chip->dev, NULL);
+drivers/clk/clk-cdce925.c:		regmap_update_bits(data->chip->regmap,
+drivers/clk/clk-cdce925.c:			regmap_write(data->chip->regmap,
+drivers/clk/clk-cdce925.c:		regmap_update_bits(data->chip->regmap,
+drivers/clk/clk-cdce925.c:	regmap_update_bits(data->chip->regmap,
+drivers/clk/clk-cdce925.c:		regmap_update_bits(data->chip->regmap,
+drivers/clk/clk-cdce925.c:		regmap_write(data->chip->regmap, 0x03, pdiv & 0xFF);
+drivers/clk/clk-cdce925.c:		regmap_update_bits(data->chip->regmap, 0x16, 0x7F, pdiv);
+drivers/clk/clk-cdce925.c:		regmap_update_bits(data->chip->regmap, 0x17, 0x7F, pdiv);
+drivers/clk/clk-cdce925.c:		regmap_update_bits(data->chip->regmap, 0x26, 0x7F, pdiv);
+drivers/clk/clk-cdce925.c:		regmap_update_bits(data->chip->regmap, 0x27, 0x7F, pdiv);
+drivers/clk/clk-cdce925.c:		regmap_update_bits(data->chip->regmap, 0x36, 0x7F, pdiv);
+drivers/clk/clk-cdce925.c:		regmap_update_bits(data->chip->regmap, 0x37, 0x7F, pdiv);
+drivers/clk/clk-cdce925.c:		regmap_update_bits(data->chip->regmap, 0x46, 0x7F, pdiv);
+drivers/clk/clk-cdce925.c:		regmap_update_bits(data->chip->regmap, 0x47, 0x7F, pdiv);
+drivers/clk/clk-cdce925.c:		regmap_update_bits(data->chip->regmap,
+drivers/clk/clk-cdce925.c:		regmap_update_bits(data->chip->regmap, 0x14, 0x03, 0x03);
+drivers/clk/clk-cdce925.c:		regmap_update_bits(data->chip->regmap, 0x24, 0x03, 0x03);
+drivers/clk/clk-cdce925.c:		regmap_update_bits(data->chip->regmap, 0x34, 0x03, 0x03);
+drivers/clk/clk-cdce925.c:		regmap_update_bits(data->chip->regmap, 0x44, 0x03, 0x03);
+drivers/clk/davinci/da8xx-cfgchip.c:		.name		= "da8xx-cfgchip-clk",
+drivers/cpufreq/powernv-cpufreq.c:	return sprintf(buf, "%u\n", chip->member);			\
+drivers/cpufreq/powernv-cpufreq.c:		if (chip->throttled)
+drivers/cpufreq/powernv-cpufreq.c:		chip->throttled = true;
+drivers/cpufreq/powernv-cpufreq.c:				     cpu, chip->id, pmsr_pmax,
+drivers/cpufreq/powernv-cpufreq.c:			chip->throttle_sub_turbo++;
+drivers/cpufreq/powernv-cpufreq.c:			chip->throttle_turbo++;
+drivers/cpufreq/powernv-cpufreq.c:		trace_powernv_throttle(chip->id,
+drivers/cpufreq/powernv-cpufreq.c:				      throttle_reason[chip->throttle_reason],
+drivers/cpufreq/powernv-cpufreq.c:	} else if (chip->throttled) {
+drivers/cpufreq/powernv-cpufreq.c:		chip->throttled = false;
+drivers/cpufreq/powernv-cpufreq.c:		trace_powernv_throttle(chip->id,
+drivers/cpufreq/powernv-cpufreq.c:				      throttle_reason[chip->throttle_reason],
+drivers/cpufreq/powernv-cpufreq.c:	cpumask_and(&mask, &chip->mask, cpu_online_mask);
+drivers/cpufreq/powernv-cpufreq.c:	if (!chip->restore)
+drivers/cpufreq/powernv-cpufreq.c:	chip->restore = false;
+drivers/crypto/nx/nx-842-powernv.c:		pr_err("ibm,chip-id missing\n");
+drivers/crypto/nx/nx-842-powernv.c:		pr_err("ibm,chip-id missing\n");
+drivers/devfreq/event/Makefile:obj-$(CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI) += rockchip-dfi.o
+drivers/devfreq/event/rockchip-dfi.c:		.name	= "rockchip-dfi",
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	iowrite32(val, chip->regs + reg);
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	return ioread32(chip->regs + reg);
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	for (i = 0; i < chip->dw->hdata->nr_channels; i++) {
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:		axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL);
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:		axi_chan_disable(&chip->dw->chan[i]);
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	u32 max_width = chan->chip->dw->hdata->m_data_width;
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	struct dw_axi_dma *dw = chan->chip->dw;
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	struct dw_axi_dma *dw = chan->chip->dw;
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	u32 priority = chan->chip->dw->hdata->priority[chan->id];
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	pm_runtime_get(chan->chip->dev);
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	pm_runtime_put(chan->chip->dev);
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	if (desc->chan->chip->dw->hdata->nr_masters > 1)
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	max_block_ts = chan->chip->dw->hdata->block_size[chan->id];
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:		if (chan->chip->dw->hdata->restrict_axi_burst_len) {
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:			u32 burst_len = chan->chip->dw->hdata->axi_rw_burst_len;
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	struct dw_axi_dma *dw = chip->dw;
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:		dev_vdbg(chip->dev, "%s %u IRQ status: 0x%08x\n",
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	clk_disable_unprepare(chip->core_clk);
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	clk_disable_unprepare(chip->cfgr_clk);
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	ret = clk_prepare_enable(chip->cfgr_clk);
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	ret = clk_prepare_enable(chip->core_clk);
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	struct device *dev = chip->dev;
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	chip->dw->hdata->nr_channels = tmp;
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	chip->dw->hdata->nr_masters = tmp;
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	chip->dw->hdata->m_data_width = tmp;
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:					     chip->dw->hdata->nr_channels);
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	for (tmp = 0; tmp < chip->dw->hdata->nr_channels; tmp++) {
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:		chip->dw->hdata->block_size[tmp] = carr[tmp];
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:					     chip->dw->hdata->nr_channels);
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	for (tmp = 0; tmp < chip->dw->hdata->nr_channels; tmp++) {
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:		if (carr[tmp] >= chip->dw->hdata->nr_channels)
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:		chip->dw->hdata->priority[tmp] = carr[tmp];
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:		chip->dw->hdata->restrict_axi_burst_len = true;
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:		chip->dw->hdata->axi_rw_burst_len = tmp - 1;
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	chip->dw = dw;
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	chip->dev = &pdev->dev;
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	chip->dw->hdata = hdata;
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	chip->irq = platform_get_irq(pdev, 0);
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	if (chip->irq < 0)
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:		return chip->irq;
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	chip->regs = devm_ioremap_resource(chip->dev, mem);
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	if (IS_ERR(chip->regs))
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:		return PTR_ERR(chip->regs);
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	chip->core_clk = devm_clk_get(chip->dev, "core-clk");
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	if (IS_ERR(chip->core_clk))
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:		return PTR_ERR(chip->core_clk);
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	chip->cfgr_clk = devm_clk_get(chip->dev, "cfgr-clk");
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	if (IS_ERR(chip->cfgr_clk))
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:		return PTR_ERR(chip->cfgr_clk);
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	dw->chan = devm_kcalloc(chip->dev, hdata->nr_channels,
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	ret = devm_request_irq(chip->dev, chip->irq, dw_axi_dma_interrupt,
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	dw->desc_pool = dmam_pool_create(KBUILD_MODNAME, chip->dev,
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:		dev_err(chip->dev, "No memory for descriptors dma pool\n");
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:		chan->chan_regs = chip->regs + COMMON_REG_LEN + i * CHAN_REG_LEN;
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	dw->dma.dev = chip->dev;
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	pm_runtime_enable(chip->dev);
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	pm_runtime_get_noresume(chip->dev);
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	pm_runtime_put(chip->dev);
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	dev_info(chip->dev, "DesignWare AXI DMA Controller, %d channels\n",
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	pm_runtime_disable(chip->dev);
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	struct dw_axi_dma *dw = chip->dw;
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	clk_prepare_enable(chip->cfgr_clk);
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	clk_prepare_enable(chip->core_clk);
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:		axi_chan_disable(&chip->dw->chan[i]);
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:		axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL);
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	pm_runtime_disable(chip->dev);
+drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:	devm_free_irq(chip->dev, chip->irq, chip);
+drivers/dma/dw-edma/dw-edma-core.c:	struct dw_edma *dw = chan->chip->dw;
+drivers/dma/dw-edma/dw-edma-core.c:	pm_runtime_get(chan->chip->dev);
+drivers/dma/dw-edma/dw-edma-core.c:	pm_runtime_put(chan->chip->dev);
+drivers/dma/dw-edma/dw-edma-core.c:	struct device *dev = chip->dev;
+drivers/dma/dw-edma/dw-edma-core.c:	struct dw_edma *dw = chip->dw;
+drivers/dma/dw-edma/dw-edma-core.c:	dma->dev = chip->dev;
+drivers/dma/dw-edma/dw-edma-core.c:	struct device *dev = chip->dev;
+drivers/dma/dw-edma/dw-edma-core.c:	struct dw_edma *dw = chip->dw;
+drivers/dma/dw-edma/dw-edma-core.c:	struct device *dev = chip->dev;
+drivers/dma/dw-edma/dw-edma-core.c:	struct dw_edma *dw = chip->dw;
+drivers/dma/dw-edma/dw-edma-core.c:	snprintf(dw->name, sizeof(dw->name), "dw-edma-core:%d", chip->id);
+drivers/dma/dw-edma/dw-edma-core.c:	struct device *dev = chip->dev;
+drivers/dma/dw-edma/dw-edma-core.c:	struct dw_edma *dw = chip->dw;
+drivers/dma/dw-edma/dw-edma-pcie.c:	chip->dw = dw;
+drivers/dma/dw-edma/dw-edma-pcie.c:	chip->dev = dev;
+drivers/dma/dw-edma/dw-edma-pcie.c:	chip->id = pdev->devfn;
+drivers/dma/dw-edma/dw-edma-pcie.c:	chip->irq = pdev->irq;
+drivers/dma/dw-edma/dw-edma-v0-core.c:	struct dw_edma *dw = chan->chip->dw;
+drivers/dma/dw-edma/dw-edma-v0-core.c:	struct dw_edma *dw = chan->chip->dw;
+drivers/dma/dw-edma/dw-edma-v0-core.c:	struct dw_edma *dw = chan->chip->dw;
+drivers/dma/dw-edma/dw-edma-v0-core.c:	struct dw_edma *dw = chan->chip->dw;
+drivers/dma/dw-edma/dw-edma-v0-core.c:	struct dw_edma *dw = chan->chip->dw;
+drivers/dma/dw-edma/dw-edma-v0-debugfs.c:	dw = chip->dw;
+drivers/dma/dw/core.c:	struct dw_dma *dw = chip->dw;
+drivers/dma/dw/core.c:	dw->pdata = devm_kzalloc(chip->dev, sizeof(*dw->pdata), GFP_KERNEL);
+drivers/dma/dw/core.c:	dw->regs = chip->regs;
+drivers/dma/dw/core.c:	pm_runtime_get_sync(chip->dev);
+drivers/dma/dw/core.c:	if (!chip->pdata) {
+drivers/dma/dw/core.c:		dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params);
+drivers/dma/dw/core.c:	} else if (chip->pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) {
+drivers/dma/dw/core.c:		memcpy(dw->pdata, chip->pdata, sizeof(*dw->pdata));
+drivers/dma/dw/core.c:	dw->chan = devm_kcalloc(chip->dev, pdata->nr_channels, sizeof(*dw->chan),
+drivers/dma/dw/core.c:	dw->set_device_name(dw, chip->id);
+drivers/dma/dw/core.c:	dw->desc_pool = dmam_pool_create(dw->name, chip->dev,
+drivers/dma/dw/core.c:		dev_err(chip->dev, "No memory for descriptors dma pool\n");
+drivers/dma/dw/core.c:	err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED,
+drivers/dma/dw/core.c:			dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i,
+drivers/dma/dw/core.c:	dw->dma.dev = chip->dev;
+drivers/dma/dw/core.c:	dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n",
+drivers/dma/dw/core.c:	pm_runtime_put_sync_suspend(chip->dev);
+drivers/dma/dw/core.c:	free_irq(chip->irq, dw);
+drivers/dma/dw/core.c:	pm_runtime_put_sync_suspend(chip->dev);
+drivers/dma/dw/core.c:	struct dw_dma		*dw = chip->dw;
+drivers/dma/dw/core.c:	pm_runtime_get_sync(chip->dev);
+drivers/dma/dw/core.c:	free_irq(chip->irq, dw);
+drivers/dma/dw/core.c:	pm_runtime_put_sync_suspend(chip->dev);
+drivers/dma/dw/core.c:	struct dw_dma *dw = chip->dw;
+drivers/dma/dw/core.c:	struct dw_dma *dw = chip->dw;
+drivers/dma/dw/dw.c:	dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL);
+drivers/dma/dw/dw.c:	chip->dw = dw;
+drivers/dma/dw/idma32.c:	dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL);
+drivers/dma/dw/idma32.c:	chip->dw = dw;
+drivers/dma/dw/pci.c:	chip->dev = &pdev->dev;
+drivers/dma/dw/pci.c:	chip->id = pdev->devfn;
+drivers/dma/dw/pci.c:	chip->regs = pcim_iomap_table(pdev)[0];
+drivers/dma/dw/pci.c:	chip->irq = pdev->irq;
+drivers/dma/dw/pci.c:	chip->pdata = data->pdata;
+drivers/dma/dw/platform.c:	chip->irq = platform_get_irq(pdev, 0);
+drivers/dma/dw/platform.c:	if (chip->irq < 0)
+drivers/dma/dw/platform.c:		return chip->irq;
+drivers/dma/dw/platform.c:	chip->regs = devm_platform_ioremap_resource(pdev, 0);
+drivers/dma/dw/platform.c:	if (IS_ERR(chip->regs))
+drivers/dma/dw/platform.c:		return PTR_ERR(chip->regs);
+drivers/dma/dw/platform.c:	chip->dev = dev;
+drivers/dma/dw/platform.c:	chip->id = pdev->id;
+drivers/dma/dw/platform.c:	chip->pdata = data->pdata;
+drivers/dma/dw/platform.c:	chip->clk = devm_clk_get_optional(chip->dev, "hclk");
+drivers/dma/dw/platform.c:	if (IS_ERR(chip->clk))
+drivers/dma/dw/platform.c:		return PTR_ERR(chip->clk);
+drivers/dma/dw/platform.c:	err = clk_prepare_enable(chip->clk);
+drivers/dma/dw/platform.c:	dw_dma_of_controller_register(chip->dw);
+drivers/dma/dw/platform.c:	dw_dma_acpi_controller_register(chip->dw);
+drivers/dma/dw/platform.c:	clk_disable_unprepare(chip->clk);
+drivers/dma/dw/platform.c:	dw_dma_acpi_controller_free(chip->dw);
+drivers/dma/dw/platform.c:	dw_dma_of_controller_free(chip->dw);
+drivers/dma/dw/platform.c:		dev_warn(chip->dev, "can't remove device properly: %d\n", ret);
+drivers/dma/dw/platform.c:	clk_disable_unprepare(chip->clk);
+drivers/dma/dw/platform.c:	pm_runtime_get_sync(chip->dev);
+drivers/dma/dw/platform.c:	pm_runtime_put_sync_suspend(chip->dev);
+drivers/dma/dw/platform.c:	clk_disable_unprepare(chip->clk);
+drivers/dma/dw/platform.c:	clk_disable_unprepare(chip->clk);
+drivers/dma/dw/platform.c:	ret = clk_prepare_enable(chip->clk);
+drivers/dma/hsu/hsu.c:	if (nr >= chip->hsu->nr_channels)
+drivers/dma/hsu/hsu.c:	hsuc = &chip->hsu->chan[nr];
+drivers/dma/hsu/hsu.c:	if (nr >= chip->hsu->nr_channels)
+drivers/dma/hsu/hsu.c:	hsuc = &chip->hsu->chan[nr];
+drivers/dma/hsu/hsu.c:	void __iomem *addr = chip->regs + chip->offset;
+drivers/dma/hsu/hsu.c:	hsu = devm_kzalloc(chip->dev, sizeof(*hsu), GFP_KERNEL);
+drivers/dma/hsu/hsu.c:	chip->hsu = hsu;
+drivers/dma/hsu/hsu.c:	hsu->nr_channels = (chip->length - chip->offset) / HSU_DMA_CHAN_LENGTH;
+drivers/dma/hsu/hsu.c:	hsu->chan = devm_kcalloc(chip->dev, hsu->nr_channels,
+drivers/dma/hsu/hsu.c:	hsu->dma.dev = chip->dev;
+drivers/dma/hsu/hsu.c:	dev_info(chip->dev, "Found HSU DMA, %d channels\n", hsu->nr_channels);
+drivers/dma/hsu/hsu.c:	struct hsu_dma *hsu = chip->hsu;
+drivers/dma/hsu/pci.c:	struct pci_dev *pdev = to_pci_dev(chip->dev);
+drivers/dma/hsu/pci.c:	dmaisr = readl(chip->regs + HSU_PCI_DMAISR);
+drivers/dma/hsu/pci.c:	for (i = 0; i < chip->hsu->nr_channels; i++) {
+drivers/dma/hsu/pci.c:	chip->dev = &pdev->dev;
+drivers/dma/hsu/pci.c:	chip->regs = pcim_iomap_table(pdev)[0];
+drivers/dma/hsu/pci.c:	chip->length = pci_resource_len(pdev, 0);
+drivers/dma/hsu/pci.c:	chip->offset = HSU_PCI_CHAN_OFFSET;
+drivers/dma/hsu/pci.c:	chip->irq = pci_irq_vector(pdev, 0);
+drivers/dma/hsu/pci.c:	ret = request_irq(chip->irq, hsu_pci_irq, 0, "hsu_dma_pci", chip);
+drivers/dma/hsu/pci.c:	free_irq(chip->irq, chip);
+drivers/dma/idma64.c:	idma64 = devm_kzalloc(chip->dev, sizeof(*idma64), GFP_KERNEL);
+drivers/dma/idma64.c:	idma64->regs = chip->regs;
+drivers/dma/idma64.c:	chip->idma64 = idma64;
+drivers/dma/idma64.c:	idma64->chan = devm_kcalloc(chip->dev, nr_chan, sizeof(*idma64->chan),
+drivers/dma/idma64.c:	ret = devm_request_irq(chip->dev, chip->irq, idma64_irq, IRQF_SHARED,
+drivers/dma/idma64.c:			       dev_name(chip->dev), idma64);
+drivers/dma/idma64.c:	idma64->dma.dev = chip->sysdev;
+drivers/dma/idma64.c:	dev_info(chip->dev, "Found Intel integrated DMA 64-bit\n");
+drivers/dma/idma64.c:	struct idma64 *idma64 = chip->idma64;
+drivers/dma/idma64.c:	devm_free_irq(chip->dev, chip->irq, idma64);
+drivers/dma/idma64.c:	chip->irq = platform_get_irq(pdev, 0);
+drivers/dma/idma64.c:	if (chip->irq < 0)
+drivers/dma/idma64.c:		return chip->irq;
+drivers/dma/idma64.c:	chip->regs = devm_ioremap_resource(dev, mem);
+drivers/dma/idma64.c:	if (IS_ERR(chip->regs))
+drivers/dma/idma64.c:		return PTR_ERR(chip->regs);
+drivers/dma/idma64.c:	chip->dev = dev;
+drivers/dma/idma64.c:	chip->sysdev = sysdev;
+drivers/dma/idma64.c:	idma64_off(chip->idma64);
+drivers/dma/idma64.c:	idma64_on(chip->idma64);
+drivers/edac/amd76x_edac.c:					 * 31:23 chip-select base
+drivers/edac/amd76x_edac.c:					 * 15:7  chip-select mask
+drivers/edac/amd76x_edac.c:					 *  0    chip-select enable
+drivers/edac/i5100_edac.c: * can not reflect this configuration so instead the chip-select
+drivers/firmware/meson/meson_sm.c:	const struct meson_sm_cmd *cmd = chip->cmd;
+drivers/firmware/meson/meson_sm.c:	if (!fw->chip->cmd_shmem_out_base)
+drivers/firmware/meson/meson_sm.c:	if (bsize > fw->chip->shmem_size)
+drivers/firmware/meson/meson_sm.c:	if (size > fw->chip->shmem_size)
+drivers/firmware/meson/meson_sm.c:	if (!fw->chip->cmd_shmem_in_base)
+drivers/firmware/meson/meson_sm.c:	if (chip->cmd_shmem_in_base) {
+drivers/firmware/meson/meson_sm.c:		fw->sm_shmem_in_base = meson_sm_map_shmem(chip->cmd_shmem_in_base,
+drivers/firmware/meson/meson_sm.c:							  chip->shmem_size);
+drivers/firmware/meson/meson_sm.c:	if (chip->cmd_shmem_out_base) {
+drivers/firmware/meson/meson_sm.c:		fw->sm_shmem_out_base = meson_sm_map_shmem(chip->cmd_shmem_out_base,
+drivers/firmware/meson/meson_sm.c:							   chip->shmem_size);
+drivers/firmware/tegra/bpmp-tegra210.c:	if (irq_data->chip->irq_retrigger)
+drivers/firmware/tegra/bpmp-tegra210.c:		return irq_data->chip->irq_retrigger(irq_data);
+drivers/fpga/ice40-spi.c:	/* Abort if the chip-select failed */
+drivers/fsi/fsi-core.c:		if (!of_property_read_u32(slave->dev.of_node, "chip-id", &prop))
+drivers/gpio/gpio-104-dio-48e.c:	bitmap_zero(bits, chip->ngpio);
+drivers/gpio/gpio-104-dio-48e.c:		generic_handle_irq(irq_find_mapping(chip->irq.domain,
+drivers/gpio/gpio-104-idi-48.c:	bitmap_zero(bits, chip->ngpio);
+drivers/gpio/gpio-104-idi-48.c:			generic_handle_irq(irq_find_mapping(chip->irq.domain,
+drivers/gpio/gpio-104-idio-16.c:	chip->set(chip, offset, value);
+drivers/gpio/gpio-104-idio-16.c:	for_each_set_bit(gpio, &idio16gpio->irq_mask, chip->ngpio)
+drivers/gpio/gpio-104-idio-16.c:		generic_handle_irq(irq_find_mapping(chip->irq.domain, gpio));
+drivers/gpio/gpio-74x164.c:	return spi_write(to_spi_device(chip->gpio_chip.parent), chip->buffer,
+drivers/gpio/gpio-74x164.c:			 chip->registers);
+drivers/gpio/gpio-74x164.c:	u8 bank = chip->registers - 1 - offset / 8;
+drivers/gpio/gpio-74x164.c:	mutex_lock(&chip->lock);
+drivers/gpio/gpio-74x164.c:	ret = (chip->buffer[bank] >> pin) & 0x1;
+drivers/gpio/gpio-74x164.c:	mutex_unlock(&chip->lock);
+drivers/gpio/gpio-74x164.c:	u8 bank = chip->registers - 1 - offset / 8;
+drivers/gpio/gpio-74x164.c:	mutex_lock(&chip->lock);
+drivers/gpio/gpio-74x164.c:		chip->buffer[bank] |= (1 << pin);
+drivers/gpio/gpio-74x164.c:		chip->buffer[bank] &= ~(1 << pin);
+drivers/gpio/gpio-74x164.c:	mutex_unlock(&chip->lock);
+drivers/gpio/gpio-74x164.c:	mutex_lock(&chip->lock);
+drivers/gpio/gpio-74x164.c:	for_each_set_clump8(offset, bankmask, mask, chip->registers * 8) {
+drivers/gpio/gpio-74x164.c:		bank = chip->registers - 1 - offset / 8;
+drivers/gpio/gpio-74x164.c:		chip->buffer[bank] &= ~bankmask;
+drivers/gpio/gpio-74x164.c:		chip->buffer[bank] |= bitmask;
+drivers/gpio/gpio-74x164.c:	mutex_unlock(&chip->lock);
+drivers/gpio/gpio-74x164.c:	chip->gpiod_oe = devm_gpiod_get_optional(&spi->dev, "enable",
+drivers/gpio/gpio-74x164.c:	if (IS_ERR(chip->gpiod_oe))
+drivers/gpio/gpio-74x164.c:		return PTR_ERR(chip->gpiod_oe);
+drivers/gpio/gpio-74x164.c:	gpiod_set_value_cansleep(chip->gpiod_oe, 1);
+drivers/gpio/gpio-74x164.c:	chip->gpio_chip.label = spi->modalias;
+drivers/gpio/gpio-74x164.c:	chip->gpio_chip.direction_output = gen_74x164_direction_output;
+drivers/gpio/gpio-74x164.c:	chip->gpio_chip.get = gen_74x164_get_value;
+drivers/gpio/gpio-74x164.c:	chip->gpio_chip.set = gen_74x164_set_value;
+drivers/gpio/gpio-74x164.c:	chip->gpio_chip.set_multiple = gen_74x164_set_multiple;
+drivers/gpio/gpio-74x164.c:	chip->gpio_chip.base = -1;
+drivers/gpio/gpio-74x164.c:	chip->registers = nregs;
+drivers/gpio/gpio-74x164.c:	chip->gpio_chip.ngpio = GEN_74X164_NUMBER_GPIOS * chip->registers;
+drivers/gpio/gpio-74x164.c:	chip->gpio_chip.can_sleep = true;
+drivers/gpio/gpio-74x164.c:	chip->gpio_chip.parent = &spi->dev;
+drivers/gpio/gpio-74x164.c:	chip->gpio_chip.owner = THIS_MODULE;
+drivers/gpio/gpio-74x164.c:	mutex_init(&chip->lock);
+drivers/gpio/gpio-74x164.c:	ret = gpiochip_add_data(&chip->gpio_chip, chip);
+drivers/gpio/gpio-74x164.c:	mutex_destroy(&chip->lock);
+drivers/gpio/gpio-74x164.c:	gpiod_set_value_cansleep(chip->gpiod_oe, 0);
+drivers/gpio/gpio-74x164.c:	gpiochip_remove(&chip->gpio_chip);
+drivers/gpio/gpio-74x164.c:	mutex_destroy(&chip->lock);
+drivers/gpio/gpio-adnp.c:	chip->direction_input = adnp_gpio_direction_input;
+drivers/gpio/gpio-adnp.c:	chip->direction_output = adnp_gpio_direction_output;
+drivers/gpio/gpio-adnp.c:	chip->get = adnp_gpio_get;
+drivers/gpio/gpio-adnp.c:	chip->set = adnp_gpio_set;
+drivers/gpio/gpio-adnp.c:	chip->can_sleep = true;
+drivers/gpio/gpio-adnp.c:		chip->dbg_show = adnp_gpio_dbg_show;
+drivers/gpio/gpio-adnp.c:	chip->base = -1;
+drivers/gpio/gpio-adnp.c:	chip->ngpio = num_gpios;
+drivers/gpio/gpio-adnp.c:	chip->label = adnp->client->name;
+drivers/gpio/gpio-adnp.c:	chip->parent = &adnp->client->dev;
+drivers/gpio/gpio-adnp.c:	chip->of_node = chip->parent->of_node;
+drivers/gpio/gpio-adnp.c:	chip->owner = THIS_MODULE;
+drivers/gpio/gpio-adnp.c:	adnp->irq_enable = devm_kcalloc(chip->parent, num_regs, 6,
+drivers/gpio/gpio-adnp.c:	err = devm_request_threaded_irq(chip->parent, adnp->client->irq,
+drivers/gpio/gpio-adnp.c:					dev_name(chip->parent), adnp);
+drivers/gpio/gpio-adnp.c:		dev_err(chip->parent, "can't request IRQ#%d: %d\n",
+drivers/gpio/gpio-adnp.c:		dev_err(chip->parent,
+drivers/gpio/gpio-adp5588.c:  * genirq core code can issue chip->mask/unmask from atomic context.
+drivers/gpio/gpio-altera.c:	raw_spin_lock_irqsave(&chip->gpio_lock, flags);
+drivers/gpio/gpio-altera.c:	raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
+drivers/gpio/gpio-altera.c:	raw_spin_lock_irqsave(&chip->gpio_lock, flags);
+drivers/gpio/gpio-altera.c:	raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
+drivers/gpio/gpio-altera.c:	raw_spin_lock_irqsave(&chip->gpio_lock, flags);
+drivers/gpio/gpio-altera.c:	raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
+drivers/gpio/gpio-arizona.c:		pm_runtime_mark_last_busy(chip->parent);
+drivers/gpio/gpio-arizona.c:		pm_runtime_put_autosuspend(chip->parent);
+drivers/gpio/gpio-arizona.c:		ret = pm_runtime_get_sync(chip->parent);
+drivers/gpio/gpio-arizona.c:			dev_err(chip->parent, "Failed to resume: %d\n", ret);
+drivers/gpio/gpio-arizona.c:			dev_err(chip->parent, "Failed to drop cache: %d\n",
+drivers/gpio/gpio-arizona.c:		pm_runtime_mark_last_busy(chip->parent);
+drivers/gpio/gpio-arizona.c:		pm_runtime_put_autosuspend(chip->parent);
+drivers/gpio/gpio-arizona.c:		ret = pm_runtime_get_sync(chip->parent);
+drivers/gpio/gpio-arizona.c:			dev_err(chip->parent, "Failed to resume: %d\n", ret);
+drivers/gpio/gpio-aspeed.c:	return pinctrl_gpio_request(chip->base + offset);
+drivers/gpio/gpio-aspeed.c:	pinctrl_gpio_free(chip->base + offset);
+drivers/gpio/gpio-aspeed.c:		dev_warn(chip->parent, "Failed to convert %luus to cycles at %luHz: %d\n",
+drivers/gpio/gpio-aspeed.c:			dev_warn(chip->parent,
+drivers/gpio/gpio-aspeed.c:		girq->chip->name = dev_name(&pdev->dev);
+drivers/gpio/gpio-aspeed.c:		girq->chip->irq_ack = aspeed_gpio_irq_ack;
+drivers/gpio/gpio-aspeed.c:		girq->chip->irq_mask = aspeed_gpio_irq_mask;
+drivers/gpio/gpio-aspeed.c:		girq->chip->irq_unmask = aspeed_gpio_irq_unmask;
+drivers/gpio/gpio-aspeed.c:		girq->chip->irq_set_type = aspeed_gpio_set_type;
+drivers/gpio/gpio-bcm-kona.c:		dev_err(chip->parent, "Debounce value %u not in range\n",
+drivers/gpio/gpio-bcm-kona.c:	chip->of_node = dev->of_node;
+drivers/gpio/gpio-bcm-kona.c:	chip->ngpio = kona_gpio->num_bank * GPIO_PER_BANK;
+drivers/gpio/gpio-bcm-kona.c:						      chip->ngpio,
+drivers/gpio/gpio-cadence.c:	spin_lock_irqsave(&chip->bgpio_lock, flags);
+drivers/gpio/gpio-cadence.c:	spin_unlock_irqrestore(&chip->bgpio_lock, flags);
+drivers/gpio/gpio-cadence.c:	spin_lock_irqsave(&chip->bgpio_lock, flags);
+drivers/gpio/gpio-cadence.c:	spin_unlock_irqrestore(&chip->bgpio_lock, flags);
+drivers/gpio/gpio-cadence.c:	spin_lock_irqsave(&chip->bgpio_lock, flags);
+drivers/gpio/gpio-cadence.c:	spin_unlock_irqrestore(&chip->bgpio_lock, flags);
+drivers/gpio/gpio-cadence.c:	for_each_set_bit(hwirq, &status, chip->ngpio)
+drivers/gpio/gpio-cadence.c:		generic_handle_irq(irq_find_mapping(chip->irq.domain, hwirq));
+drivers/gpio/gpio-cs5535.c:	unsigned long addr = chip->base + 0x80 + reg;
+drivers/gpio/gpio-cs5535.c:		outl(1 << offset, chip->base + reg);
+drivers/gpio/gpio-cs5535.c:	spin_lock_irqsave(&chip->lock, flags);
+drivers/gpio/gpio-cs5535.c:	spin_unlock_irqrestore(&chip->lock, flags);
+drivers/gpio/gpio-cs5535.c:		outl(1 << (offset + 16), chip->base + reg);
+drivers/gpio/gpio-cs5535.c:	spin_lock_irqsave(&chip->lock, flags);
+drivers/gpio/gpio-cs5535.c:	spin_unlock_irqrestore(&chip->lock, flags);
+drivers/gpio/gpio-cs5535.c:	spin_lock_irqsave(&chip->lock, flags);
+drivers/gpio/gpio-cs5535.c:		val = inl(chip->base + reg);
+drivers/gpio/gpio-cs5535.c:		val = inl(chip->base + 0x80 + reg);
+drivers/gpio/gpio-cs5535.c:	spin_unlock_irqrestore(&chip->lock, flags);
+drivers/gpio/gpio-cs5535.c:	spin_lock_irqsave(&chip->lock, flags);
+drivers/gpio/gpio-cs5535.c:	val = inl(chip->base + offset);
+drivers/gpio/gpio-cs5535.c:	outl(val, chip->base + offset);
+drivers/gpio/gpio-cs5535.c:	spin_unlock_irqrestore(&chip->lock, flags);
+drivers/gpio/gpio-cs5535.c:	spin_lock_irqsave(&chip->lock, flags);
+drivers/gpio/gpio-cs5535.c:		dev_info(&chip->pdev->dev,
+drivers/gpio/gpio-cs5535.c:		spin_unlock_irqrestore(&chip->lock, flags);
+drivers/gpio/gpio-cs5535.c:	spin_unlock_irqrestore(&chip->lock, flags);
+drivers/gpio/gpio-cs5535.c:	spin_lock_irqsave(&chip->lock, flags);
+drivers/gpio/gpio-cs5535.c:	spin_unlock_irqrestore(&chip->lock, flags);
+drivers/gpio/gpio-cs5535.c:	spin_lock_irqsave(&chip->lock, flags);
+drivers/gpio/gpio-cs5535.c:	spin_unlock_irqrestore(&chip->lock, flags);
+drivers/gpio/gpio-davinci.c:		irq_chip->name = "GPIO-AINTC";
+drivers/gpio/gpio-davinci.c:		irq_chip->irq_set_type = gpio_irq_type_unbanked;
+drivers/gpio/gpio-dwapb.c:	if (chip->irq_eoi)
+drivers/gpio/gpio-dwapb.c:		chip->irq_eoi(irq_desc_get_irq_data(desc));
+drivers/gpio/gpio-eic-sprd.c:		dev_err(chip->parent, "Unsupported EIC type.\n");
+drivers/gpio/gpio-eic-sprd.c:		dev_err(chip->parent, "Unsupported EIC type.\n");
+drivers/gpio/gpio-eic-sprd.c:		dev_err(chip->parent, "Unsupported EIC type.\n");
+drivers/gpio/gpio-eic-sprd.c:		dev_err(chip->parent, "Unsupported EIC type.\n");
+drivers/gpio/gpio-eic-sprd.c:		dev_warn(chip->parent, "EIC level was changed.\n");
+drivers/gpio/gpio-eic-sprd.c:	return !strcmp(chip->label, sprd_eic_label_name[type]);
+drivers/gpio/gpio-eic-sprd.c:	for (bank = 0; bank * SPRD_EIC_PER_BANK_NR < chip->ngpio; bank++) {
+drivers/gpio/gpio-eic-sprd.c:			dev_err(chip->parent, "Unsupported EIC type.\n");
+drivers/gpio/gpio-eic-sprd.c:			girq = irq_find_mapping(chip->irq.domain, offset);
+drivers/gpio/gpio-em.c:	return pinctrl_gpio_request(chip->base + offset);
+drivers/gpio/gpio-em.c:	pinctrl_gpio_free(chip->base + offset);
+drivers/gpio/gpio-em.c:	gpio_chip->of_node = dev->of_node;
+drivers/gpio/gpio-em.c:	gpio_chip->direction_input = em_gio_direction_input;
+drivers/gpio/gpio-em.c:	gpio_chip->get = em_gio_get;
+drivers/gpio/gpio-em.c:	gpio_chip->direction_output = em_gio_direction_output;
+drivers/gpio/gpio-em.c:	gpio_chip->set = em_gio_set;
+drivers/gpio/gpio-em.c:	gpio_chip->to_irq = em_gio_to_irq;
+drivers/gpio/gpio-em.c:	gpio_chip->request = em_gio_request;
+drivers/gpio/gpio-em.c:	gpio_chip->free = em_gio_free;
+drivers/gpio/gpio-em.c:	gpio_chip->label = name;
+drivers/gpio/gpio-em.c:	gpio_chip->parent = dev;
+drivers/gpio/gpio-em.c:	gpio_chip->owner = THIS_MODULE;
+drivers/gpio/gpio-em.c:	gpio_chip->base = -1;
+drivers/gpio/gpio-em.c:	gpio_chip->ngpio = ngpios;
+drivers/gpio/gpio-em.c:	irq_chip->name = "gpio-em";
+drivers/gpio/gpio-em.c:	irq_chip->irq_mask = em_gio_irq_disable;
+drivers/gpio/gpio-em.c:	irq_chip->irq_unmask = em_gio_irq_enable;
+drivers/gpio/gpio-em.c:	irq_chip->irq_set_type = em_gio_irq_set_type;
+drivers/gpio/gpio-em.c:	irq_chip->irq_request_resources = em_gio_irq_reqres;
+drivers/gpio/gpio-em.c:	irq_chip->irq_release_resources = em_gio_irq_relres;
+drivers/gpio/gpio-em.c:	irq_chip->flags	= IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;
+drivers/gpio/gpio-gpio-mm.c:	bitmap_zero(bits, chip->ngpio);
+drivers/gpio/gpio-htc-egpio.c:	pr_debug("egpio_get_value(%d)\n", chip->base + offset);
+drivers/gpio/gpio-htc-egpio.c:			chip->label, offset, offset+chip->base, value);
+drivers/gpio/gpio-htc-egpio.c:		chip->label = devm_kasprintf(&pdev->dev, GFP_KERNEL,
+drivers/gpio/gpio-htc-egpio.c:		if (!chip->label)
+drivers/gpio/gpio-htc-egpio.c:		chip->parent          = &pdev->dev;
+drivers/gpio/gpio-htc-egpio.c:		chip->owner           = THIS_MODULE;
+drivers/gpio/gpio-htc-egpio.c:		chip->get             = egpio_get;
+drivers/gpio/gpio-htc-egpio.c:		chip->set             = egpio_set;
+drivers/gpio/gpio-htc-egpio.c:		chip->direction_input = egpio_direction_input;
+drivers/gpio/gpio-htc-egpio.c:		chip->direction_output = egpio_direction_output;
+drivers/gpio/gpio-htc-egpio.c:		chip->get_direction   = egpio_get_direction;
+drivers/gpio/gpio-htc-egpio.c:		chip->base            = pdata->chip[i].gpio_base;
+drivers/gpio/gpio-htc-egpio.c:		chip->ngpio           = pdata->chip[i].num_gpios;
+drivers/gpio/gpio-ich.c:	chip->owner = THIS_MODULE;
+drivers/gpio/gpio-ich.c:	chip->label = DRV_NAME;
+drivers/gpio/gpio-ich.c:	chip->parent = ichx_priv.dev;
+drivers/gpio/gpio-ich.c:	/* Allow chip-specific overrides of request()/get() */
+drivers/gpio/gpio-ich.c:	chip->request = ichx_priv.desc->request ?
+drivers/gpio/gpio-ich.c:	chip->get = ichx_priv.desc->get ?
+drivers/gpio/gpio-ich.c:	chip->set = ichx_gpio_set;
+drivers/gpio/gpio-ich.c:	chip->get_direction = ichx_gpio_get_direction;
+drivers/gpio/gpio-ich.c:	chip->direction_input = ichx_gpio_direction_input;
+drivers/gpio/gpio-ich.c:	chip->direction_output = ichx_gpio_direction_output;
+drivers/gpio/gpio-ich.c:	chip->base = modparam_gpiobase;
+drivers/gpio/gpio-ich.c:	chip->ngpio = ichx_priv.desc->ngpio;
+drivers/gpio/gpio-ich.c:	chip->can_sleep = false;
+drivers/gpio/gpio-ich.c:	chip->dbg_show = NULL;
+drivers/gpio/gpio-intel-mid.c:	unsigned nreg = chip->ngpio / 32;
+drivers/gpio/gpio-intel-mid.c:	unsigned nreg = chip->ngpio / 32;
+drivers/gpio/gpio-intel-mid.c:	chip->irq_eoi(data);
+drivers/gpio/gpio-kempld.c:	chip->label = "gpio-kempld";
+drivers/gpio/gpio-kempld.c:	chip->owner = THIS_MODULE;
+drivers/gpio/gpio-kempld.c:	chip->parent = dev;
+drivers/gpio/gpio-kempld.c:	chip->can_sleep = true;
+drivers/gpio/gpio-kempld.c:		chip->base = pdata->gpio_base;
+drivers/gpio/gpio-kempld.c:		chip->base = -1;
+drivers/gpio/gpio-kempld.c:	chip->direction_input = kempld_gpio_direction_input;
+drivers/gpio/gpio-kempld.c:	chip->direction_output = kempld_gpio_direction_output;
+drivers/gpio/gpio-kempld.c:	chip->get_direction = kempld_gpio_get_direction;
+drivers/gpio/gpio-kempld.c:	chip->get = kempld_gpio_get;
+drivers/gpio/gpio-kempld.c:	chip->set = kempld_gpio_set;
+drivers/gpio/gpio-kempld.c:	chip->ngpio = kempld_gpio_pincount(pld);
+drivers/gpio/gpio-kempld.c:	if (chip->ngpio == 0) {
+drivers/gpio/gpio-kempld.c:		 chip->ngpio);
+drivers/gpio/gpio-lpc32xx.c:	if (pin < chip->ngpio)
+drivers/gpio/gpio-lynxpoint.c:	chip->irq_eoi(data);
+drivers/gpio/gpio-max732x.c:	client = group_a ? chip->client_group_a : chip->client_group_b;
+drivers/gpio/gpio-max732x.c:	client = group_a ? chip->client_group_a : chip->client_group_b;
+drivers/gpio/gpio-max732x.c:	return (1u << off) & chip->mask_group_a;
+drivers/gpio/gpio-max732x.c:	mutex_lock(&chip->lock);
+drivers/gpio/gpio-max732x.c:	reg_out = (off > 7) ? chip->reg_out[1] : chip->reg_out[0];
+drivers/gpio/gpio-max732x.c:		chip->reg_out[1] = reg_out;
+drivers/gpio/gpio-max732x.c:		chip->reg_out[0] = reg_out;
+drivers/gpio/gpio-max732x.c:	mutex_unlock(&chip->lock);
+drivers/gpio/gpio-max732x.c:	if ((mask & chip->dir_input) == 0) {
+drivers/gpio/gpio-max732x.c:		dev_dbg(&chip->client->dev, "%s port %d is output only\n",
+drivers/gpio/gpio-max732x.c:			chip->client->name, off);
+drivers/gpio/gpio-max732x.c:	if ((mask & chip->dir_output))
+drivers/gpio/gpio-max732x.c:	if ((mask & chip->dir_output) == 0) {
+drivers/gpio/gpio-max732x.c:		dev_dbg(&chip->client->dev, "%s port %d is input only\n",
+drivers/gpio/gpio-max732x.c:			chip->client->name, off);
+drivers/gpio/gpio-max732x.c:	ret = i2c_master_send(chip->client_group_a, (char *)&val, 2);
+drivers/gpio/gpio-max732x.c:		dev_err(&chip->client_group_a->dev, "failed writing\n");
+drivers/gpio/gpio-max732x.c:	ret = i2c_master_recv(chip->client_group_a, (char *)val, 2);
+drivers/gpio/gpio-max732x.c:		dev_err(&chip->client_group_a->dev, "failed reading\n");
+drivers/gpio/gpio-max732x.c:	if (chip->irq_mask == chip->irq_mask_cur)
+drivers/gpio/gpio-max732x.c:	chip->irq_mask = chip->irq_mask_cur;
+drivers/gpio/gpio-max732x.c:	if (chip->irq_features == INT_NO_MASK)
+drivers/gpio/gpio-max732x.c:	mutex_lock(&chip->lock);
+drivers/gpio/gpio-max732x.c:	switch (chip->irq_features) {
+drivers/gpio/gpio-max732x.c:		msg = (chip->irq_mask << 8) | chip->reg_out[0];
+drivers/gpio/gpio-max732x.c:		msg = chip->irq_mask | chip->reg_out[0];
+drivers/gpio/gpio-max732x.c:	mutex_unlock(&chip->lock);
+drivers/gpio/gpio-max732x.c:	chip->irq_mask_cur &= ~(1 << d->hwirq);
+drivers/gpio/gpio-max732x.c:	chip->irq_mask_cur |= 1 << d->hwirq;
+drivers/gpio/gpio-max732x.c:	mutex_lock(&chip->irq_lock);
+drivers/gpio/gpio-max732x.c:	chip->irq_mask_cur = chip->irq_mask;
+drivers/gpio/gpio-max732x.c:	new_irqs = chip->irq_trig_fall | chip->irq_trig_raise;
+drivers/gpio/gpio-max732x.c:		max732x_gpio_direction_input(&chip->gpio_chip, level);
+drivers/gpio/gpio-max732x.c:	mutex_unlock(&chip->irq_lock);
+drivers/gpio/gpio-max732x.c:	if (!(mask & chip->dir_input)) {
+drivers/gpio/gpio-max732x.c:		dev_dbg(&chip->client->dev, "%s port %d is output only\n",
+drivers/gpio/gpio-max732x.c:			chip->client->name, off);
+drivers/gpio/gpio-max732x.c:		dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
+drivers/gpio/gpio-max732x.c:		chip->irq_trig_fall |= mask;
+drivers/gpio/gpio-max732x.c:		chip->irq_trig_fall &= ~mask;
+drivers/gpio/gpio-max732x.c:		chip->irq_trig_raise |= mask;
+drivers/gpio/gpio-max732x.c:		chip->irq_trig_raise &= ~mask;
+drivers/gpio/gpio-max732x.c:	irq_set_irq_wake(chip->client->irq, on);
+drivers/gpio/gpio-max732x.c:	trigger &= chip->irq_mask;
+drivers/gpio/gpio-max732x.c:	cur_stat &= chip->irq_mask;
+drivers/gpio/gpio-max732x.c:	pending = (old_stat & chip->irq_trig_fall) |
+drivers/gpio/gpio-max732x.c:		  (cur_stat & chip->irq_trig_raise);
+drivers/gpio/gpio-max732x.c:		handle_nested_irq(irq_find_mapping(chip->gpio_chip.irq.domain,
+drivers/gpio/gpio-max732x.c:	struct i2c_client *client = chip->client;
+drivers/gpio/gpio-max732x.c:		chip->irq_features = has_irq;
+drivers/gpio/gpio-max732x.c:		mutex_init(&chip->irq_lock);
+drivers/gpio/gpio-max732x.c:		ret =  gpiochip_irqchip_add_nested(&chip->gpio_chip,
+drivers/gpio/gpio-max732x.c:		gpiochip_set_nested_irqchip(&chip->gpio_chip,
+drivers/gpio/gpio-max732x.c:	struct i2c_client *client = chip->client;
+drivers/gpio/gpio-max732x.c:	struct gpio_chip *gc = &chip->gpio_chip;
+drivers/gpio/gpio-max732x.c:			chip->dir_output |= mask;
+drivers/gpio/gpio-max732x.c:			chip->dir_input |= mask;
+drivers/gpio/gpio-max732x.c:			chip->dir_output |= mask;
+drivers/gpio/gpio-max732x.c:			chip->dir_input |= mask;
+drivers/gpio/gpio-max732x.c:			chip->mask_group_a |= mask;
+drivers/gpio/gpio-max732x.c:	if (chip->dir_input)
+drivers/gpio/gpio-max732x.c:	if (chip->dir_output) {
+drivers/gpio/gpio-max732x.c:	gc->label = chip->client->name;
+drivers/gpio/gpio-max732x.c:	gc->parent = &chip->client->dev;
+drivers/gpio/gpio-max732x.c:	chip->client = client;
+drivers/gpio/gpio-max732x.c:	chip->gpio_chip.parent = &client->dev;
+drivers/gpio/gpio-max732x.c:		chip->client_group_a = client;
+drivers/gpio/gpio-max732x.c:			chip->client_group_b = chip->client_dummy = c;
+drivers/gpio/gpio-max732x.c:		chip->client_group_b = client;
+drivers/gpio/gpio-max732x.c:			chip->client_group_a = chip->client_dummy = c;
+drivers/gpio/gpio-max732x.c:	if (nr_port > 8 && !chip->client_dummy) {
+drivers/gpio/gpio-max732x.c:	mutex_init(&chip->lock);
+drivers/gpio/gpio-max732x.c:	ret = max732x_readb(chip, is_group_a(chip, 0), &chip->reg_out[0]);
+drivers/gpio/gpio-max732x.c:		ret = max732x_readb(chip, is_group_a(chip, 8), &chip->reg_out[1]);
+drivers/gpio/gpio-max732x.c:	ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip);
+drivers/gpio/gpio-max732x.c:		ret = pdata->setup(client, chip->gpio_chip.base,
+drivers/gpio/gpio-max732x.c:				chip->gpio_chip.ngpio, pdata->context);
+drivers/gpio/gpio-max732x.c:		ret = pdata->teardown(client, chip->gpio_chip.base,
+drivers/gpio/gpio-max732x.c:				chip->gpio_chip.ngpio, pdata->context);
+drivers/gpio/gpio-max77620.c:		dev_err(chip->parent, "failed to update interrupt mask: %d\n",
+drivers/gpio/gpio-max77620.c:	mgpio->rmap = chip->rmap;
+drivers/gpio/gpio-max77650.c:	return regmap_update_bits(chip->map,
+drivers/gpio/gpio-max77650.c:	return regmap_update_bits(chip->map,
+drivers/gpio/gpio-max77650.c:	rv = regmap_update_bits(chip->map, MAX77650_REG_CNFG_GPIO,
+drivers/gpio/gpio-max77650.c:	rv = regmap_read(chip->map, MAX77650_REG_CNFG_GPIO, &val);
+drivers/gpio/gpio-max77650.c:	rv = regmap_read(chip->map, MAX77650_REG_CNFG_GPIO, &val);
+drivers/gpio/gpio-max77650.c:		return regmap_update_bits(chip->map,
+drivers/gpio/gpio-max77650.c:		return regmap_update_bits(chip->map,
+drivers/gpio/gpio-max77650.c:		return regmap_update_bits(chip->map,
+drivers/gpio/gpio-max77650.c:	return chip->irq;
+drivers/gpio/gpio-max77650.c:	chip->map = dev_get_regmap(parent, NULL);
+drivers/gpio/gpio-max77650.c:	if (!chip->map)
+drivers/gpio/gpio-max77650.c:	chip->irq = platform_get_irq_byname(pdev, "GPI");
+drivers/gpio/gpio-max77650.c:	if (chip->irq < 0)
+drivers/gpio/gpio-max77650.c:		return chip->irq;
+drivers/gpio/gpio-max77650.c:	chip->gc.base = -1;
+drivers/gpio/gpio-max77650.c:	chip->gc.ngpio = 1;
+drivers/gpio/gpio-max77650.c:	chip->gc.label = i2c->name;
+drivers/gpio/gpio-max77650.c:	chip->gc.parent = dev;
+drivers/gpio/gpio-max77650.c:	chip->gc.owner = THIS_MODULE;
+drivers/gpio/gpio-max77650.c:	chip->gc.can_sleep = true;
+drivers/gpio/gpio-max77650.c:	chip->gc.direction_input = max77650_gpio_direction_input;
+drivers/gpio/gpio-max77650.c:	chip->gc.direction_output = max77650_gpio_direction_output;
+drivers/gpio/gpio-max77650.c:	chip->gc.set = max77650_gpio_set_value;
+drivers/gpio/gpio-max77650.c:	chip->gc.get = max77650_gpio_get_value;
+drivers/gpio/gpio-max77650.c:	chip->gc.get_direction = max77650_gpio_get_direction;
+drivers/gpio/gpio-max77650.c:	chip->gc.set_config = max77650_gpio_set_config;
+drivers/gpio/gpio-max77650.c:	chip->gc.to_irq = max77650_gpio_to_irq;
+drivers/gpio/gpio-max77650.c:	return devm_gpiochip_add_data(dev, &chip->gc, chip);
+drivers/gpio/gpio-mb86s7x.c:	spin_lock_irqsave(&gchip->lock, flags);
+drivers/gpio/gpio-mb86s7x.c:	val = readl(gchip->base + PFR(gpio));
+drivers/gpio/gpio-mb86s7x.c:	writel(val, gchip->base + PFR(gpio));
+drivers/gpio/gpio-mb86s7x.c:	spin_unlock_irqrestore(&gchip->lock, flags);
+drivers/gpio/gpio-mb86s7x.c:	spin_lock_irqsave(&gchip->lock, flags);
+drivers/gpio/gpio-mb86s7x.c:	val = readl(gchip->base + PFR(gpio));
+drivers/gpio/gpio-mb86s7x.c:	writel(val, gchip->base + PFR(gpio));
+drivers/gpio/gpio-mb86s7x.c:	spin_unlock_irqrestore(&gchip->lock, flags);
+drivers/gpio/gpio-mb86s7x.c:	spin_lock_irqsave(&gchip->lock, flags);
+drivers/gpio/gpio-mb86s7x.c:	val = readl(gchip->base + DDR(gpio));
+drivers/gpio/gpio-mb86s7x.c:	writel(val, gchip->base + DDR(gpio));
+drivers/gpio/gpio-mb86s7x.c:	spin_unlock_irqrestore(&gchip->lock, flags);
+drivers/gpio/gpio-mb86s7x.c:	spin_lock_irqsave(&gchip->lock, flags);
+drivers/gpio/gpio-mb86s7x.c:	val = readl(gchip->base + PDR(gpio));
+drivers/gpio/gpio-mb86s7x.c:	writel(val, gchip->base + PDR(gpio));
+drivers/gpio/gpio-mb86s7x.c:	val = readl(gchip->base + DDR(gpio));
+drivers/gpio/gpio-mb86s7x.c:	writel(val, gchip->base + DDR(gpio));
+drivers/gpio/gpio-mb86s7x.c:	spin_unlock_irqrestore(&gchip->lock, flags);
+drivers/gpio/gpio-mb86s7x.c:	return !!(readl(gchip->base + PDR(gpio)) & OFFSET(gpio));
+drivers/gpio/gpio-mb86s7x.c:	spin_lock_irqsave(&gchip->lock, flags);
+drivers/gpio/gpio-mb86s7x.c:	val = readl(gchip->base + PDR(gpio));
+drivers/gpio/gpio-mb86s7x.c:	writel(val, gchip->base + PDR(gpio));
+drivers/gpio/gpio-mb86s7x.c:	spin_unlock_irqrestore(&gchip->lock, flags);
+drivers/gpio/gpio-mb86s7x.c:	gchip->base = devm_platform_ioremap_resource(pdev, 0);
+drivers/gpio/gpio-mb86s7x.c:	if (IS_ERR(gchip->base))
+drivers/gpio/gpio-mb86s7x.c:		return PTR_ERR(gchip->base);
+drivers/gpio/gpio-mb86s7x.c:		gchip->clk = devm_clk_get(&pdev->dev, NULL);
+drivers/gpio/gpio-mb86s7x.c:		if (IS_ERR(gchip->clk))
+drivers/gpio/gpio-mb86s7x.c:			return PTR_ERR(gchip->clk);
+drivers/gpio/gpio-mb86s7x.c:		ret = clk_prepare_enable(gchip->clk);
+drivers/gpio/gpio-mb86s7x.c:	spin_lock_init(&gchip->lock);
+drivers/gpio/gpio-mb86s7x.c:	gchip->gc.direction_output = mb86s70_gpio_direction_output;
+drivers/gpio/gpio-mb86s7x.c:	gchip->gc.direction_input = mb86s70_gpio_direction_input;
+drivers/gpio/gpio-mb86s7x.c:	gchip->gc.request = mb86s70_gpio_request;
+drivers/gpio/gpio-mb86s7x.c:	gchip->gc.free = mb86s70_gpio_free;
+drivers/gpio/gpio-mb86s7x.c:	gchip->gc.get = mb86s70_gpio_get;
+drivers/gpio/gpio-mb86s7x.c:	gchip->gc.set = mb86s70_gpio_set;
+drivers/gpio/gpio-mb86s7x.c:	gchip->gc.label = dev_name(&pdev->dev);
+drivers/gpio/gpio-mb86s7x.c:	gchip->gc.ngpio = 32;
+drivers/gpio/gpio-mb86s7x.c:	gchip->gc.owner = THIS_MODULE;
+drivers/gpio/gpio-mb86s7x.c:	gchip->gc.parent = &pdev->dev;
+drivers/gpio/gpio-mb86s7x.c:	gchip->gc.base = -1;
+drivers/gpio/gpio-mb86s7x.c:		gchip->gc.to_irq = mb86s70_gpio_to_irq;
+drivers/gpio/gpio-mb86s7x.c:	ret = gpiochip_add_data(&gchip->gc, gchip);
+drivers/gpio/gpio-mb86s7x.c:		clk_disable_unprepare(gchip->clk);
+drivers/gpio/gpio-mb86s7x.c:		acpi_gpiochip_request_interrupts(&gchip->gc);
+drivers/gpio/gpio-mb86s7x.c:		acpi_gpiochip_free_interrupts(&gchip->gc);
+drivers/gpio/gpio-mb86s7x.c:	gpiochip_remove(&gchip->gc);
+drivers/gpio/gpio-mb86s7x.c:	clk_disable_unprepare(gchip->clk);
+drivers/gpio/gpio-ml-ioh.c:	spin_lock_irqsave(&chip->spinlock, flags);
+drivers/gpio/gpio-ml-ioh.c:	reg_val = ioread32(&chip->reg->regs[chip->ch].po);
+drivers/gpio/gpio-ml-ioh.c:	iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
+drivers/gpio/gpio-ml-ioh.c:	spin_unlock_irqrestore(&chip->spinlock, flags);
+drivers/gpio/gpio-ml-ioh.c:	return !!(ioread32(&chip->reg->regs[chip->ch].pi) & (1 << nr));
+drivers/gpio/gpio-ml-ioh.c:	spin_lock_irqsave(&chip->spinlock, flags);
+drivers/gpio/gpio-ml-ioh.c:	pm = ioread32(&chip->reg->regs[chip->ch].pm) &
+drivers/gpio/gpio-ml-ioh.c:					((1 << num_ports[chip->ch]) - 1);
+drivers/gpio/gpio-ml-ioh.c:	iowrite32(pm, &chip->reg->regs[chip->ch].pm);
+drivers/gpio/gpio-ml-ioh.c:	reg_val = ioread32(&chip->reg->regs[chip->ch].po);
+drivers/gpio/gpio-ml-ioh.c:	iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
+drivers/gpio/gpio-ml-ioh.c:	spin_unlock_irqrestore(&chip->spinlock, flags);
+drivers/gpio/gpio-ml-ioh.c:	spin_lock_irqsave(&chip->spinlock, flags);
+drivers/gpio/gpio-ml-ioh.c:	pm = ioread32(&chip->reg->regs[chip->ch].pm) &
+drivers/gpio/gpio-ml-ioh.c:				((1 << num_ports[chip->ch]) - 1);
+drivers/gpio/gpio-ml-ioh.c:	iowrite32(pm, &chip->reg->regs[chip->ch].pm);
+drivers/gpio/gpio-ml-ioh.c:	spin_unlock_irqrestore(&chip->spinlock, flags);
+drivers/gpio/gpio-ml-ioh.c:		chip->ioh_gpio_reg.po_reg =
+drivers/gpio/gpio-ml-ioh.c:					ioread32(&chip->reg->regs[chip->ch].po);
+drivers/gpio/gpio-ml-ioh.c:		chip->ioh_gpio_reg.pm_reg =
+drivers/gpio/gpio-ml-ioh.c:					ioread32(&chip->reg->regs[chip->ch].pm);
+drivers/gpio/gpio-ml-ioh.c:		chip->ioh_gpio_reg.ien_reg =
+drivers/gpio/gpio-ml-ioh.c:				       ioread32(&chip->reg->regs[chip->ch].ien);
+drivers/gpio/gpio-ml-ioh.c:		chip->ioh_gpio_reg.imask_reg =
+drivers/gpio/gpio-ml-ioh.c:				     ioread32(&chip->reg->regs[chip->ch].imask);
+drivers/gpio/gpio-ml-ioh.c:		chip->ioh_gpio_reg.im0_reg =
+drivers/gpio/gpio-ml-ioh.c:				      ioread32(&chip->reg->regs[chip->ch].im_0);
+drivers/gpio/gpio-ml-ioh.c:		chip->ioh_gpio_reg.im1_reg =
+drivers/gpio/gpio-ml-ioh.c:				      ioread32(&chip->reg->regs[chip->ch].im_1);
+drivers/gpio/gpio-ml-ioh.c:			chip->ioh_gpio_reg.use_sel_reg =
+drivers/gpio/gpio-ml-ioh.c:					   ioread32(&chip->reg->ioh_sel_reg[i]);
+drivers/gpio/gpio-ml-ioh.c:		iowrite32(chip->ioh_gpio_reg.po_reg,
+drivers/gpio/gpio-ml-ioh.c:			  &chip->reg->regs[chip->ch].po);
+drivers/gpio/gpio-ml-ioh.c:		iowrite32(chip->ioh_gpio_reg.pm_reg,
+drivers/gpio/gpio-ml-ioh.c:			  &chip->reg->regs[chip->ch].pm);
+drivers/gpio/gpio-ml-ioh.c:		iowrite32(chip->ioh_gpio_reg.ien_reg,
+drivers/gpio/gpio-ml-ioh.c:			  &chip->reg->regs[chip->ch].ien);
+drivers/gpio/gpio-ml-ioh.c:		iowrite32(chip->ioh_gpio_reg.imask_reg,
+drivers/gpio/gpio-ml-ioh.c:			  &chip->reg->regs[chip->ch].imask);
+drivers/gpio/gpio-ml-ioh.c:		iowrite32(chip->ioh_gpio_reg.im0_reg,
+drivers/gpio/gpio-ml-ioh.c:			  &chip->reg->regs[chip->ch].im_0);
+drivers/gpio/gpio-ml-ioh.c:		iowrite32(chip->ioh_gpio_reg.im1_reg,
+drivers/gpio/gpio-ml-ioh.c:			  &chip->reg->regs[chip->ch].im_1);
+drivers/gpio/gpio-ml-ioh.c:			iowrite32(chip->ioh_gpio_reg.use_sel_reg,
+drivers/gpio/gpio-ml-ioh.c:				  &chip->reg->ioh_sel_reg[i]);
+drivers/gpio/gpio-ml-ioh.c:	return chip->irq_base + offset;
+drivers/gpio/gpio-ml-ioh.c:	struct gpio_chip *gpio = &chip->gpio;
+drivers/gpio/gpio-ml-ioh.c:	gpio->label = dev_name(chip->dev);
+drivers/gpio/gpio-ml-ioh.c:	ch = irq - chip->irq_base;
+drivers/gpio/gpio-ml-ioh.c:	if (irq <= chip->irq_base + 7) {
+drivers/gpio/gpio-ml-ioh.c:		im_reg = &chip->reg->regs[chip->ch].im_0;
+drivers/gpio/gpio-ml-ioh.c:		im_reg = &chip->reg->regs[chip->ch].im_1;
+drivers/gpio/gpio-ml-ioh.c:	dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d type=%d\n",
+drivers/gpio/gpio-ml-ioh.c:	spin_lock_irqsave(&chip->spinlock, flags);
+drivers/gpio/gpio-ml-ioh.c:		dev_warn(chip->dev, "%s: unknown type(%dd)",
+drivers/gpio/gpio-ml-ioh.c:	iowrite32(BIT(ch), &chip->reg->regs[chip->ch].iclr);
+drivers/gpio/gpio-ml-ioh.c:	iowrite32(BIT(ch), &chip->reg->regs[chip->ch].imaskclr);
+drivers/gpio/gpio-ml-ioh.c:	ien = ioread32(&chip->reg->regs[chip->ch].ien);
+drivers/gpio/gpio-ml-ioh.c:	iowrite32(ien | BIT(ch), &chip->reg->regs[chip->ch].ien);
+drivers/gpio/gpio-ml-ioh.c:	spin_unlock_irqrestore(&chip->spinlock, flags);
+drivers/gpio/gpio-ml-ioh.c:	iowrite32(1 << (d->irq - chip->irq_base),
+drivers/gpio/gpio-ml-ioh.c:		  &chip->reg->regs[chip->ch].imaskclr);
+drivers/gpio/gpio-ml-ioh.c:	iowrite32(1 << (d->irq - chip->irq_base),
+drivers/gpio/gpio-ml-ioh.c:		  &chip->reg->regs[chip->ch].imask);
+drivers/gpio/gpio-ml-ioh.c:	spin_lock_irqsave(&chip->spinlock, flags);
+drivers/gpio/gpio-ml-ioh.c:	ien = ioread32(&chip->reg->regs[chip->ch].ien);
+drivers/gpio/gpio-ml-ioh.c:	ien &= ~(1 << (d->irq - chip->irq_base));
+drivers/gpio/gpio-ml-ioh.c:	iowrite32(ien, &chip->reg->regs[chip->ch].ien);
+drivers/gpio/gpio-ml-ioh.c:	spin_unlock_irqrestore(&chip->spinlock, flags);
+drivers/gpio/gpio-ml-ioh.c:	spin_lock_irqsave(&chip->spinlock, flags);
+drivers/gpio/gpio-ml-ioh.c:	ien = ioread32(&chip->reg->regs[chip->ch].ien);
+drivers/gpio/gpio-ml-ioh.c:	ien |= 1 << (d->irq - chip->irq_base);
+drivers/gpio/gpio-ml-ioh.c:	iowrite32(ien, &chip->reg->regs[chip->ch].ien);
+drivers/gpio/gpio-ml-ioh.c:	spin_unlock_irqrestore(&chip->spinlock, flags);
+drivers/gpio/gpio-ml-ioh.c:		reg_val = ioread32(&chip->reg->regs[i].istatus);
+drivers/gpio/gpio-ml-ioh.c:				dev_dbg(chip->dev,
+drivers/gpio/gpio-ml-ioh.c:					  &chip->reg->regs[chip->ch].iclr);
+drivers/gpio/gpio-ml-ioh.c:				generic_handle_irq(chip->irq_base + j);
+drivers/gpio/gpio-ml-ioh.c:	gc = devm_irq_alloc_generic_chip(chip->dev, "ioh_gpio", 1, irq_start,
+drivers/gpio/gpio-ml-ioh.c:					 chip->base, handle_simple_irq);
+drivers/gpio/gpio-ml-ioh.c:	rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num),
+drivers/gpio/gpio-ml-ioh.c:		chip->dev = &pdev->dev;
+drivers/gpio/gpio-ml-ioh.c:		chip->base = base;
+drivers/gpio/gpio-ml-ioh.c:		chip->reg = chip->base;
+drivers/gpio/gpio-ml-ioh.c:		chip->ch = i;
+drivers/gpio/gpio-ml-ioh.c:		spin_lock_init(&chip->spinlock);
+drivers/gpio/gpio-ml-ioh.c:		ret = gpiochip_add_data(&chip->gpio, chip);
+drivers/gpio/gpio-ml-ioh.c:		chip->irq_base = irq_base;
+drivers/gpio/gpio-ml-ioh.c:		gpiochip_remove(&chip->gpio);
+drivers/gpio/gpio-ml-ioh.c:		gpiochip_remove(&chip->gpio);
+drivers/gpio/gpio-ml-ioh.c:	pci_iounmap(pdev, chip->base);
+drivers/gpio/gpio-ml-ioh.c:	spin_lock_irqsave(&chip->spinlock, flags);
+drivers/gpio/gpio-ml-ioh.c:	spin_unlock_irqrestore(&chip->spinlock, flags);
+drivers/gpio/gpio-ml-ioh.c:	spin_lock_irqsave(&chip->spinlock, flags);
+drivers/gpio/gpio-ml-ioh.c:	iowrite32(0x01, &chip->reg->srst);
+drivers/gpio/gpio-ml-ioh.c:	iowrite32(0x00, &chip->reg->srst);
+drivers/gpio/gpio-ml-ioh.c:	spin_unlock_irqrestore(&chip->spinlock, flags);
+drivers/gpio/gpio-mm-lantiq.c:	__raw_writew(chip->shadow, chip->mmchip.regs);
+drivers/gpio/gpio-mm-lantiq.c: * ltq_mm_set() - gpio_chip->set - set gpios.
+drivers/gpio/gpio-mm-lantiq.c:		chip->shadow |= (1 << offset);
+drivers/gpio/gpio-mm-lantiq.c:		chip->shadow &= ~(1 << offset);
+drivers/gpio/gpio-mm-lantiq.c: * ltq_mm_dir_out() - gpio_chip->dir_out - set gpio direction.
+drivers/gpio/gpio-mm-lantiq.c:	ltq_ebu_w32(CPHYSADDR(chip->mmchip.regs) | 0x1, LTQ_EBU_ADDRSEL1);
+drivers/gpio/gpio-mm-lantiq.c:	chip->mmchip.gc.ngpio = 16;
+drivers/gpio/gpio-mm-lantiq.c:	chip->mmchip.gc.direction_output = ltq_mm_dir_out;
+drivers/gpio/gpio-mm-lantiq.c:	chip->mmchip.gc.set = ltq_mm_set;
+drivers/gpio/gpio-mm-lantiq.c:	chip->mmchip.save_regs = ltq_mm_save_regs;
+drivers/gpio/gpio-mm-lantiq.c:		chip->shadow = shadow;
+drivers/gpio/gpio-mm-lantiq.c:	return of_mm_gpiochip_add_data(pdev->dev.of_node, &chip->mmchip, chip);
+drivers/gpio/gpio-mm-lantiq.c:	of_mm_gpiochip_remove(&chip->mmchip);
+drivers/gpio/gpio-mmio.c:	if (gpio_pin < chip->ngpio)
+drivers/gpio/gpio-mockup.c:	return chip->lines[offset].value;
+drivers/gpio/gpio-mockup.c:	mutex_lock(&chip->lock);
+drivers/gpio/gpio-mockup.c:	mutex_unlock(&chip->lock);
+drivers/gpio/gpio-mockup.c:	mutex_lock(&chip->lock);
+drivers/gpio/gpio-mockup.c:	mutex_unlock(&chip->lock);
+drivers/gpio/gpio-mockup.c:	chip->lines[offset].value = !!value;
+drivers/gpio/gpio-mockup.c:	mutex_lock(&chip->lock);
+drivers/gpio/gpio-mockup.c:	mutex_unlock(&chip->lock);
+drivers/gpio/gpio-mockup.c:	mutex_lock(&chip->lock);
+drivers/gpio/gpio-mockup.c:	mutex_unlock(&chip->lock);
+drivers/gpio/gpio-mockup.c:	gc = &chip->gc;
+drivers/gpio/gpio-mockup.c:	sim = &chip->irqsim;
+drivers/gpio/gpio-mockup.c:	mutex_lock(&chip->lock);
+drivers/gpio/gpio-mockup.c:	chip->lines[offset].pull = value;
+drivers/gpio/gpio-mockup.c:	mutex_unlock(&chip->lock);
+drivers/gpio/gpio-mockup.c:	mutex_lock(&chip->lock);
+drivers/gpio/gpio-mockup.c:	chip->lines[offset].dir = GPIO_LINE_DIRECTION_OUT;
+drivers/gpio/gpio-mockup.c:	mutex_unlock(&chip->lock);
+drivers/gpio/gpio-mockup.c:	mutex_lock(&chip->lock);
+drivers/gpio/gpio-mockup.c:	chip->lines[offset].dir = GPIO_LINE_DIRECTION_IN;
+drivers/gpio/gpio-mockup.c:	mutex_unlock(&chip->lock);
+drivers/gpio/gpio-mockup.c:	mutex_lock(&chip->lock);
+drivers/gpio/gpio-mockup.c:	direction = chip->lines[offset].dir;
+drivers/gpio/gpio-mockup.c:	mutex_unlock(&chip->lock);
+drivers/gpio/gpio-mockup.c:	return irq_sim_irqnum(&chip->irqsim, offset);
+drivers/gpio/gpio-mockup.c:	__gpio_mockup_set(chip, offset, chip->lines[offset].pull);
+drivers/gpio/gpio-mockup.c:	gc = &chip->gc;
+drivers/gpio/gpio-mockup.c:	gc = &chip->gc;
+drivers/gpio/gpio-mockup.c:	chip->dbg_dir = debugfs_create_dir(devname, gpio_mockup_dbg_dir);
+drivers/gpio/gpio-mockup.c:		debugfs_create_file(name, 0200, chip->dbg_dir, priv,
+drivers/gpio/gpio-mockup.c:	struct gpio_chip *gc = &chip->gc;
+drivers/gpio/gpio-mockup.c:	rv = device_property_read_string(dev, "chip-name", &name);
+drivers/gpio/gpio-mockup.c:	mutex_init(&chip->lock);
+drivers/gpio/gpio-mockup.c:	gc = &chip->gc;
+drivers/gpio/gpio-mockup.c:	chip->lines = devm_kcalloc(dev, gc->ngpio,
+drivers/gpio/gpio-mockup.c:				   sizeof(*chip->lines), GFP_KERNEL);
+drivers/gpio/gpio-mockup.c:	if (!chip->lines)
+drivers/gpio/gpio-mockup.c:		chip->lines[i].dir = GPIO_LINE_DIRECTION_IN;
+drivers/gpio/gpio-mockup.c:	rv = devm_irq_sim_init(dev, &chip->irqsim, gc->ngpio);
+drivers/gpio/gpio-mockup.c:	rv = devm_gpiochip_add_data(dev, &chip->gc, chip);
+drivers/gpio/gpio-moxtet.c:	if (chip->desc->in_mask & BIT(offset)) {
+drivers/gpio/gpio-moxtet.c:		ret = moxtet_device_read(chip->dev);
+drivers/gpio/gpio-moxtet.c:	} else if (chip->desc->out_mask & BIT(offset)) {
+drivers/gpio/gpio-moxtet.c:		ret = moxtet_device_written(chip->dev);
+drivers/gpio/gpio-moxtet.c:	state = moxtet_device_written(chip->dev);
+drivers/gpio/gpio-moxtet.c:	moxtet_device_write(chip->dev, state);
+drivers/gpio/gpio-moxtet.c:	if (chip->desc->in_mask & BIT(offset))
+drivers/gpio/gpio-moxtet.c:	else if (chip->desc->out_mask & BIT(offset))
+drivers/gpio/gpio-moxtet.c:	if (chip->desc->in_mask & BIT(offset))
+drivers/gpio/gpio-moxtet.c:	else if (chip->desc->out_mask & BIT(offset))
+drivers/gpio/gpio-moxtet.c:	if (chip->desc->out_mask & BIT(offset))
+drivers/gpio/gpio-moxtet.c:	else if (chip->desc->in_mask & BIT(offset))
+drivers/gpio/gpio-moxtet.c:	chip->dev = dev;
+drivers/gpio/gpio-moxtet.c:	chip->gpio_chip.parent = dev;
+drivers/gpio/gpio-moxtet.c:	chip->desc = &descs[id];
+drivers/gpio/gpio-moxtet.c:	chip->gpio_chip.label = dev_name(dev);
+drivers/gpio/gpio-moxtet.c:	chip->gpio_chip.get_direction = moxtet_gpio_get_direction;
+drivers/gpio/gpio-moxtet.c:	chip->gpio_chip.direction_input = moxtet_gpio_direction_input;
+drivers/gpio/gpio-moxtet.c:	chip->gpio_chip.direction_output = moxtet_gpio_direction_output;
+drivers/gpio/gpio-moxtet.c:	chip->gpio_chip.get = moxtet_gpio_get_value;
+drivers/gpio/gpio-moxtet.c:	chip->gpio_chip.set = moxtet_gpio_set_value;
+drivers/gpio/gpio-moxtet.c:	chip->gpio_chip.base = -1;
+drivers/gpio/gpio-moxtet.c:	chip->gpio_chip.ngpio = MOXTET_GPIO_NGPIOS;
+drivers/gpio/gpio-moxtet.c:	chip->gpio_chip.can_sleep = true;
+drivers/gpio/gpio-moxtet.c:	chip->gpio_chip.owner = THIS_MODULE;
+drivers/gpio/gpio-moxtet.c:	return devm_gpiochip_add_data(dev, &chip->gpio_chip, chip);
+drivers/gpio/gpio-mpc5200.c:		chip->shadow_dvo |= 1 << (7 - gpio);
+drivers/gpio/gpio-mpc5200.c:		chip->shadow_dvo &= ~(1 << (7 - gpio));
+drivers/gpio/gpio-mpc5200.c:	out_8(&regs->wkup_dvo, chip->shadow_dvo);
+drivers/gpio/gpio-mpc5200.c:	chip->shadow_ddr &= ~(1 << (7 - gpio));
+drivers/gpio/gpio-mpc5200.c:	out_8(&regs->wkup_ddr, chip->shadow_ddr);
+drivers/gpio/gpio-mpc5200.c:	chip->shadow_gpioe |= 1 << (7 - gpio);
+drivers/gpio/gpio-mpc5200.c:	out_8(&regs->wkup_gpioe, chip->shadow_gpioe);
+drivers/gpio/gpio-mpc5200.c:	chip->shadow_ddr |= 1 << (7 - gpio);
+drivers/gpio/gpio-mpc5200.c:	out_8(&regs->wkup_ddr, chip->shadow_ddr);
+drivers/gpio/gpio-mpc5200.c:	chip->shadow_gpioe |= 1 << (7 - gpio);
+drivers/gpio/gpio-mpc5200.c:	out_8(&regs->wkup_gpioe, chip->shadow_gpioe);
+drivers/gpio/gpio-mpc5200.c:	gc = &chip->mmchip.gc;
+drivers/gpio/gpio-mpc5200.c:	ret = of_mm_gpiochip_add_data(ofdev->dev.of_node, &chip->mmchip, chip);
+drivers/gpio/gpio-mpc5200.c:	regs = chip->mmchip.regs;
+drivers/gpio/gpio-mpc5200.c:	chip->shadow_gpioe = in_8(&regs->wkup_gpioe);
+drivers/gpio/gpio-mpc5200.c:	chip->shadow_ddr = in_8(&regs->wkup_ddr);
+drivers/gpio/gpio-mpc5200.c:	chip->shadow_dvo = in_8(&regs->wkup_dvo);
+drivers/gpio/gpio-mpc5200.c:	of_mm_gpiochip_remove(&chip->mmchip);
+drivers/gpio/gpio-mpc5200.c:		chip->shadow_dvo |= 1 << (31 - gpio);
+drivers/gpio/gpio-mpc5200.c:		chip->shadow_dvo &= ~(1 << (31 - gpio));
+drivers/gpio/gpio-mpc5200.c:	out_be32(&regs->simple_dvo, chip->shadow_dvo);
+drivers/gpio/gpio-mpc5200.c:	chip->shadow_ddr &= ~(1 << (31 - gpio));
+drivers/gpio/gpio-mpc5200.c:	out_be32(&regs->simple_ddr, chip->shadow_ddr);
+drivers/gpio/gpio-mpc5200.c:	chip->shadow_gpioe |= 1 << (31 - gpio);
+drivers/gpio/gpio-mpc5200.c:	out_be32(&regs->simple_gpioe, chip->shadow_gpioe);
+drivers/gpio/gpio-mpc5200.c:	chip->shadow_ddr |= 1 << (31 - gpio);
+drivers/gpio/gpio-mpc5200.c:	out_be32(&regs->simple_ddr, chip->shadow_ddr);
+drivers/gpio/gpio-mpc5200.c:	chip->shadow_gpioe |= 1 << (31 - gpio);
+drivers/gpio/gpio-mpc5200.c:	out_be32(&regs->simple_gpioe, chip->shadow_gpioe);
+drivers/gpio/gpio-mpc5200.c:	gc = &chip->mmchip.gc;
+drivers/gpio/gpio-mpc5200.c:	ret = of_mm_gpiochip_add_data(ofdev->dev.of_node, &chip->mmchip, chip);
+drivers/gpio/gpio-mpc5200.c:	regs = chip->mmchip.regs;
+drivers/gpio/gpio-mpc5200.c:	chip->shadow_gpioe = in_be32(&regs->simple_gpioe);
+drivers/gpio/gpio-mpc5200.c:	chip->shadow_ddr = in_be32(&regs->simple_ddr);
+drivers/gpio/gpio-mpc5200.c:	chip->shadow_dvo = in_be32(&regs->simple_dvo);
+drivers/gpio/gpio-msic.c:	chip->irq_eoi(data);
+drivers/gpio/gpio-mvebu.c:	switch (mvchip->soc_variant) {
+drivers/gpio/gpio-mvebu.c:		*map = mvchip->regs;
+drivers/gpio/gpio-mvebu.c:		*offset = GPIO_EDGE_CAUSE_OFF + mvchip->offset;
+drivers/gpio/gpio-mvebu.c:		*map = mvchip->percpu_regs;
+drivers/gpio/gpio-mvebu.c:	switch (mvchip->soc_variant) {
+drivers/gpio/gpio-mvebu.c:		*map = mvchip->regs;
+drivers/gpio/gpio-mvebu.c:		*offset = GPIO_EDGE_MASK_OFF + mvchip->offset;
+drivers/gpio/gpio-mvebu.c:		*map = mvchip->regs;
+drivers/gpio/gpio-mvebu.c:		*map = mvchip->percpu_regs;
+drivers/gpio/gpio-mvebu.c:	switch (mvchip->soc_variant) {
+drivers/gpio/gpio-mvebu.c:		*map = mvchip->regs;
+drivers/gpio/gpio-mvebu.c:		*offset = GPIO_LEVEL_MASK_OFF + mvchip->offset;
+drivers/gpio/gpio-mvebu.c:		*map = mvchip->regs;
+drivers/gpio/gpio-mvebu.c:		*map = mvchip->percpu_regs;
+drivers/gpio/gpio-mvebu.c:	regmap_update_bits(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
+drivers/gpio/gpio-mvebu.c:	regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
+drivers/gpio/gpio-mvebu.c:		regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset,
+drivers/gpio/gpio-mvebu.c:		regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
+drivers/gpio/gpio-mvebu.c:		regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &u);
+drivers/gpio/gpio-mvebu.c:	regmap_update_bits(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
+drivers/gpio/gpio-mvebu.c:	ret = pinctrl_gpio_direction_input(chip->base + pin);
+drivers/gpio/gpio-mvebu.c:	regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
+drivers/gpio/gpio-mvebu.c:	ret = pinctrl_gpio_direction_output(chip->base + pin);
+drivers/gpio/gpio-mvebu.c:	regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
+drivers/gpio/gpio-mvebu.c:	regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
+drivers/gpio/gpio-mvebu.c:	return irq_create_mapping(mvchip->domain, pin);
+drivers/gpio/gpio-mvebu.c:	regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
+drivers/gpio/gpio-mvebu.c:		regmap_update_bits(mvchip->regs,
+drivers/gpio/gpio-mvebu.c:				   GPIO_IN_POL_OFF + mvchip->offset,
+drivers/gpio/gpio-mvebu.c:		regmap_update_bits(mvchip->regs,
+drivers/gpio/gpio-mvebu.c:				   GPIO_IN_POL_OFF + mvchip->offset,
+drivers/gpio/gpio-mvebu.c:		regmap_read(mvchip->regs,
+drivers/gpio/gpio-mvebu.c:			    GPIO_IN_POL_OFF + mvchip->offset, &in_pol);
+drivers/gpio/gpio-mvebu.c:		regmap_read(mvchip->regs,
+drivers/gpio/gpio-mvebu.c:			    GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
+drivers/gpio/gpio-mvebu.c:		regmap_update_bits(mvchip->regs,
+drivers/gpio/gpio-mvebu.c:				   GPIO_IN_POL_OFF + mvchip->offset,
+drivers/gpio/gpio-mvebu.c:	regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
+drivers/gpio/gpio-mvebu.c:	for (i = 0; i < mvchip->chip.ngpio; i++) {
+drivers/gpio/gpio-mvebu.c:		irq = irq_find_mapping(mvchip->domain, i);
+drivers/gpio/gpio-mvebu.c:			regmap_read(mvchip->regs,
+drivers/gpio/gpio-mvebu.c:				    GPIO_IN_POL_OFF + mvchip->offset,
+drivers/gpio/gpio-mvebu.c:			regmap_write(mvchip->regs,
+drivers/gpio/gpio-mvebu.c:				     GPIO_IN_POL_OFF + mvchip->offset,
+drivers/gpio/gpio-mvebu.c:		desc = gpiochip_request_own_desc(&mvchip->chip,
+drivers/gpio/gpio-mvebu.c:	regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &u);
+drivers/gpio/gpio-mvebu.c:		mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1);
+drivers/gpio/gpio-mvebu.c:		mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0);
+drivers/gpio/gpio-mvebu.c:	struct mvebu_pwm *mvpwm = mvchip->mvpwm;
+drivers/gpio/gpio-mvebu.c:	regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
+drivers/gpio/gpio-mvebu.c:	struct mvebu_pwm *mvpwm = mvchip->mvpwm;
+drivers/gpio/gpio-mvebu.c:	regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
+drivers/gpio/gpio-mvebu.c:	if (!of_device_is_compatible(mvchip->chip.of_node,
+drivers/gpio/gpio-mvebu.c:	if (IS_ERR(mvchip->clk))
+drivers/gpio/gpio-mvebu.c:		return PTR_ERR(mvchip->clk);
+drivers/gpio/gpio-mvebu.c:	regmap_write(mvchip->regs,
+drivers/gpio/gpio-mvebu.c:		     GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, set);
+drivers/gpio/gpio-mvebu.c:	mvchip->mvpwm = mvpwm;
+drivers/gpio/gpio-mvebu.c:	mvpwm->clk_rate = clk_get_rate(mvchip->clk);
+drivers/gpio/gpio-mvebu.c:	mvpwm->chip.npwm = mvchip->chip.ngpio;
+drivers/gpio/gpio-mvebu.c:	 * mvpwm->chip.base to a fixed point like mvchip->chip.base.
+drivers/gpio/gpio-mvebu.c:	regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &out);
+drivers/gpio/gpio-mvebu.c:	regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &io_conf);
+drivers/gpio/gpio-mvebu.c:	regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &blink);
+drivers/gpio/gpio-mvebu.c:	regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, &in_pol);
+drivers/gpio/gpio-mvebu.c:	regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
+drivers/gpio/gpio-mvebu.c:	for (i = 0; i < chip->ngpio; i++) {
+drivers/gpio/gpio-mvebu.c:		seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label);
+drivers/gpio/gpio-mvebu.c:	regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
+drivers/gpio/gpio-mvebu.c:		    &mvchip->out_reg);
+drivers/gpio/gpio-mvebu.c:	regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
+drivers/gpio/gpio-mvebu.c:		    &mvchip->io_conf_reg);
+drivers/gpio/gpio-mvebu.c:	regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
+drivers/gpio/gpio-mvebu.c:		    &mvchip->blink_en_reg);
+drivers/gpio/gpio-mvebu.c:	regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
+drivers/gpio/gpio-mvebu.c:		    &mvchip->in_pol_reg);
+drivers/gpio/gpio-mvebu.c:	switch (mvchip->soc_variant) {
+drivers/gpio/gpio-mvebu.c:		regmap_read(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset,
+drivers/gpio/gpio-mvebu.c:			    &mvchip->edge_mask_regs[0]);
+drivers/gpio/gpio-mvebu.c:		regmap_read(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset,
+drivers/gpio/gpio-mvebu.c:			    &mvchip->level_mask_regs[0]);
+drivers/gpio/gpio-mvebu.c:			regmap_read(mvchip->regs,
+drivers/gpio/gpio-mvebu.c:				    &mvchip->edge_mask_regs[i]);
+drivers/gpio/gpio-mvebu.c:			regmap_read(mvchip->regs,
+drivers/gpio/gpio-mvebu.c:				    &mvchip->level_mask_regs[i]);
+drivers/gpio/gpio-mvebu.c:			regmap_read(mvchip->regs,
+drivers/gpio/gpio-mvebu.c:				    &mvchip->edge_mask_regs[i]);
+drivers/gpio/gpio-mvebu.c:			regmap_read(mvchip->regs,
+drivers/gpio/gpio-mvebu.c:				    &mvchip->level_mask_regs[i]);
+drivers/gpio/gpio-mvebu.c:	regmap_write(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
+drivers/gpio/gpio-mvebu.c:		     mvchip->out_reg);
+drivers/gpio/gpio-mvebu.c:	regmap_write(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
+drivers/gpio/gpio-mvebu.c:		     mvchip->io_conf_reg);
+drivers/gpio/gpio-mvebu.c:	regmap_write(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
+drivers/gpio/gpio-mvebu.c:		     mvchip->blink_en_reg);
+drivers/gpio/gpio-mvebu.c:	regmap_write(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
+drivers/gpio/gpio-mvebu.c:		     mvchip->in_pol_reg);
+drivers/gpio/gpio-mvebu.c:	switch (mvchip->soc_variant) {
+drivers/gpio/gpio-mvebu.c:		regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset,
+drivers/gpio/gpio-mvebu.c:			     mvchip->edge_mask_regs[0]);
+drivers/gpio/gpio-mvebu.c:		regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset,
+drivers/gpio/gpio-mvebu.c:			     mvchip->level_mask_regs[0]);
+drivers/gpio/gpio-mvebu.c:			regmap_write(mvchip->regs,
+drivers/gpio/gpio-mvebu.c:				     mvchip->edge_mask_regs[i]);
+drivers/gpio/gpio-mvebu.c:			regmap_write(mvchip->regs,
+drivers/gpio/gpio-mvebu.c:				     mvchip->level_mask_regs[i]);
+drivers/gpio/gpio-mvebu.c:			regmap_write(mvchip->regs,
+drivers/gpio/gpio-mvebu.c:				     mvchip->edge_mask_regs[i]);
+drivers/gpio/gpio-mvebu.c:			regmap_write(mvchip->regs,
+drivers/gpio/gpio-mvebu.c:				     mvchip->level_mask_regs[i]);
+drivers/gpio/gpio-mvebu.c:	mvchip->regs = devm_regmap_init_mmio(&pdev->dev, base,
+drivers/gpio/gpio-mvebu.c:	if (IS_ERR(mvchip->regs))
+drivers/gpio/gpio-mvebu.c:		return PTR_ERR(mvchip->regs);
+drivers/gpio/gpio-mvebu.c:	mvchip->offset = 0;
+drivers/gpio/gpio-mvebu.c:	if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
+drivers/gpio/gpio-mvebu.c:		mvchip->percpu_regs =
+drivers/gpio/gpio-mvebu.c:		if (IS_ERR(mvchip->percpu_regs))
+drivers/gpio/gpio-mvebu.c:			return PTR_ERR(mvchip->percpu_regs);
+drivers/gpio/gpio-mvebu.c:	mvchip->regs = syscon_node_to_regmap(pdev->dev.parent->of_node);
+drivers/gpio/gpio-mvebu.c:	if (IS_ERR(mvchip->regs))
+drivers/gpio/gpio-mvebu.c:		return PTR_ERR(mvchip->regs);
+drivers/gpio/gpio-mvebu.c:	if (of_property_read_u32(pdev->dev.of_node, "offset", &mvchip->offset))
+drivers/gpio/gpio-mvebu.c:	mvchip->clk = devm_clk_get(&pdev->dev, NULL);
+drivers/gpio/gpio-mvebu.c:	if (!IS_ERR(mvchip->clk))
+drivers/gpio/gpio-mvebu.c:		clk_prepare_enable(mvchip->clk);
+drivers/gpio/gpio-mvebu.c:	mvchip->soc_variant = soc_variant;
+drivers/gpio/gpio-mvebu.c:	mvchip->chip.label = dev_name(&pdev->dev);
+drivers/gpio/gpio-mvebu.c:	mvchip->chip.parent = &pdev->dev;
+drivers/gpio/gpio-mvebu.c:	mvchip->chip.request = gpiochip_generic_request;
+drivers/gpio/gpio-mvebu.c:	mvchip->chip.free = gpiochip_generic_free;
+drivers/gpio/gpio-mvebu.c:	mvchip->chip.get_direction = mvebu_gpio_get_direction;
+drivers/gpio/gpio-mvebu.c:	mvchip->chip.direction_input = mvebu_gpio_direction_input;
+drivers/gpio/gpio-mvebu.c:	mvchip->chip.get = mvebu_gpio_get;
+drivers/gpio/gpio-mvebu.c:	mvchip->chip.direction_output = mvebu_gpio_direction_output;
+drivers/gpio/gpio-mvebu.c:	mvchip->chip.set = mvebu_gpio_set;
+drivers/gpio/gpio-mvebu.c:		mvchip->chip.to_irq = mvebu_gpio_to_irq;
+drivers/gpio/gpio-mvebu.c:	mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK;
+drivers/gpio/gpio-mvebu.c:	mvchip->chip.ngpio = ngpios;
+drivers/gpio/gpio-mvebu.c:	mvchip->chip.can_sleep = false;
+drivers/gpio/gpio-mvebu.c:	mvchip->chip.of_node = np;
+drivers/gpio/gpio-mvebu.c:	mvchip->chip.dbg_show = mvebu_gpio_dbg_show;
+drivers/gpio/gpio-mvebu.c:		regmap_write(mvchip->regs,
+drivers/gpio/gpio-mvebu.c:			     GPIO_EDGE_CAUSE_OFF + mvchip->offset, 0);
+drivers/gpio/gpio-mvebu.c:		regmap_write(mvchip->regs,
+drivers/gpio/gpio-mvebu.c:			     GPIO_EDGE_MASK_OFF + mvchip->offset, 0);
+drivers/gpio/gpio-mvebu.c:		regmap_write(mvchip->regs,
+drivers/gpio/gpio-mvebu.c:			     GPIO_LEVEL_MASK_OFF + mvchip->offset, 0);
+drivers/gpio/gpio-mvebu.c:		regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
+drivers/gpio/gpio-mvebu.c:			regmap_write(mvchip->regs,
+drivers/gpio/gpio-mvebu.c:			regmap_write(mvchip->regs,
+drivers/gpio/gpio-mvebu.c:		regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
+drivers/gpio/gpio-mvebu.c:		regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF, 0);
+drivers/gpio/gpio-mvebu.c:		regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF, 0);
+drivers/gpio/gpio-mvebu.c:			regmap_write(mvchip->percpu_regs,
+drivers/gpio/gpio-mvebu.c:			regmap_write(mvchip->percpu_regs,
+drivers/gpio/gpio-mvebu.c:			regmap_write(mvchip->percpu_regs,
+drivers/gpio/gpio-mvebu.c:	devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip);
+drivers/gpio/gpio-mvebu.c:	mvchip->domain =
+drivers/gpio/gpio-mvebu.c:	if (!mvchip->domain) {
+drivers/gpio/gpio-mvebu.c:			mvchip->chip.label);
+drivers/gpio/gpio-mvebu.c:	    mvchip->domain, ngpios, 2, np->name, handle_level_irq,
+drivers/gpio/gpio-mvebu.c:			mvchip->chip.label);
+drivers/gpio/gpio-mvebu.c:	gc = irq_get_domain_generic_chip(mvchip->domain, 0);
+drivers/gpio/gpio-mvebu.c:	ct->chip.name = mvchip->chip.label;
+drivers/gpio/gpio-mvebu.c:	ct->chip.name = mvchip->chip.label;
+drivers/gpio/gpio-mvebu.c:	irq_domain_remove(mvchip->domain);
+drivers/gpio/gpio-mxs.c:	desc->irq_data.chip->irq_ack(&desc->irq_data);
+drivers/gpio/gpio-octeon.c:	chip->label = "octeon-gpio";
+drivers/gpio/gpio-octeon.c:	chip->parent = &pdev->dev;
+drivers/gpio/gpio-octeon.c:	chip->owner = THIS_MODULE;
+drivers/gpio/gpio-octeon.c:	chip->base = 0;
+drivers/gpio/gpio-octeon.c:	chip->can_sleep = false;
+drivers/gpio/gpio-octeon.c:	chip->ngpio = 20;
+drivers/gpio/gpio-octeon.c:	chip->direction_input = octeon_gpio_dir_in;
+drivers/gpio/gpio-octeon.c:	chip->get = octeon_gpio_get;
+drivers/gpio/gpio-octeon.c:	chip->direction_output = octeon_gpio_dir_out;
+drivers/gpio/gpio-octeon.c:	chip->set = octeon_gpio_set;
+drivers/gpio/gpio-omap.c:	pm_runtime_get_sync(chip->parent);
+drivers/gpio/gpio-omap.c:	pm_runtime_put(chip->parent);
+drivers/gpio/gpio-omap.c:		dev_info(chip->parent,
+drivers/gpio/gpio-pca953x.c:#define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ)
+drivers/gpio/gpio-pca953x.c:	return fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
+drivers/gpio/gpio-pca953x.c:		if (!(chip->driver_data & PCA_PCAL))
+drivers/gpio/gpio-pca953x.c:	if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) {
+drivers/gpio/gpio-pca953x.c:	if (chip->driver_data & PCA_PCAL) {
+drivers/gpio/gpio-pca953x.c:	if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) {
+drivers/gpio/gpio-pca953x.c:	if (chip->driver_data & PCA_PCAL)
+drivers/gpio/gpio-pca953x.c:	if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE)
+drivers/gpio/gpio-pca953x.c:	if (chip->driver_data & PCA_PCAL)
+drivers/gpio/gpio-pca953x.c:	if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE)
+drivers/gpio/gpio-pca953x.c:	ret = regmap_bulk_write(chip->regmap, regaddr, value, NBANK(chip));
+drivers/gpio/gpio-pca953x.c:		dev_err(&chip->client->dev, "failed writing register\n");
+drivers/gpio/gpio-pca953x.c:	ret = regmap_bulk_read(chip->regmap, regaddr, value, NBANK(chip));
+drivers/gpio/gpio-pca953x.c:		dev_err(&chip->client->dev, "failed reading register\n");
+drivers/gpio/gpio-pca953x.c:	u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off,
+drivers/gpio/gpio-pca953x.c:	mutex_lock(&chip->i2c_lock);
+drivers/gpio/gpio-pca953x.c:	ret = regmap_write_bits(chip->regmap, dirreg, bit, bit);
+drivers/gpio/gpio-pca953x.c:	mutex_unlock(&chip->i2c_lock);
+drivers/gpio/gpio-pca953x.c:	u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off,
+drivers/gpio/gpio-pca953x.c:	u8 outreg = pca953x_recalc_addr(chip, chip->regs->output, off,
+drivers/gpio/gpio-pca953x.c:	mutex_lock(&chip->i2c_lock);
+drivers/gpio/gpio-pca953x.c:	ret = regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
+drivers/gpio/gpio-pca953x.c:	ret = regmap_write_bits(chip->regmap, dirreg, bit, 0);
+drivers/gpio/gpio-pca953x.c:	mutex_unlock(&chip->i2c_lock);
+drivers/gpio/gpio-pca953x.c:	u8 inreg = pca953x_recalc_addr(chip, chip->regs->input, off,
+drivers/gpio/gpio-pca953x.c:	mutex_lock(&chip->i2c_lock);
+drivers/gpio/gpio-pca953x.c:	ret = regmap_read(chip->regmap, inreg, &reg_val);
+drivers/gpio/gpio-pca953x.c:	mutex_unlock(&chip->i2c_lock);
+drivers/gpio/gpio-pca953x.c:	u8 outreg = pca953x_recalc_addr(chip, chip->regs->output, off,
+drivers/gpio/gpio-pca953x.c:	mutex_lock(&chip->i2c_lock);
+drivers/gpio/gpio-pca953x.c:	regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
+drivers/gpio/gpio-pca953x.c:	mutex_unlock(&chip->i2c_lock);
+drivers/gpio/gpio-pca953x.c:	u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off,
+drivers/gpio/gpio-pca953x.c:	mutex_lock(&chip->i2c_lock);
+drivers/gpio/gpio-pca953x.c:	ret = regmap_read(chip->regmap, dirreg, &reg_val);
+drivers/gpio/gpio-pca953x.c:	mutex_unlock(&chip->i2c_lock);
+drivers/gpio/gpio-pca953x.c:	mutex_lock(&chip->i2c_lock);
+drivers/gpio/gpio-pca953x.c:	ret = pca953x_read_regs(chip, chip->regs->output, reg_val);
+drivers/gpio/gpio-pca953x.c:	pca953x_write_regs(chip, chip->regs->output, reg_val);
+drivers/gpio/gpio-pca953x.c:	mutex_unlock(&chip->i2c_lock);
+drivers/gpio/gpio-pca953x.c:	if (!(chip->driver_data & PCA_PCAL))
+drivers/gpio/gpio-pca953x.c:	mutex_lock(&chip->i2c_lock);
+drivers/gpio/gpio-pca953x.c:	ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, 0);
+drivers/gpio/gpio-pca953x.c:		ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, bit);
+drivers/gpio/gpio-pca953x.c:		ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, 0);
+drivers/gpio/gpio-pca953x.c:	ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, bit);
+drivers/gpio/gpio-pca953x.c:	mutex_unlock(&chip->i2c_lock);
+drivers/gpio/gpio-pca953x.c:	gc = &chip->gpio_chip;
+drivers/gpio/gpio-pca953x.c:	gc->base = chip->gpio_start;
+drivers/gpio/gpio-pca953x.c:	gc->label = dev_name(&chip->client->dev);
+drivers/gpio/gpio-pca953x.c:	gc->parent = &chip->client->dev;
+drivers/gpio/gpio-pca953x.c:	gc->names = chip->names;
+drivers/gpio/gpio-pca953x.c:	clear_bit(hwirq, chip->irq_mask);
+drivers/gpio/gpio-pca953x.c:	set_bit(hwirq, chip->irq_mask);
+drivers/gpio/gpio-pca953x.c:		atomic_inc(&chip->wakeup_path);
+drivers/gpio/gpio-pca953x.c:		atomic_dec(&chip->wakeup_path);
+drivers/gpio/gpio-pca953x.c:	return irq_set_irq_wake(chip->client->irq, on);
+drivers/gpio/gpio-pca953x.c:	mutex_lock(&chip->irq_lock);
+drivers/gpio/gpio-pca953x.c:	pca953x_read_regs(chip, chip->regs->direction, reg_direction);
+drivers/gpio/gpio-pca953x.c:	if (chip->driver_data & PCA_PCAL) {
+drivers/gpio/gpio-pca953x.c:		pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask);
+drivers/gpio/gpio-pca953x.c:		bitmap_complement(irq_mask, chip->irq_mask, gc->ngpio);
+drivers/gpio/gpio-pca953x.c:	bitmap_or(irq_mask, chip->irq_trig_fall, chip->irq_trig_raise, gc->ngpio);
+drivers/gpio/gpio-pca953x.c:		pca953x_gpio_direction_input(&chip->gpio_chip, level);
+drivers/gpio/gpio-pca953x.c:	mutex_unlock(&chip->irq_lock);
+drivers/gpio/gpio-pca953x.c:		dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
+drivers/gpio/gpio-pca953x.c:	assign_bit(hwirq, chip->irq_trig_fall, type & IRQ_TYPE_EDGE_FALLING);
+drivers/gpio/gpio-pca953x.c:	assign_bit(hwirq, chip->irq_trig_raise, type & IRQ_TYPE_EDGE_RISING);
+drivers/gpio/gpio-pca953x.c:	clear_bit(hwirq, chip->irq_trig_raise);
+drivers/gpio/gpio-pca953x.c:	clear_bit(hwirq, chip->irq_trig_fall);
+drivers/gpio/gpio-pca953x.c:	struct gpio_chip *gc = &chip->gpio_chip;
+drivers/gpio/gpio-pca953x.c:	if (chip->driver_data & PCA_PCAL) {
+drivers/gpio/gpio-pca953x.c:		ret = pca953x_read_regs(chip, chip->regs->input, cur_stat);
+drivers/gpio/gpio-pca953x.c:		bitmap_replace(new_stat, chip->irq_trig_fall, chip->irq_trig_raise, cur_stat, gc->ngpio);
+drivers/gpio/gpio-pca953x.c:	ret = pca953x_read_regs(chip, chip->regs->input, cur_stat);
+drivers/gpio/gpio-pca953x.c:	pca953x_read_regs(chip, chip->regs->direction, reg_direction);
+drivers/gpio/gpio-pca953x.c:	bitmap_copy(old_stat, chip->irq_stat, gc->ngpio);
+drivers/gpio/gpio-pca953x.c:	bitmap_and(trigger, cur_stat, chip->irq_mask, gc->ngpio);
+drivers/gpio/gpio-pca953x.c:	bitmap_copy(chip->irq_stat, new_stat, gc->ngpio);
+drivers/gpio/gpio-pca953x.c:	bitmap_and(cur_stat, chip->irq_trig_fall, old_stat, gc->ngpio);
+drivers/gpio/gpio-pca953x.c:	bitmap_and(old_stat, chip->irq_trig_raise, new_stat, gc->ngpio);
+drivers/gpio/gpio-pca953x.c:	struct gpio_chip *gc = &chip->gpio_chip;
+drivers/gpio/gpio-pca953x.c:	struct i2c_client *client = chip->client;
+drivers/gpio/gpio-pca953x.c:	struct irq_chip *irq_chip = &chip->irq_chip;
+drivers/gpio/gpio-pca953x.c:	if (!(chip->driver_data & PCA_INT))
+drivers/gpio/gpio-pca953x.c:	ret = pca953x_read_regs(chip, chip->regs->input, irq_stat);
+drivers/gpio/gpio-pca953x.c:	pca953x_read_regs(chip, chip->regs->direction, reg_direction);
+drivers/gpio/gpio-pca953x.c:	bitmap_and(chip->irq_stat, irq_stat, reg_direction, chip->gpio_chip.ngpio);
+drivers/gpio/gpio-pca953x.c:	mutex_init(&chip->irq_lock);
+drivers/gpio/gpio-pca953x.c:	irq_chip->name = dev_name(&chip->client->dev);
+drivers/gpio/gpio-pca953x.c:	irq_chip->irq_mask = pca953x_irq_mask;
+drivers/gpio/gpio-pca953x.c:	irq_chip->irq_unmask = pca953x_irq_unmask;
+drivers/gpio/gpio-pca953x.c:	irq_chip->irq_set_wake = pca953x_irq_set_wake;
+drivers/gpio/gpio-pca953x.c:	irq_chip->irq_bus_lock = pca953x_irq_bus_lock;
+drivers/gpio/gpio-pca953x.c:	irq_chip->irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock;
+drivers/gpio/gpio-pca953x.c:	irq_chip->irq_set_type = pca953x_irq_set_type;
+drivers/gpio/gpio-pca953x.c:	irq_chip->irq_shutdown = pca953x_irq_shutdown;
+drivers/gpio/gpio-pca953x.c:	ret = gpiochip_irqchip_add_nested(&chip->gpio_chip, irq_chip,
+drivers/gpio/gpio-pca953x.c:	gpiochip_set_nested_irqchip(&chip->gpio_chip, irq_chip, client->irq);
+drivers/gpio/gpio-pca953x.c:	struct i2c_client *client = chip->client;
+drivers/gpio/gpio-pca953x.c:	if (client->irq && irq_base != -1 && (chip->driver_data & PCA_INT))
+drivers/gpio/gpio-pca953x.c:	ret = regcache_sync_region(chip->regmap, chip->regs->output,
+drivers/gpio/gpio-pca953x.c:				   chip->regs->output + NBANK(chip));
+drivers/gpio/gpio-pca953x.c:	ret = regcache_sync_region(chip->regmap, chip->regs->direction,
+drivers/gpio/gpio-pca953x.c:				   chip->regs->direction + NBANK(chip));
+drivers/gpio/gpio-pca953x.c:	ret = pca953x_write_regs(chip, chip->regs->invert, val);
+drivers/gpio/gpio-pca953x.c:		chip->gpio_start = pdata->gpio_base;
+drivers/gpio/gpio-pca953x.c:		chip->names = pdata->names;
+drivers/gpio/gpio-pca953x.c:		chip->gpio_start = -1;
+drivers/gpio/gpio-pca953x.c:	chip->client = client;
+drivers/gpio/gpio-pca953x.c:	chip->regulator = reg;
+drivers/gpio/gpio-pca953x.c:		chip->driver_data = i2c_id->driver_data;
+drivers/gpio/gpio-pca953x.c:		chip->driver_data = (uintptr_t)match;
+drivers/gpio/gpio-pca953x.c:	chip->regmap = devm_regmap_init_i2c(client, &pca953x_i2c_regmap);
+drivers/gpio/gpio-pca953x.c:	if (IS_ERR(chip->regmap)) {
+drivers/gpio/gpio-pca953x.c:		ret = PTR_ERR(chip->regmap);
+drivers/gpio/gpio-pca953x.c:	regcache_mark_dirty(chip->regmap);
+drivers/gpio/gpio-pca953x.c:	mutex_init(&chip->i2c_lock);
+drivers/gpio/gpio-pca953x.c:	 * subclass for chip->i2c_lock.
+drivers/gpio/gpio-pca953x.c:	lockdep_set_subclass(&chip->i2c_lock,
+drivers/gpio/gpio-pca953x.c:	pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK);
+drivers/gpio/gpio-pca953x.c:	if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) {
+drivers/gpio/gpio-pca953x.c:		chip->regs = &pca953x_regs;
+drivers/gpio/gpio-pca953x.c:		chip->regs = &pca957x_regs;
+drivers/gpio/gpio-pca953x.c:	ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip);
+drivers/gpio/gpio-pca953x.c:		ret = pdata->setup(client, chip->gpio_chip.base,
+drivers/gpio/gpio-pca953x.c:				   chip->gpio_chip.ngpio, pdata->context);
+drivers/gpio/gpio-pca953x.c:	regulator_disable(chip->regulator);
+drivers/gpio/gpio-pca953x.c:		ret = pdata->teardown(client, chip->gpio_chip.base,
+drivers/gpio/gpio-pca953x.c:				      chip->gpio_chip.ngpio, pdata->context);
+drivers/gpio/gpio-pca953x.c:	regulator_disable(chip->regulator);
+drivers/gpio/gpio-pca953x.c:	ret = regcache_sync_region(chip->regmap, chip->regs->direction,
+drivers/gpio/gpio-pca953x.c:				   chip->regs->direction + NBANK(chip));
+drivers/gpio/gpio-pca953x.c:	ret = regcache_sync_region(chip->regmap, chip->regs->output,
+drivers/gpio/gpio-pca953x.c:				   chip->regs->output + NBANK(chip));
+drivers/gpio/gpio-pca953x.c:	if (chip->driver_data & PCA_PCAL) {
+drivers/gpio/gpio-pca953x.c:		ret = regcache_sync_region(chip->regmap, PCAL953X_IN_LATCH,
+drivers/gpio/gpio-pca953x.c:		ret = regcache_sync_region(chip->regmap, PCAL953X_INT_MASK,
+drivers/gpio/gpio-pca953x.c:	regcache_cache_only(chip->regmap, true);
+drivers/gpio/gpio-pca953x.c:	if (atomic_read(&chip->wakeup_path))
+drivers/gpio/gpio-pca953x.c:		regulator_disable(chip->regulator);
+drivers/gpio/gpio-pca953x.c:	if (!atomic_read(&chip->wakeup_path)) {
+drivers/gpio/gpio-pca953x.c:		ret = regulator_enable(chip->regulator);
+drivers/gpio/gpio-pca953x.c:	regcache_cache_only(chip->regmap, false);
+drivers/gpio/gpio-pca953x.c:	regcache_mark_dirty(chip->regmap);
+drivers/gpio/gpio-pca953x.c:	ret = regcache_sync(chip->regmap);
+drivers/gpio/gpio-pch.c:	spin_lock_irqsave(&chip->spinlock, flags);
+drivers/gpio/gpio-pch.c:	reg_val = ioread32(&chip->reg->po);
+drivers/gpio/gpio-pch.c:	iowrite32(reg_val, &chip->reg->po);
+drivers/gpio/gpio-pch.c:	spin_unlock_irqrestore(&chip->spinlock, flags);
+drivers/gpio/gpio-pch.c:	return (ioread32(&chip->reg->pi) >> nr) & 1;
+drivers/gpio/gpio-pch.c:	spin_lock_irqsave(&chip->spinlock, flags);
+drivers/gpio/gpio-pch.c:	reg_val = ioread32(&chip->reg->po);
+drivers/gpio/gpio-pch.c:	iowrite32(reg_val, &chip->reg->po);
+drivers/gpio/gpio-pch.c:	pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
+drivers/gpio/gpio-pch.c:	iowrite32(pm, &chip->reg->pm);
+drivers/gpio/gpio-pch.c:	spin_unlock_irqrestore(&chip->spinlock, flags);
+drivers/gpio/gpio-pch.c:	spin_lock_irqsave(&chip->spinlock, flags);
+drivers/gpio/gpio-pch.c:	pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
+drivers/gpio/gpio-pch.c:	iowrite32(pm, &chip->reg->pm);
+drivers/gpio/gpio-pch.c:	spin_unlock_irqrestore(&chip->spinlock, flags);
+drivers/gpio/gpio-pch.c:	chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien);
+drivers/gpio/gpio-pch.c:	chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask);
+drivers/gpio/gpio-pch.c:	chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po);
+drivers/gpio/gpio-pch.c:	chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm);
+drivers/gpio/gpio-pch.c:	chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0);
+drivers/gpio/gpio-pch.c:	if (chip->ioh == INTEL_EG20T_PCH)
+drivers/gpio/gpio-pch.c:		chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1);
+drivers/gpio/gpio-pch.c:	if (chip->ioh == OKISEMI_ML7223n_IOH)
+drivers/gpio/gpio-pch.c:		chip->pch_gpio_reg.gpio_use_sel_reg = ioread32(&chip->reg->gpio_use_sel);
+drivers/gpio/gpio-pch.c:	iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien);
+drivers/gpio/gpio-pch.c:	iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask);
+drivers/gpio/gpio-pch.c:	iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po);
+drivers/gpio/gpio-pch.c:	iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm);
+drivers/gpio/gpio-pch.c:	iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0);
+drivers/gpio/gpio-pch.c:	if (chip->ioh == INTEL_EG20T_PCH)
+drivers/gpio/gpio-pch.c:		iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1);
+drivers/gpio/gpio-pch.c:	if (chip->ioh == OKISEMI_ML7223n_IOH)
+drivers/gpio/gpio-pch.c:		iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg, &chip->reg->gpio_use_sel);
+drivers/gpio/gpio-pch.c:	return chip->irq_base + offset;
+drivers/gpio/gpio-pch.c:	struct gpio_chip *gpio = &chip->gpio;
+drivers/gpio/gpio-pch.c:	gpio->label = dev_name(chip->dev);
+drivers/gpio/gpio-pch.c:	gpio->parent = chip->dev;
+drivers/gpio/gpio-pch.c:	gpio->ngpio = gpio_pins[chip->ioh];
+drivers/gpio/gpio-pch.c:	ch = irq - chip->irq_base;
+drivers/gpio/gpio-pch.c:	if (irq <= chip->irq_base + 7) {
+drivers/gpio/gpio-pch.c:		im_reg = &chip->reg->im0;
+drivers/gpio/gpio-pch.c:		im_reg = &chip->reg->im1;
+drivers/gpio/gpio-pch.c:	dev_dbg(chip->dev, "irq=%d type=%d ch=%d pos=%d\n", irq, type, ch, im_pos);
+drivers/gpio/gpio-pch.c:	spin_lock_irqsave(&chip->spinlock, flags);
+drivers/gpio/gpio-pch.c:	spin_unlock_irqrestore(&chip->spinlock, flags);
+drivers/gpio/gpio-pch.c:	iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imaskclr);
+drivers/gpio/gpio-pch.c:	iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imask);
+drivers/gpio/gpio-pch.c:	iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->iclr);
+drivers/gpio/gpio-pch.c:	unsigned long reg_val = ioread32(&chip->reg->istatus);
+drivers/gpio/gpio-pch.c:	for_each_set_bit(i, &reg_val, gpio_pins[chip->ioh]) {
+drivers/gpio/gpio-pch.c:		dev_dbg(chip->dev, "[%d]:irq=%d  status=0x%lx\n", i, irq, reg_val);
+drivers/gpio/gpio-pch.c:		generic_handle_irq(chip->irq_base + i);
+drivers/gpio/gpio-pch.c:	gc = devm_irq_alloc_generic_chip(chip->dev, "pch_gpio", 1, irq_start,
+drivers/gpio/gpio-pch.c:					 chip->base, handle_simple_irq);
+drivers/gpio/gpio-pch.c:	rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num),
+drivers/gpio/gpio-pch.c:	chip->dev = &pdev->dev;
+drivers/gpio/gpio-pch.c:	chip->base = pcim_iomap_table(pdev)[1];
+drivers/gpio/gpio-pch.c:		chip->ioh = INTEL_EG20T_PCH;
+drivers/gpio/gpio-pch.c:		chip->ioh = OKISEMI_ML7223m_IOH;
+drivers/gpio/gpio-pch.c:		chip->ioh = OKISEMI_ML7223n_IOH;
+drivers/gpio/gpio-pch.c:	chip->reg = chip->base;
+drivers/gpio/gpio-pch.c:	spin_lock_init(&chip->spinlock);
+drivers/gpio/gpio-pch.c:	ret = devm_gpiochip_add_data(&pdev->dev, &chip->gpio, chip);
+drivers/gpio/gpio-pch.c:					gpio_pins[chip->ioh], NUMA_NO_NODE);
+drivers/gpio/gpio-pch.c:		chip->irq_base = -1;
+drivers/gpio/gpio-pch.c:	chip->irq_base = irq_base;
+drivers/gpio/gpio-pch.c:	msk = (1 << gpio_pins[chip->ioh]) - 1;
+drivers/gpio/gpio-pch.c:	iowrite32(msk, &chip->reg->imask);
+drivers/gpio/gpio-pch.c:	iowrite32(msk, &chip->reg->ien);
+drivers/gpio/gpio-pch.c:	return pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]);
+drivers/gpio/gpio-pch.c:	spin_lock_irqsave(&chip->spinlock, flags);
+drivers/gpio/gpio-pch.c:	spin_unlock_irqrestore(&chip->spinlock, flags);
+drivers/gpio/gpio-pch.c:	spin_lock_irqsave(&chip->spinlock, flags);
+drivers/gpio/gpio-pch.c:	iowrite32(0x01, &chip->reg->reset);
+drivers/gpio/gpio-pch.c:	iowrite32(0x00, &chip->reg->reset);
+drivers/gpio/gpio-pch.c:	spin_unlock_irqrestore(&chip->spinlock, flags);
+drivers/gpio/gpio-pci-idio-16.c:	chip->set(chip, offset, value);
+drivers/gpio/gpio-pci-idio-16.c:	bitmap_zero(bits, chip->ngpio);
+drivers/gpio/gpio-pci-idio-16.c:	for_each_set_bit(gpio, &idio16gpio->irq_mask, chip->ngpio)
+drivers/gpio/gpio-pci-idio-16.c:		generic_handle_irq(irq_find_mapping(chip->irq.domain, gpio));
+drivers/gpio/gpio-pcie-idio-24.c:	chip->set(chip, offset, value);
+drivers/gpio/gpio-pcie-idio-24.c:	bitmap_zero(bits, chip->ngpio);
+drivers/gpio/gpio-pcie-idio-24.c:	for_each_set_bit(gpio, &irq_mask, chip->ngpio - 24)
+drivers/gpio/gpio-pcie-idio-24.c:		generic_handle_irq(irq_find_mapping(chip->irq.domain,
+drivers/gpio/gpio-pisosr.c:	bitmap_zero(bits, chip->ngpio);
+drivers/gpio/gpio-pisosr.c:	for_each_set_clump8(offset, gpio_mask, mask, chip->ngpio) {
+drivers/gpio/gpio-pmic-eic-sprd.c:		dev_warn(chip->parent, "PMIC EIC level was changed.\n");
+drivers/gpio/gpio-pmic-eic-sprd.c:	for_each_set_bit(n, &status, chip->ngpio) {
+drivers/gpio/gpio-pmic-eic-sprd.c:		girq = irq_find_mapping(chip->irq.domain, n);
+drivers/gpio/gpio-pxa.c:	base = gpio_bank_base(&pchip->chip, gpio);
+drivers/gpio/gpio-pxa.c:	irq_gpio0 = irq_find_mapping(pchip->irqdomain, 0);
+drivers/gpio/gpio-pxa.c:	return irq_find_mapping(pchip->irqdomain, offset);
+drivers/gpio/gpio-pxa.c:		ret = pinctrl_gpio_direction_input(chip->base + offset);
+drivers/gpio/gpio-pxa.c:	if (__gpio_is_inverted(chip->base + offset))
+drivers/gpio/gpio-pxa.c:		ret = pinctrl_gpio_direction_output(chip->base + offset);
+drivers/gpio/gpio-pxa.c:	if (__gpio_is_inverted(chip->base + offset))
+drivers/gpio/gpio-pxa.c:	pchip->banks = devm_kcalloc(pchip->dev, nbanks, sizeof(*pchip->banks),
+drivers/gpio/gpio-pxa.c:	if (!pchip->banks)
+drivers/gpio/gpio-pxa.c:	pchip->chip.label = "gpio-pxa";
+drivers/gpio/gpio-pxa.c:	pchip->chip.direction_input  = pxa_gpio_direction_input;
+drivers/gpio/gpio-pxa.c:	pchip->chip.direction_output = pxa_gpio_direction_output;
+drivers/gpio/gpio-pxa.c:	pchip->chip.get = pxa_gpio_get;
+drivers/gpio/gpio-pxa.c:	pchip->chip.set = pxa_gpio_set;
+drivers/gpio/gpio-pxa.c:	pchip->chip.to_irq = pxa_gpio_to_irq;
+drivers/gpio/gpio-pxa.c:	pchip->chip.ngpio = ngpio;
+drivers/gpio/gpio-pxa.c:		pchip->chip.request = gpiochip_generic_request;
+drivers/gpio/gpio-pxa.c:		pchip->chip.free = gpiochip_generic_free;
+drivers/gpio/gpio-pxa.c:	pchip->chip.of_node = np;
+drivers/gpio/gpio-pxa.c:	pchip->chip.of_xlate = pxa_gpio_of_xlate;
+drivers/gpio/gpio-pxa.c:	pchip->chip.of_gpio_n_cells = 2;
+drivers/gpio/gpio-pxa.c:		bank = pchip->banks + i;
+drivers/gpio/gpio-pxa.c:	return gpiochip_add_data(&pchip->chip, pchip);
+drivers/gpio/gpio-pxa.c:	struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio);
+drivers/gpio/gpio-pxa.c:					irq_find_mapping(pchip->irqdomain,
+drivers/gpio/gpio-pxa.c:	if (in_irq == pchip->irq0) {
+drivers/gpio/gpio-pxa.c:		generic_handle_irq(irq_find_mapping(pchip->irqdomain, 0));
+drivers/gpio/gpio-pxa.c:	} else if (in_irq == pchip->irq1) {
+drivers/gpio/gpio-pxa.c:		generic_handle_irq(irq_find_mapping(pchip->irqdomain, 1));
+drivers/gpio/gpio-pxa.c:	void __iomem *base = gpio_bank_base(&pchip->chip, gpio);
+drivers/gpio/gpio-pxa.c:	struct pxa_gpio_bank *b = gpio_to_pxabank(&pchip->chip, gpio);
+drivers/gpio/gpio-pxa.c:	void __iomem *base = gpio_bank_base(&pchip->chip, gpio);
+drivers/gpio/gpio-pxa.c:	if (pchip->set_wake)
+drivers/gpio/gpio-pxa.c:		return pchip->set_wake(gpio, on);
+drivers/gpio/gpio-pxa.c:	struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio);
+drivers/gpio/gpio-pxa.c:	pchip->dev = &pdev->dev;
+drivers/gpio/gpio-pxa.c:		pchip->set_wake = info->gpio_set_wake;
+drivers/gpio/gpio-pxa.c:	pchip->irqdomain = irq_domain_add_legacy(pdev->dev.of_node,
+drivers/gpio/gpio-pxa.c:	if (!pchip->irqdomain)
+drivers/gpio/gpio-pxa.c:	pchip->irq0 = irq0;
+drivers/gpio/gpio-pxa.c:	pchip->irq1 = irq1;
+drivers/gpio/gpio-rcar.c:	error = pinctrl_gpio_request(chip->base + offset);
+drivers/gpio/gpio-rcar.c:	pinctrl_gpio_free(chip->base + offset);
+drivers/gpio/gpio-rcar.c:	bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
+drivers/gpio/gpio-rcar.c:	if (chip->valid_mask)
+drivers/gpio/gpio-rcar.c:		bankmask &= chip->valid_mask[0];
+drivers/gpio/gpio-rcar.c:	gpio_chip->request = gpio_rcar_request;
+drivers/gpio/gpio-rcar.c:	gpio_chip->free = gpio_rcar_free;
+drivers/gpio/gpio-rcar.c:	gpio_chip->get_direction = gpio_rcar_get_direction;
+drivers/gpio/gpio-rcar.c:	gpio_chip->direction_input = gpio_rcar_direction_input;
+drivers/gpio/gpio-rcar.c:	gpio_chip->get = gpio_rcar_get;
+drivers/gpio/gpio-rcar.c:	gpio_chip->direction_output = gpio_rcar_direction_output;
+drivers/gpio/gpio-rcar.c:	gpio_chip->set = gpio_rcar_set;
+drivers/gpio/gpio-rcar.c:	gpio_chip->set_multiple = gpio_rcar_set_multiple;
+drivers/gpio/gpio-rcar.c:	gpio_chip->label = name;
+drivers/gpio/gpio-rcar.c:	gpio_chip->parent = dev;
+drivers/gpio/gpio-rcar.c:	gpio_chip->owner = THIS_MODULE;
+drivers/gpio/gpio-rcar.c:	gpio_chip->base = -1;
+drivers/gpio/gpio-rcar.c:	gpio_chip->ngpio = npins;
+drivers/gpio/gpio-rcar.c:	irq_chip->name = "gpio-rcar";
+drivers/gpio/gpio-rcar.c:	irq_chip->parent_device = dev;
+drivers/gpio/gpio-rcar.c:	irq_chip->irq_mask = gpio_rcar_irq_disable;
+drivers/gpio/gpio-rcar.c:	irq_chip->irq_unmask = gpio_rcar_irq_enable;
+drivers/gpio/gpio-rcar.c:	irq_chip->irq_set_type = gpio_rcar_irq_set_type;
+drivers/gpio/gpio-rcar.c:	irq_chip->irq_set_wake = gpio_rcar_irq_set_wake;
+drivers/gpio/gpio-rcar.c:	irq_chip->flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;
+drivers/gpio/gpio-rda.c:		girq = irq_find_mapping(chip->irq.domain, n);
+drivers/gpio/gpio-sch311x.c:		dev_err(chip->parent, "Failed to request region 0x%04x.\n",
+drivers/gpio/gpio-sprd.c:	for (bank = 0; bank * SPRD_GPIO_BANK_NR < chip->ngpio; bank++) {
+drivers/gpio/gpio-sprd.c:			girq = irq_find_mapping(chip->irq.domain,
+drivers/gpio/gpio-sta2x11.c:	struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK];
+drivers/gpio/gpio-sta2x11.c:	struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK];
+drivers/gpio/gpio-sta2x11.c:	struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK];
+drivers/gpio/gpio-sta2x11.c:	struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK];
+drivers/gpio/gpio-sta2x11.c:	return chip->irq_base + offset;
+drivers/gpio/gpio-sta2x11.c:	struct gpio_chip *gpio = &chip->gpio;
+drivers/gpio/gpio-sta2x11.c:	gpio->label = dev_name(chip->dev);
+drivers/gpio/gpio-sta2x11.c:	struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK];
+drivers/gpio/gpio-sta2x11.c:	spin_lock_irqsave(&chip->lock, flags);
+drivers/gpio/gpio-sta2x11.c:		spin_unlock_irqrestore(&chip->lock, flags);
+drivers/gpio/gpio-sta2x11.c:	spin_unlock_irqrestore(&chip->lock, flags);
+drivers/gpio/gpio-sta2x11.c:	int nr = data->irq - chip->irq_base;
+drivers/gpio/gpio-sta2x11.c:	struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK];
+drivers/gpio/gpio-sta2x11.c:	spin_lock_irqsave(&chip->lock, flags);
+drivers/gpio/gpio-sta2x11.c:	if (chip->irq_type[nr] & IRQ_TYPE_EDGE_RISING) {
+drivers/gpio/gpio-sta2x11.c:	if (chip->irq_type[nr] & IRQ_TYPE_EDGE_FALLING) {
+drivers/gpio/gpio-sta2x11.c:	spin_unlock_irqrestore(&chip->lock, flags);
+drivers/gpio/gpio-sta2x11.c:	int nr = data->irq - chip->irq_base;
+drivers/gpio/gpio-sta2x11.c:	struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK];
+drivers/gpio/gpio-sta2x11.c:	type = chip->irq_type[nr];
+drivers/gpio/gpio-sta2x11.c:	spin_lock_irqsave(&chip->lock, flags);
+drivers/gpio/gpio-sta2x11.c:	spin_unlock_irqrestore(&chip->lock, flags);
+drivers/gpio/gpio-sta2x11.c:	int nr = d->irq - chip->irq_base;
+drivers/gpio/gpio-sta2x11.c:	chip->irq_type[nr] = type; /* used for enable/disable */
+drivers/gpio/gpio-sta2x11.c:		regs = chip->regs[i];
+drivers/gpio/gpio-sta2x11.c:		base = chip->irq_base + i * GSTA_GPIO_PER_BLOCK;
+drivers/gpio/gpio-sta2x11.c:	gc = devm_irq_alloc_generic_chip(chip->dev, KBUILD_MODNAME, 1,
+drivers/gpio/gpio-sta2x11.c:					 chip->irq_base,
+drivers/gpio/gpio-sta2x11.c:					 chip->reg_base, handle_simple_irq);
+drivers/gpio/gpio-sta2x11.c:	rv = devm_irq_setup_generic_chip(chip->dev, gc,
+drivers/gpio/gpio-sta2x11.c:			i = chip->irq_base + j;
+drivers/gpio/gpio-sta2x11.c:	chip->dev = &dev->dev;
+drivers/gpio/gpio-sta2x11.c:	chip->reg_base = devm_platform_ioremap_resource(dev, 0);
+drivers/gpio/gpio-sta2x11.c:	if (IS_ERR(chip->reg_base))
+drivers/gpio/gpio-sta2x11.c:		return PTR_ERR(chip->reg_base);
+drivers/gpio/gpio-sta2x11.c:		chip->regs[i] = chip->reg_base + i * 4096;
+drivers/gpio/gpio-sta2x11.c:		writel(0, &chip->regs[i]->rimsc);
+drivers/gpio/gpio-sta2x11.c:		writel(0, &chip->regs[i]->fimsc);
+drivers/gpio/gpio-sta2x11.c:		writel(~0, &chip->regs[i]->ic);
+drivers/gpio/gpio-sta2x11.c:	spin_lock_init(&chip->lock);
+drivers/gpio/gpio-sta2x11.c:	chip->irq_base = err;
+drivers/gpio/gpio-sta2x11.c:	err = devm_gpiochip_add_data(&dev->dev, &chip->gpio, chip);
+drivers/gpio/gpio-stp-xway.c: * xway_stp_get() - gpio_chip->get - get gpios.
+drivers/gpio/gpio-stp-xway.c:	return (xway_stp_r32(chip->virt, XWAY_STP_CPU0) & BIT(gpio));
+drivers/gpio/gpio-stp-xway.c: * xway_stp_set() - gpio_chip->set - set gpios.
+drivers/gpio/gpio-stp-xway.c:		chip->shadow |= BIT(gpio);
+drivers/gpio/gpio-stp-xway.c:		chip->shadow &= ~BIT(gpio);
+drivers/gpio/gpio-stp-xway.c:	xway_stp_w32(chip->virt, chip->shadow, XWAY_STP_CPU0);
+drivers/gpio/gpio-stp-xway.c:	xway_stp_w32_mask(chip->virt, 0, XWAY_STP_CON_SWU, XWAY_STP_CON0);
+drivers/gpio/gpio-stp-xway.c: * xway_stp_dir_out() - gpio_chip->dir_out - set gpio direction.
+drivers/gpio/gpio-stp-xway.c: * xway_stp_request() - gpio_chip->request
+drivers/gpio/gpio-stp-xway.c:	if ((gpio < 8) && (chip->reserved & BIT(gpio))) {
+drivers/gpio/gpio-stp-xway.c:	xway_stp_w32(chip->virt, 0, XWAY_STP_AR);
+drivers/gpio/gpio-stp-xway.c:	xway_stp_w32(chip->virt, 0, XWAY_STP_CPU0);
+drivers/gpio/gpio-stp-xway.c:	xway_stp_w32(chip->virt, 0, XWAY_STP_CPU1);
+drivers/gpio/gpio-stp-xway.c:	xway_stp_w32(chip->virt, XWAY_STP_CON_SWU, XWAY_STP_CON0);
+drivers/gpio/gpio-stp-xway.c:	xway_stp_w32(chip->virt, 0, XWAY_STP_CON1);
+drivers/gpio/gpio-stp-xway.c:	xway_stp_w32_mask(chip->virt, XWAY_STP_EDGE_MASK,
+drivers/gpio/gpio-stp-xway.c:				chip->edge, XWAY_STP_CON0);
+drivers/gpio/gpio-stp-xway.c:	xway_stp_w32_mask(chip->virt, XWAY_STP_GROUP_MASK,
+drivers/gpio/gpio-stp-xway.c:				chip->groups, XWAY_STP_CON1);
+drivers/gpio/gpio-stp-xway.c:	xway_stp_w32_mask(chip->virt,
+drivers/gpio/gpio-stp-xway.c:			chip->dsl << XWAY_STP_ADSL_SHIFT,
+drivers/gpio/gpio-stp-xway.c:	xway_stp_w32_mask(chip->virt,
+drivers/gpio/gpio-stp-xway.c:			chip->phy1 << XWAY_STP_PHY1_SHIFT,
+drivers/gpio/gpio-stp-xway.c:	xway_stp_w32_mask(chip->virt,
+drivers/gpio/gpio-stp-xway.c:			chip->phy2 << XWAY_STP_PHY2_SHIFT,
+drivers/gpio/gpio-stp-xway.c:	chip->reserved = (chip->phy2 << 5) | (chip->phy1 << 2) | chip->dsl;
+drivers/gpio/gpio-stp-xway.c:	if (chip->reserved)
+drivers/gpio/gpio-stp-xway.c:		xway_stp_w32_mask(chip->virt, XWAY_STP_UPD_MASK,
+drivers/gpio/gpio-stp-xway.c:	chip->virt = devm_platform_ioremap_resource(pdev, 0);
+drivers/gpio/gpio-stp-xway.c:	if (IS_ERR(chip->virt))
+drivers/gpio/gpio-stp-xway.c:		return PTR_ERR(chip->virt);
+drivers/gpio/gpio-stp-xway.c:	chip->gc.parent = &pdev->dev;
+drivers/gpio/gpio-stp-xway.c:	chip->gc.label = "stp-xway";
+drivers/gpio/gpio-stp-xway.c:	chip->gc.direction_output = xway_stp_dir_out;
+drivers/gpio/gpio-stp-xway.c:	chip->gc.get = xway_stp_get;
+drivers/gpio/gpio-stp-xway.c:	chip->gc.set = xway_stp_set;
+drivers/gpio/gpio-stp-xway.c:	chip->gc.request = xway_stp_request;
+drivers/gpio/gpio-stp-xway.c:	chip->gc.base = -1;
+drivers/gpio/gpio-stp-xway.c:	chip->gc.owner = THIS_MODULE;
+drivers/gpio/gpio-stp-xway.c:		chip->shadow = shadow;
+drivers/gpio/gpio-stp-xway.c:		chip->groups = groups & XWAY_STP_GROUP_MASK;
+drivers/gpio/gpio-stp-xway.c:		chip->groups = XWAY_STP_GROUP0;
+drivers/gpio/gpio-stp-xway.c:	chip->gc.ngpio = fls(chip->groups) * 8;
+drivers/gpio/gpio-stp-xway.c:		chip->dsl = dsl & XWAY_STP_ADSL_MASK;
+drivers/gpio/gpio-stp-xway.c:			chip->phy1 = phy & XWAY_STP_PHY_MASK;
+drivers/gpio/gpio-stp-xway.c:			chip->phy2 = phy & XWAY_STP_PHY_MASK;
+drivers/gpio/gpio-stp-xway.c:		chip->edge = XWAY_STP_FALLING;
+drivers/gpio/gpio-stp-xway.c:	ret = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip);
+drivers/gpio/gpio-syscon.c:	chip->set(chip, offset, val);
+drivers/gpio/gpio-syscon.c:		dev_err(chip->parent, "gpio write failed ret(%d)\n", ret);
+drivers/gpio/gpio-syscon.c:		dev_err(chip->parent, "gpio write failed ret(%d)\n", ret);
+drivers/gpio/gpio-tegra.c:	return pinctrl_gpio_request(chip->base + offset);
+drivers/gpio/gpio-tegra.c:	pinctrl_gpio_free(chip->base + offset);
+drivers/gpio/gpio-tegra.c:	ret = pinctrl_gpio_direction_input(chip->base + offset);
+drivers/gpio/gpio-tegra.c:			 chip->base + offset, ret);
+drivers/gpio/gpio-tegra.c:	ret = pinctrl_gpio_direction_output(chip->base + offset);
+drivers/gpio/gpio-tegra.c:			 chip->base + offset, ret);
+drivers/gpio/gpio-tegra186.c:	chip->set(chip, offset, level);
+drivers/gpio/gpio-tegra186.c:	if (WARN_ON(chip->of_gpio_n_cells < 2))
+drivers/gpio/gpio-tegra186.c:	if (WARN_ON(spec->args_count < chip->of_gpio_n_cells))
+drivers/gpio/gpio-tegra186.c:		dev_err(chip->parent, "invalid port number: %u\n", port);
+drivers/gpio/gpio-tegra186.c:	*parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq);
+drivers/gpio/gpio-thunderx.c:	for (bank = 0; bank <= chip->ngpio / 64; bank++) {
+drivers/gpio/gpio-thunderx.c:	chip->label = KBUILD_MODNAME;
+drivers/gpio/gpio-thunderx.c:	chip->parent = dev;
+drivers/gpio/gpio-thunderx.c:	chip->owner = THIS_MODULE;
+drivers/gpio/gpio-thunderx.c:	chip->request = thunderx_gpio_request;
+drivers/gpio/gpio-thunderx.c:	chip->base = -1; /* System allocated */
+drivers/gpio/gpio-thunderx.c:	chip->can_sleep = false;
+drivers/gpio/gpio-thunderx.c:	chip->ngpio = ngpio;
+drivers/gpio/gpio-thunderx.c:	chip->get_direction = thunderx_gpio_get_direction;
+drivers/gpio/gpio-thunderx.c:	chip->direction_input = thunderx_gpio_dir_in;
+drivers/gpio/gpio-thunderx.c:	chip->get = thunderx_gpio_get;
+drivers/gpio/gpio-thunderx.c:	chip->direction_output = thunderx_gpio_dir_out;
+drivers/gpio/gpio-thunderx.c:	chip->set = thunderx_gpio_set;
+drivers/gpio/gpio-thunderx.c:	chip->set_multiple = thunderx_gpio_set_multiple;
+drivers/gpio/gpio-thunderx.c:	chip->set_config = thunderx_gpio_set_config;
+drivers/gpio/gpio-thunderx.c:	girq = &chip->irq;
+drivers/gpio/gpio-thunderx.c:		err = irq_domain_push_irq(chip->irq.domain,
+drivers/gpio/gpio-thunderx.c:		 ngpio, chip->base);
+drivers/gpio/gpio-timberdale.c:	data->chip->irq_ack(data);
+drivers/gpio/gpio-tqmx86.c:	chip->label = "gpio-tqmx86";
+drivers/gpio/gpio-tqmx86.c:	chip->owner = THIS_MODULE;
+drivers/gpio/gpio-tqmx86.c:	chip->can_sleep = false;
+drivers/gpio/gpio-tqmx86.c:	chip->base = -1;
+drivers/gpio/gpio-tqmx86.c:	chip->direction_input = tqmx86_gpio_direction_input;
+drivers/gpio/gpio-tqmx86.c:	chip->direction_output = tqmx86_gpio_direction_output;
+drivers/gpio/gpio-tqmx86.c:	chip->get_direction = tqmx86_gpio_get_direction;
+drivers/gpio/gpio-tqmx86.c:	chip->get = tqmx86_gpio_get;
+drivers/gpio/gpio-tqmx86.c:	chip->set = tqmx86_gpio_set;
+drivers/gpio/gpio-tqmx86.c:	chip->ngpio = TQMX86_NGPIO;
+drivers/gpio/gpio-tqmx86.c:	chip->parent = pdev->dev.parent;
+drivers/gpio/gpio-tqmx86.c:		irq_chip->name = chip->label;
+drivers/gpio/gpio-tqmx86.c:		irq_chip->parent_device = &pdev->dev;
+drivers/gpio/gpio-tqmx86.c:		irq_chip->irq_mask = tqmx86_gpio_irq_mask;
+drivers/gpio/gpio-tqmx86.c:		irq_chip->irq_unmask = tqmx86_gpio_irq_unmask;
+drivers/gpio/gpio-tqmx86.c:		irq_chip->irq_set_type = tqmx86_gpio_irq_set_type;
+drivers/gpio/gpio-tqmx86.c:		girq = &chip->irq;
+drivers/gpio/gpio-tqmx86.c:		 chip->ngpio);
+drivers/gpio/gpio-ts4800.c:	chip->ngpio = ngpios;
+drivers/gpio/gpio-twl4030.c:		pdata = dev_get_platdata(chip->parent);
+drivers/gpio/gpio-twl6040.c:	struct twl6040 *twl6040 = dev_get_drvdata(chip->parent->parent);
+drivers/gpio/gpio-twl6040.c:	struct twl6040 *twl6040 = dev_get_drvdata(chip->parent->parent);
+drivers/gpio/gpio-uniphier.c:	for_each_set_clump8(i, bank_mask, mask, chip->ngpio) {
+drivers/gpio/gpio-uniphier.c:	fwspec.fwnode = of_node_to_fwnode(chip->parent->of_node);
+drivers/gpio/gpio-uniphier.c:	chip->label = dev_name(dev);
+drivers/gpio/gpio-uniphier.c:	chip->parent = dev;
+drivers/gpio/gpio-uniphier.c:	chip->request = gpiochip_generic_request;
+drivers/gpio/gpio-uniphier.c:	chip->free = gpiochip_generic_free;
+drivers/gpio/gpio-uniphier.c:	chip->get_direction = uniphier_gpio_get_direction;
+drivers/gpio/gpio-uniphier.c:	chip->direction_input = uniphier_gpio_direction_input;
+drivers/gpio/gpio-uniphier.c:	chip->direction_output = uniphier_gpio_direction_output;
+drivers/gpio/gpio-uniphier.c:	chip->get = uniphier_gpio_get;
+drivers/gpio/gpio-uniphier.c:	chip->set = uniphier_gpio_set;
+drivers/gpio/gpio-uniphier.c:	chip->set_multiple = uniphier_gpio_set_multiple;
+drivers/gpio/gpio-uniphier.c:	chip->to_irq = uniphier_gpio_to_irq;
+drivers/gpio/gpio-uniphier.c:	chip->base = -1;
+drivers/gpio/gpio-uniphier.c:	chip->ngpio = ngpios;
+drivers/gpio/gpio-uniphier.c:	irq_chip->name = dev_name(dev);
+drivers/gpio/gpio-uniphier.c:	irq_chip->irq_mask = uniphier_gpio_irq_mask;
+drivers/gpio/gpio-uniphier.c:	irq_chip->irq_unmask = uniphier_gpio_irq_unmask;
+drivers/gpio/gpio-uniphier.c:	irq_chip->irq_eoi = irq_chip_eoi_parent;
+drivers/gpio/gpio-uniphier.c:	irq_chip->irq_set_affinity = irq_chip_set_affinity_parent;
+drivers/gpio/gpio-uniphier.c:	irq_chip->irq_set_type = uniphier_gpio_irq_set_type;
+drivers/gpio/gpio-vf610.c:	return pinctrl_gpio_direction_input(chip->base + gpio);
+drivers/gpio/gpio-vf610.c:	return pinctrl_gpio_direction_output(chip->base + gpio);
+drivers/gpio/gpio-viperboard.c:			dev_err(chip->parent, "usb error setting pin value\n");
+drivers/gpio/gpio-viperboard.c:			dev_err(chip->parent, "usb error setting pin value\n");
+drivers/gpio/gpio-viperboard.c:		dev_err(chip->parent, "usb error setting pin to input\n");
+drivers/gpio/gpio-viperboard.c:		dev_err(chip->parent, "usb error setting pin to output\n");
+drivers/gpio/gpio-vr41xx.c:	if (pin >= chip->ngpio)
+drivers/gpio/gpio-vr41xx.c:	if (pin >= chip->ngpio)
+drivers/gpio/gpio-vr41xx.c:	if (pin >= chip->ngpio)
+drivers/gpio/gpio-vr41xx.c:	if (offset >= chip->ngpio)
+drivers/gpio/gpio-wm831x.c:	for (i = 0; i < chip->ngpio; i++) {
+drivers/gpio/gpio-wm831x.c:		int gpio = i + chip->base;
+drivers/gpio/gpio-wm8994.c:	for (i = 0; i < chip->ngpio; i++) {
+drivers/gpio/gpio-wm8994.c:		int gpio = i + chip->base;
+drivers/gpio/gpio-ws16c48.c:	bitmap_zero(bits, chip->ngpio);
+drivers/gpio/gpio-ws16c48.c:	for_each_set_clump8(offset, gpio_mask, mask, chip->ngpio) {
+drivers/gpio/gpio-ws16c48.c:	for_each_set_clump8(offset, gpio_mask, mask, chip->ngpio) {
+drivers/gpio/gpio-ws16c48.c:					chip->irq.domain, gpio + 8*port));
+drivers/gpio/gpio-xgene.c:	return !!(ioread32(chip->base + bank_offset) & BIT(bit_offset));
+drivers/gpio/gpio-xgene.c:	setval = ioread32(chip->base + bank_offset);
+drivers/gpio/gpio-xgene.c:	iowrite32(setval, chip->base + bank_offset);
+drivers/gpio/gpio-xgene.c:	spin_lock_irqsave(&chip->lock, flags);
+drivers/gpio/gpio-xgene.c:	spin_unlock_irqrestore(&chip->lock, flags);
+drivers/gpio/gpio-xgene.c:	if (ioread32(chip->base + bank_offset) & BIT(bit_offset))
+drivers/gpio/gpio-xgene.c:	spin_lock_irqsave(&chip->lock, flags);
+drivers/gpio/gpio-xgene.c:	dirval = ioread32(chip->base + bank_offset);
+drivers/gpio/gpio-xgene.c:	iowrite32(dirval, chip->base + bank_offset);
+drivers/gpio/gpio-xgene.c:	spin_unlock_irqrestore(&chip->lock, flags);
+drivers/gpio/gpio-xgene.c:	spin_lock_irqsave(&chip->lock, flags);
+drivers/gpio/gpio-xgene.c:	dirval = ioread32(chip->base + bank_offset);
+drivers/gpio/gpio-xgene.c:	iowrite32(dirval, chip->base + bank_offset);
+drivers/gpio/gpio-xgene.c:	spin_unlock_irqrestore(&chip->lock, flags);
+drivers/gpio/gpio-xgs-iproc.c:	spin_lock_irqsave(&chip->lock, flags);
+drivers/gpio/gpio-xgs-iproc.c:			       chip->base + IPROC_GPIO_CCA_INT_EVENT);
+drivers/gpio/gpio-xgs-iproc.c:	spin_unlock_irqrestore(&chip->lock, flags);
+drivers/gpio/gpio-xgs-iproc.c:	spin_lock_irqsave(&chip->lock, flags);
+drivers/gpio/gpio-xgs-iproc.c:	event_mask = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK);
+drivers/gpio/gpio-xgs-iproc.c:	int_mask = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL_MASK);
+drivers/gpio/gpio-xgs-iproc.c:			       chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK);
+drivers/gpio/gpio-xgs-iproc.c:			       chip->base + IPROC_GPIO_CCA_INT_LEVEL_MASK);
+drivers/gpio/gpio-xgs-iproc.c:	spin_unlock_irqrestore(&chip->lock, flags);
+drivers/gpio/gpio-xgs-iproc.c:	spin_lock_irqsave(&chip->lock, flags);
+drivers/gpio/gpio-xgs-iproc.c:	event_mask = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK);
+drivers/gpio/gpio-xgs-iproc.c:	int_mask = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL_MASK);
+drivers/gpio/gpio-xgs-iproc.c:			       chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK);
+drivers/gpio/gpio-xgs-iproc.c:			       chip->base + IPROC_GPIO_CCA_INT_LEVEL_MASK);
+drivers/gpio/gpio-xgs-iproc.c:	spin_unlock_irqrestore(&chip->lock, flags);
+drivers/gpio/gpio-xgs-iproc.c:	spin_lock_irqsave(&chip->lock, flags);
+drivers/gpio/gpio-xgs-iproc.c:		event_pol = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EDGE);
+drivers/gpio/gpio-xgs-iproc.c:		writel_relaxed(event_pol, chip->base + IPROC_GPIO_CCA_INT_EDGE);
+drivers/gpio/gpio-xgs-iproc.c:		event_pol = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EDGE);
+drivers/gpio/gpio-xgs-iproc.c:		writel_relaxed(event_pol, chip->base + IPROC_GPIO_CCA_INT_EDGE);
+drivers/gpio/gpio-xgs-iproc.c:		int_pol = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL);
+drivers/gpio/gpio-xgs-iproc.c:		writel_relaxed(int_pol, chip->base + IPROC_GPIO_CCA_INT_LEVEL);
+drivers/gpio/gpio-xgs-iproc.c:		int_pol = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL);
+drivers/gpio/gpio-xgs-iproc.c:		writel_relaxed(int_pol, chip->base + IPROC_GPIO_CCA_INT_LEVEL);
+drivers/gpio/gpio-xgs-iproc.c:	spin_unlock_irqrestore(&chip->lock, flags);
+drivers/gpio/gpio-xgs-iproc.c:	int_status = readl_relaxed(chip->intr + IPROC_CCA_INT_STS);
+drivers/gpio/gpio-xgs-iproc.c:		    readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK);
+drivers/gpio/gpio-xgs-iproc.c:		event &= readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EVENT);
+drivers/gpio/gpio-xgs-iproc.c:		level = readl_relaxed(chip->base + IPROC_GPIO_CCA_DIN);
+drivers/gpio/gpio-xgs-iproc.c:		level ^= readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL);
+drivers/gpio/gpio-xgs-iproc.c:		    readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL_MASK);
+drivers/gpio/gpio-xgs-iproc.c:	chip->dev = dev;
+drivers/gpio/gpio-xgs-iproc.c:	spin_lock_init(&chip->lock);
+drivers/gpio/gpio-xgs-iproc.c:	chip->base = devm_platform_ioremap_resource(pdev, 0);
+drivers/gpio/gpio-xgs-iproc.c:	if (IS_ERR(chip->base))
+drivers/gpio/gpio-xgs-iproc.c:		return PTR_ERR(chip->base);
+drivers/gpio/gpio-xgs-iproc.c:	ret = bgpio_init(&chip->gc, dev, 4,
+drivers/gpio/gpio-xgs-iproc.c:			 chip->base + IPROC_GPIO_CCA_DIN,
+drivers/gpio/gpio-xgs-iproc.c:			 chip->base + IPROC_GPIO_CCA_DOUT,
+drivers/gpio/gpio-xgs-iproc.c:			 chip->base + IPROC_GPIO_CCA_OUT_EN,
+drivers/gpio/gpio-xgs-iproc.c:	chip->gc.label = dev_name(dev);
+drivers/gpio/gpio-xgs-iproc.c:		chip->gc.ngpio = num_gpios;
+drivers/gpio/gpio-xgs-iproc.c:		irqc = &chip->irqchip;
+drivers/gpio/gpio-xgs-iproc.c:		chip->intr = devm_platform_ioremap_resource(pdev, 1);
+drivers/gpio/gpio-xgs-iproc.c:		if (IS_ERR(chip->intr))
+drivers/gpio/gpio-xgs-iproc.c:			return PTR_ERR(chip->intr);
+drivers/gpio/gpio-xgs-iproc.c:		val = readl_relaxed(chip->intr + IPROC_CCA_INT_MASK);
+drivers/gpio/gpio-xgs-iproc.c:		writel_relaxed(val, chip->intr + IPROC_CCA_INT_MASK);
+drivers/gpio/gpio-xgs-iproc.c:				       IRQF_SHARED, chip->gc.label, &chip->gc);
+drivers/gpio/gpio-xgs-iproc.c:		girq = &chip->gc.irq;
+drivers/gpio/gpio-xgs-iproc.c:	ret = devm_gpiochip_add_data(dev, &chip->gc, chip);
+drivers/gpio/gpio-xgs-iproc.c:	if (chip->intr) {
+drivers/gpio/gpio-xgs-iproc.c:		val = readl_relaxed(chip->intr + IPROC_CCA_INT_MASK);
+drivers/gpio/gpio-xgs-iproc.c:		writel_relaxed(val, chip->intr + IPROC_CCA_INT_MASK);
+drivers/gpio/gpio-xilinx.c:	if (gpio >= chip->gpio_width[0])
+drivers/gpio/gpio-xilinx.c:		return gpio - chip->gpio_width[0];
+drivers/gpio/gpio-xilinx.c:	val = xgpio_readreg(chip->regs + XGPIO_DATA_OFFSET +
+drivers/gpio/gpio-xilinx.c:	spin_lock_irqsave(&chip->gpio_lock[index], flags);
+drivers/gpio/gpio-xilinx.c:		chip->gpio_state[index] |= BIT(offset);
+drivers/gpio/gpio-xilinx.c:		chip->gpio_state[index] &= ~BIT(offset);
+drivers/gpio/gpio-xilinx.c:	xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET +
+drivers/gpio/gpio-xilinx.c:		       xgpio_regoffset(chip, gpio), chip->gpio_state[index]);
+drivers/gpio/gpio-xilinx.c:	spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
+drivers/gpio/gpio-xilinx.c:	spin_lock_irqsave(&chip->gpio_lock[index], flags);
+drivers/gpio/gpio-xilinx.c:			xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET +
+drivers/gpio/gpio-xilinx.c:				       chip->gpio_state[index]);
+drivers/gpio/gpio-xilinx.c:			spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
+drivers/gpio/gpio-xilinx.c:			spin_lock_irqsave(&chip->gpio_lock[index], flags);
+drivers/gpio/gpio-xilinx.c:				chip->gpio_state[index] |= BIT(offset);
+drivers/gpio/gpio-xilinx.c:				chip->gpio_state[index] &= ~BIT(offset);
+drivers/gpio/gpio-xilinx.c:	xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET +
+drivers/gpio/gpio-xilinx.c:		       xgpio_regoffset(chip, i), chip->gpio_state[index]);
+drivers/gpio/gpio-xilinx.c:	spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
+drivers/gpio/gpio-xilinx.c:	spin_lock_irqsave(&chip->gpio_lock[index], flags);
+drivers/gpio/gpio-xilinx.c:	chip->gpio_dir[index] |= BIT(offset);
+drivers/gpio/gpio-xilinx.c:	xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET +
+drivers/gpio/gpio-xilinx.c:		       xgpio_regoffset(chip, gpio), chip->gpio_dir[index]);
+drivers/gpio/gpio-xilinx.c:	spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
+drivers/gpio/gpio-xilinx.c:	spin_lock_irqsave(&chip->gpio_lock[index], flags);
+drivers/gpio/gpio-xilinx.c:		chip->gpio_state[index] |= BIT(offset);
+drivers/gpio/gpio-xilinx.c:		chip->gpio_state[index] &= ~BIT(offset);
+drivers/gpio/gpio-xilinx.c:	xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET +
+drivers/gpio/gpio-xilinx.c:			xgpio_regoffset(chip, gpio), chip->gpio_state[index]);
+drivers/gpio/gpio-xilinx.c:	chip->gpio_dir[index] &= ~BIT(offset);
+drivers/gpio/gpio-xilinx.c:	xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET +
+drivers/gpio/gpio-xilinx.c:			xgpio_regoffset(chip, gpio), chip->gpio_dir[index]);
+drivers/gpio/gpio-xilinx.c:	spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
+drivers/gpio/gpio-xilinx.c:	xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET,	chip->gpio_state[0]);
+drivers/gpio/gpio-xilinx.c:	xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET, chip->gpio_dir[0]);
+drivers/gpio/gpio-xilinx.c:	if (!chip->gpio_width[1])
+drivers/gpio/gpio-xilinx.c:	xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + XGPIO_CHANNEL_OFFSET,
+drivers/gpio/gpio-xilinx.c:		       chip->gpio_state[1]);
+drivers/gpio/gpio-xilinx.c:	xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET + XGPIO_CHANNEL_OFFSET,
+drivers/gpio/gpio-xilinx.c:		       chip->gpio_dir[1]);
+drivers/gpio/gpio-xilinx.c:	of_property_read_u32(np, "xlnx,dout-default", &chip->gpio_state[0]);
+drivers/gpio/gpio-xilinx.c:	if (of_property_read_u32(np, "xlnx,tri-default", &chip->gpio_dir[0]))
+drivers/gpio/gpio-xilinx.c:		chip->gpio_dir[0] = 0xFFFFFFFF;
+drivers/gpio/gpio-xilinx.c:	if (of_property_read_u32(np, "xlnx,gpio-width", &chip->gpio_width[0]))
+drivers/gpio/gpio-xilinx.c:		chip->gpio_width[0] = 32;
+drivers/gpio/gpio-xilinx.c:	spin_lock_init(&chip->gpio_lock[0]);
+drivers/gpio/gpio-xilinx.c:				     &chip->gpio_state[1]);
+drivers/gpio/gpio-xilinx.c:					 &chip->gpio_dir[1]))
+drivers/gpio/gpio-xilinx.c:			chip->gpio_dir[1] = 0xFFFFFFFF;
+drivers/gpio/gpio-xilinx.c:					 &chip->gpio_width[1]))
+drivers/gpio/gpio-xilinx.c:			chip->gpio_width[1] = 32;
+drivers/gpio/gpio-xilinx.c:		spin_lock_init(&chip->gpio_lock[1]);
+drivers/gpio/gpio-xilinx.c:	chip->gc.base = -1;
+drivers/gpio/gpio-xilinx.c:	chip->gc.ngpio = chip->gpio_width[0] + chip->gpio_width[1];
+drivers/gpio/gpio-xilinx.c:	chip->gc.parent = &pdev->dev;
+drivers/gpio/gpio-xilinx.c:	chip->gc.direction_input = xgpio_dir_in;
+drivers/gpio/gpio-xilinx.c:	chip->gc.direction_output = xgpio_dir_out;
+drivers/gpio/gpio-xilinx.c:	chip->gc.get = xgpio_get;
+drivers/gpio/gpio-xilinx.c:	chip->gc.set = xgpio_set;
+drivers/gpio/gpio-xilinx.c:	chip->gc.set_multiple = xgpio_set_multiple;
+drivers/gpio/gpio-xilinx.c:	chip->gc.label = dev_name(&pdev->dev);
+drivers/gpio/gpio-xilinx.c:	chip->regs = devm_platform_ioremap_resource(pdev, 0);
+drivers/gpio/gpio-xilinx.c:	if (IS_ERR(chip->regs)) {
+drivers/gpio/gpio-xilinx.c:		return PTR_ERR(chip->regs);
+drivers/gpio/gpio-xilinx.c:	status = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip);
+drivers/gpio/gpio-xra1403.c:		dev_err(chip->parent, "Failed to set pin: %d, ret: %d\n",
+drivers/gpio/gpio-xra1403.c:	for (i = 0; i < chip->ngpio; i++) {
+drivers/gpio/gpio-xra1403.c:			   chip->base + i, label,
+drivers/gpio/gpio-zx.c:	raw_spin_lock_irqsave(&chip->lock, flags);
+drivers/gpio/gpio-zx.c:	gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR);
+drivers/gpio/gpio-zx.c:	writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR);
+drivers/gpio/gpio-zx.c:	raw_spin_unlock_irqrestore(&chip->lock, flags);
+drivers/gpio/gpio-zx.c:	raw_spin_lock_irqsave(&chip->lock, flags);
+drivers/gpio/gpio-zx.c:	gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR);
+drivers/gpio/gpio-zx.c:	writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR);
+drivers/gpio/gpio-zx.c:		writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1);
+drivers/gpio/gpio-zx.c:		writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0);
+drivers/gpio/gpio-zx.c:	raw_spin_unlock_irqrestore(&chip->lock, flags);
+drivers/gpio/gpio-zx.c:	return !!(readw_relaxed(chip->base + ZX_GPIO_DI) & BIT(offset));
+drivers/gpio/gpio-zx.c:		writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1);
+drivers/gpio/gpio-zx.c:		writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0);
+drivers/gpio/gpio-zx.c:	raw_spin_lock_irqsave(&chip->lock, flags);
+drivers/gpio/gpio-zx.c:	gpioiev = readw_relaxed(chip->base + ZX_GPIO_IV);
+drivers/gpio/gpio-zx.c:	gpiois = readw_relaxed(chip->base + ZX_GPIO_IVE);
+drivers/gpio/gpio-zx.c:	gpioi_epos = readw_relaxed(chip->base + ZX_GPIO_IEP);
+drivers/gpio/gpio-zx.c:	gpioi_eneg = readw_relaxed(chip->base + ZX_GPIO_IEN);
+drivers/gpio/gpio-zx.c:	writew_relaxed(gpiois, chip->base + ZX_GPIO_IVE);
+drivers/gpio/gpio-zx.c:	writew_relaxed(gpioi_epos, chip->base + ZX_GPIO_IEP);
+drivers/gpio/gpio-zx.c:	writew_relaxed(gpioi_eneg, chip->base + ZX_GPIO_IEN);
+drivers/gpio/gpio-zx.c:	writew_relaxed(gpioiev, chip->base + ZX_GPIO_IV);
+drivers/gpio/gpio-zx.c:	raw_spin_unlock_irqrestore(&chip->lock, flags);
+drivers/gpio/gpio-zx.c:	pending = readw_relaxed(chip->base + ZX_GPIO_MIS);
+drivers/gpio/gpio-zx.c:	writew_relaxed(pending, chip->base + ZX_GPIO_IC);
+drivers/gpio/gpio-zx.c:	raw_spin_lock(&chip->lock);
+drivers/gpio/gpio-zx.c:	gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) | mask;
+drivers/gpio/gpio-zx.c:	writew_relaxed(gpioie, chip->base + ZX_GPIO_IM);
+drivers/gpio/gpio-zx.c:	gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) & ~mask;
+drivers/gpio/gpio-zx.c:	writew_relaxed(gpioie, chip->base + ZX_GPIO_IE);
+drivers/gpio/gpio-zx.c:	raw_spin_unlock(&chip->lock);
+drivers/gpio/gpio-zx.c:	raw_spin_lock(&chip->lock);
+drivers/gpio/gpio-zx.c:	gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) & ~mask;
+drivers/gpio/gpio-zx.c:	writew_relaxed(gpioie, chip->base + ZX_GPIO_IM);
+drivers/gpio/gpio-zx.c:	gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) | mask;
+drivers/gpio/gpio-zx.c:	writew_relaxed(gpioie, chip->base + ZX_GPIO_IE);
+drivers/gpio/gpio-zx.c:	raw_spin_unlock(&chip->lock);
+drivers/gpio/gpio-zx.c:	chip->base = devm_platform_ioremap_resource(pdev, 0);
+drivers/gpio/gpio-zx.c:	if (IS_ERR(chip->base))
+drivers/gpio/gpio-zx.c:		return PTR_ERR(chip->base);
+drivers/gpio/gpio-zx.c:	raw_spin_lock_init(&chip->lock);
+drivers/gpio/gpio-zx.c:		chip->gc.request = gpiochip_generic_request;
+drivers/gpio/gpio-zx.c:		chip->gc.free = gpiochip_generic_free;
+drivers/gpio/gpio-zx.c:	chip->gc.direction_input = zx_direction_input;
+drivers/gpio/gpio-zx.c:	chip->gc.direction_output = zx_direction_output;
+drivers/gpio/gpio-zx.c:	chip->gc.get = zx_get_value;
+drivers/gpio/gpio-zx.c:	chip->gc.set = zx_set_value;
+drivers/gpio/gpio-zx.c:	chip->gc.base = ZX_GPIO_NR * id;
+drivers/gpio/gpio-zx.c:	chip->gc.ngpio = ZX_GPIO_NR;
+drivers/gpio/gpio-zx.c:	chip->gc.label = dev_name(dev);
+drivers/gpio/gpio-zx.c:	chip->gc.parent = dev;
+drivers/gpio/gpio-zx.c:	chip->gc.owner = THIS_MODULE;
+drivers/gpio/gpio-zx.c:	writew_relaxed(0xffff, chip->base + ZX_GPIO_IM);
+drivers/gpio/gpio-zx.c:	writew_relaxed(0, chip->base + ZX_GPIO_IE);
+drivers/gpio/gpio-zx.c:	girq = &chip->gc.irq;
+drivers/gpio/gpio-zx.c:	ret = gpiochip_add_data(&chip->gc, chip);
+drivers/gpio/gpio-zynq.c:	ret = pm_runtime_get_sync(chip->parent);
+drivers/gpio/gpio-zynq.c:	pm_runtime_put(chip->parent);
+drivers/gpio/gpio-zynq.c:	ret = pm_runtime_get_sync(chip->parent);
+drivers/gpio/gpio-zynq.c:	pm_runtime_put(chip->parent);
+drivers/gpio/gpio-zynq.c:	chip->label = gpio->p_data->label;
+drivers/gpio/gpio-zynq.c:	chip->owner = THIS_MODULE;
+drivers/gpio/gpio-zynq.c:	chip->parent = &pdev->dev;
+drivers/gpio/gpio-zynq.c:	chip->get = zynq_gpio_get_value;
+drivers/gpio/gpio-zynq.c:	chip->set = zynq_gpio_set_value;
+drivers/gpio/gpio-zynq.c:	chip->request = zynq_gpio_request;
+drivers/gpio/gpio-zynq.c:	chip->free = zynq_gpio_free;
+drivers/gpio/gpio-zynq.c:	chip->direction_input = zynq_gpio_dir_in;
+drivers/gpio/gpio-zynq.c:	chip->direction_output = zynq_gpio_dir_out;
+drivers/gpio/gpio-zynq.c:	chip->get_direction = zynq_gpio_get_direction;
+drivers/gpio/gpio-zynq.c:	chip->base = of_alias_get_id(pdev->dev.of_node, "gpio");
+drivers/gpio/gpio-zynq.c:	chip->ngpio = gpio->p_data->ngpio;
+drivers/gpio/gpio-zynq.c:	girq = &chip->irq;
+drivers/gpio/gpiolib-acpi.c:		dev_err(acpi_gpio->chip->parent,
+drivers/gpio/gpiolib-acpi.c:	handle = ACPI_HANDLE(chip->parent);
+drivers/gpio/gpiolib-acpi.c:		dev_err(chip->parent,
+drivers/gpio/gpiolib-acpi.c:		dev_err(chip->parent,
+drivers/gpio/gpiolib-acpi.c:		dev_err(chip->parent,
+drivers/gpio/gpiolib-acpi.c:	if (!chip->parent || !chip->to_irq)
+drivers/gpio/gpiolib-acpi.c:	handle = ACPI_HANDLE(chip->parent);
+drivers/gpio/gpiolib-acpi.c:	if (!chip->parent || !chip->to_irq)
+drivers/gpio/gpiolib-acpi.c:	handle = ACPI_HANDLE(chip->parent);
+drivers/gpio/gpiolib-acpi.c:	struct gpio_chip *chip = achip->chip;
+drivers/gpio/gpiolib-acpi.c:	status = acpi_buffer_to_resource(achip->conn_info.connection,
+drivers/gpio/gpiolib-acpi.c:					 achip->conn_info.length, &ares);
+drivers/gpio/gpiolib-acpi.c:		mutex_lock(&achip->conn_lock);
+drivers/gpio/gpiolib-acpi.c:		list_for_each_entry(conn, &achip->conns, node) {
+drivers/gpio/gpiolib-acpi.c:			list_for_each_entry(event, &achip->events, node) {
+drivers/gpio/gpiolib-acpi.c:				mutex_unlock(&achip->conn_lock);
+drivers/gpio/gpiolib-acpi.c:				mutex_unlock(&achip->conn_lock);
+drivers/gpio/gpiolib-acpi.c:			list_add_tail(&conn->node, &achip->conns);
+drivers/gpio/gpiolib-acpi.c:		mutex_unlock(&achip->conn_lock);
+drivers/gpio/gpiolib-acpi.c:	struct gpio_chip *chip = achip->chip;
+drivers/gpio/gpiolib-acpi.c:	acpi_handle handle = ACPI_HANDLE(chip->parent);
+drivers/gpio/gpiolib-acpi.c:	INIT_LIST_HEAD(&achip->conns);
+drivers/gpio/gpiolib-acpi.c:	mutex_init(&achip->conn_lock);
+drivers/gpio/gpiolib-acpi.c:		dev_err(chip->parent,
+drivers/gpio/gpiolib-acpi.c:	struct gpio_chip *chip = achip->chip;
+drivers/gpio/gpiolib-acpi.c:	acpi_handle handle = ACPI_HANDLE(chip->parent);
+drivers/gpio/gpiolib-acpi.c:		dev_err(chip->parent,
+drivers/gpio/gpiolib-acpi.c:	list_for_each_entry_safe_reverse(conn, tmp, &achip->conns, node) {
+drivers/gpio/gpiolib-acpi.c:	struct gpio_chip *chip = achip->chip;
+drivers/gpio/gpiolib-acpi.c:	struct gpio_chip *chip = achip->chip;
+drivers/gpio/gpiolib-acpi.c:	device_for_each_child_node(chip->parent, fwnode) {
+drivers/gpio/gpiolib-acpi.c:			dev_err(chip->parent, "Failed to hog GPIO\n");
+drivers/gpio/gpiolib-acpi.c:	if (!chip || !chip->parent)
+drivers/gpio/gpiolib-acpi.c:	handle = ACPI_HANDLE(chip->parent);
+drivers/gpio/gpiolib-acpi.c:		dev_err(chip->parent,
+drivers/gpio/gpiolib-acpi.c:		dev_err(chip->parent, "Failed to attach ACPI GPIO chip\n");
+drivers/gpio/gpiolib-acpi.c:	if (!chip->names)
+drivers/gpio/gpiolib-acpi.c:		devprop_gpiochip_set_names(chip, dev_fwnode(chip->parent));
+drivers/gpio/gpiolib-acpi.c:	if (!chip || !chip->parent)
+drivers/gpio/gpiolib-acpi.c:	handle = ACPI_HANDLE(chip->parent);
+drivers/gpio/gpiolib-acpi.c:		dev_warn(chip->parent, "Failed to retrieve ACPI GPIO chip\n");
+drivers/gpio/gpiolib-devprop.c:	struct gpio_device *gdev = chip->gpiodev;
+drivers/gpio/gpiolib-of.c:	return chip->gpiodev->dev.of_node == gpiospec->np &&
+drivers/gpio/gpiolib-of.c:				chip->of_xlate &&
+drivers/gpio/gpiolib-of.c:				chip->of_xlate(chip, gpiospec, NULL) >= 0;
+drivers/gpio/gpiolib-of.c:	if (chip->of_gpio_n_cells != gpiospec->args_count)
+drivers/gpio/gpiolib-of.c:	ret = chip->of_xlate(chip, gpiospec, flags);
+drivers/gpio/gpiolib-of.c:	chip_np = chip->of_node;
+drivers/gpio/gpiolib-of.c:	for_each_available_child_of_node(chip->of_node, np) {
+drivers/gpio/gpiolib-of.c:	struct device_node *np = chip->of_node;
+drivers/gpio/gpiolib-of.c:		if (start >= chip->ngpio || start + count >= chip->ngpio)
+drivers/gpio/gpiolib-of.c:		bitmap_clear(chip->valid_mask, start, count);
+drivers/gpio/gpiolib-of.c:	struct device_node *np = chip->of_node;
+drivers/gpio/gpiolib-of.c:	if (!chip->of_node)
+drivers/gpio/gpiolib-of.c:	if (!chip->of_xlate) {
+drivers/gpio/gpiolib-of.c:		chip->of_gpio_n_cells = 2;
+drivers/gpio/gpiolib-of.c:		chip->of_xlate = of_gpio_simple_xlate;
+drivers/gpio/gpiolib-of.c:	if (chip->of_gpio_n_cells > MAX_PHANDLE_ARGS)
+drivers/gpio/gpiolib-of.c:	if (!chip->names)
+drivers/gpio/gpiolib-of.c:					   of_fwnode_handle(chip->of_node));
+drivers/gpio/gpiolib-of.c:	of_node_get(chip->of_node);
+drivers/gpio/gpiolib-of.c:		of_node_put(chip->of_node);
+drivers/gpio/gpiolib-of.c:	of_node_put(chip->of_node);
+drivers/gpio/gpiolib-sysfs.c:	return sprintf(buf, "%d\n", chip->base);
+drivers/gpio/gpiolib-sysfs.c:	return sprintf(buf, "%s\n", chip->label ? : "");
+drivers/gpio/gpiolib-sysfs.c:	return sprintf(buf, "%u\n", chip->ngpio);
+drivers/gpio/gpiolib-sysfs.c:	if (chip->direction_input && chip->direction_output)
+drivers/gpio/gpiolib-sysfs.c:	if (chip->names && chip->names[offset])
+drivers/gpio/gpiolib-sysfs.c:		ioname = chip->names[offset];
+drivers/gpio/gpiolib-sysfs.c:	if (chip->parent)
+drivers/gpio/gpiolib-sysfs.c:		parent = chip->parent;
+drivers/gpio/gpiolib-sysfs.c:	/* use chip->base for the ID; it's already known to be unique */
+drivers/gpio/gpiolib-sysfs.c:					"gpiochip%d", chip->base);
+drivers/gpio/gpiolib-sysfs.c:	for (i = 0; i < chip->ngpio; i++) {
+drivers/gpio/gpiolib-sysfs.c:	 * We run before arch_initcall() so chip->dev nodes can have
+drivers/gpio/gpiolib.c:	struct gpio_device *gdev = chip->gpiodev;
+drivers/gpio/gpiolib.c:	if (!chip->get_direction)
+drivers/gpio/gpiolib.c:	ret = chip->get_direction(chip, offset);
+drivers/gpio/gpiolib.c:	p = bitmap_alloc(chip->ngpio, GFP_KERNEL);
+drivers/gpio/gpiolib.c:	bitmap_fill(p, chip->ngpio);
+drivers/gpio/gpiolib.c:	bitmap_free(gpiochip->valid_mask);
+drivers/gpio/gpiolib.c:	gpiochip->valid_mask = NULL;
+drivers/gpio/gpiolib.c:	if (likely(!gpiochip->valid_mask))
+drivers/gpio/gpiolib.c:	return test_bit(offset, gpiochip->valid_mask);
+drivers/gpio/gpiolib.c:		    !pinctrl_gpio_can_use_line(chip->base + lineinfo.line_offset))
+drivers/gpio/gpiolib.c:		 dev_name(&gdev->dev), gdev->chip->label ? : "generic");
+drivers/gpio/gpiolib.c:		       __func__, chip->label, hog->chip_hwnum, rv);
+drivers/gpio/gpiolib.c:		if (!strcmp(chip->label, hog->chip_label))
+drivers/gpio/gpiolib.c:	int		base = chip->base;
+drivers/gpio/gpiolib.c:	chip->gpiodev = gdev;
+drivers/gpio/gpiolib.c:	if (chip->parent) {
+drivers/gpio/gpiolib.c:		gdev->dev.parent = chip->parent;
+drivers/gpio/gpiolib.c:		gdev->dev.of_node = chip->parent->of_node;
+drivers/gpio/gpiolib.c:	if (chip->of_node)
+drivers/gpio/gpiolib.c:		gdev->dev.of_node = chip->of_node;
+drivers/gpio/gpiolib.c:		chip->of_node = gdev->dev.of_node;
+drivers/gpio/gpiolib.c:	if (chip->parent && chip->parent->driver)
+drivers/gpio/gpiolib.c:		gdev->owner = chip->parent->driver->owner;
+drivers/gpio/gpiolib.c:	else if (chip->owner)
+drivers/gpio/gpiolib.c:		/* TODO: remove chip->owner */
+drivers/gpio/gpiolib.c:		gdev->owner = chip->owner;
+drivers/gpio/gpiolib.c:	gdev->descs = kcalloc(chip->ngpio, sizeof(gdev->descs[0]), GFP_KERNEL);
+drivers/gpio/gpiolib.c:	if (chip->ngpio == 0) {
+drivers/gpio/gpiolib.c:	if (chip->ngpio > FASTPATH_NGPIO)
+drivers/gpio/gpiolib.c:		chip->ngpio, FASTPATH_NGPIO);
+drivers/gpio/gpiolib.c:	gdev->label = kstrdup_const(chip->label ?: "unknown", GFP_KERNEL);
+drivers/gpio/gpiolib.c:	gdev->ngpio = chip->ngpio;
+drivers/gpio/gpiolib.c:		base = gpiochip_find_base(chip->ngpio);
+drivers/gpio/gpiolib.c:		chip->base = base;
+drivers/gpio/gpiolib.c:	for (i = 0; i < chip->ngpio; i++)
+drivers/gpio/gpiolib.c:	for (i = 0; i < chip->ngpio; i++) {
+drivers/gpio/gpiolib.c:		if (chip->get_direction && gpiochip_line_is_valid(chip, i)) {
+drivers/gpio/gpiolib.c:			if (!chip->get_direction(chip, i))
+drivers/gpio/gpiolib.c:			if (!chip->direction_input)
+drivers/gpio/gpiolib.c:	       chip->label ? : "generic", ret);
+drivers/gpio/gpiolib.c:	return chip->gpiodev->data;
+drivers/gpio/gpiolib.c:	struct gpio_device *gdev = chip->gpiodev;
+drivers/gpio/gpiolib.c: * @chip: the chip to register, with chip->base initialized
+drivers/gpio/gpiolib.c: * chip->base is invalid or already associated with a different chip.
+drivers/gpio/gpiolib.c:	return !strcmp(chip->label, name);
+drivers/gpio/gpiolib.c:	bitmap_free(gpiochip->irq.valid_mask);
+drivers/gpio/gpiolib.c:	gpiochip->irq.valid_mask = NULL;
+drivers/gpio/gpiolib.c:	if (likely(!gpiochip->irq.valid_mask))
+drivers/gpio/gpiolib.c:	return test_bit(offset, gpiochip->irq.valid_mask);
+drivers/gpio/gpiolib.c:	if (gpiochip->irq.threaded) {
+drivers/gpio/gpiolib.c:	irq_set_lockdep_class(irq, chip->irq.lock_key, chip->irq.request_key);
+drivers/gpio/gpiolib.c:	irq_set_chip_and_handler(irq, chip->irq.chip, chip->irq.handler);
+drivers/gpio/gpiolib.c:	if (chip->irq.threaded)
+drivers/gpio/gpiolib.c:	if (chip->irq.num_parents == 1)
+drivers/gpio/gpiolib.c:		ret = irq_set_parent(irq, chip->irq.parents[0]);
+drivers/gpio/gpiolib.c:	else if (chip->irq.map)
+drivers/gpio/gpiolib.c:		ret = irq_set_parent(irq, chip->irq.map[hwirq]);
+drivers/gpio/gpiolib.c:	if (chip->irq.default_type != IRQ_TYPE_NONE)
+drivers/gpio/gpiolib.c:		irq_set_irq_type(irq, chip->irq.default_type);
+drivers/gpio/gpiolib.c:	if (chip->irq.threaded)
+drivers/gpio/gpiolib.c:	struct irq_domain *domain = chip->irq.domain;
+drivers/gpio/gpiolib.c:		spec.param[0] = chip->irq.child_offset_to_irq(chip, offset);
+drivers/gpio/gpiolib.c:	if (chip->irq.irq_enable)
+drivers/gpio/gpiolib.c:		chip->irq.irq_enable(d);
+drivers/gpio/gpiolib.c:		chip->irq.chip->irq_unmask(d);
+drivers/gpio/gpiolib.c:	if (chip->irq.irq_disable)
+drivers/gpio/gpiolib.c:		chip->irq.irq_disable(d);
+drivers/gpio/gpiolib.c:		chip->irq.chip->irq_mask(d);
+drivers/gpio/gpiolib.c:	struct irq_chip *irqchip = gpiochip->irq.chip;
+drivers/gpio/gpiolib.c:	if (!irqchip->irq_request_resources &&
+drivers/gpio/gpiolib.c:	    !irqchip->irq_release_resources) {
+drivers/gpio/gpiolib.c:		irqchip->irq_request_resources = gpiochip_irq_reqres;
+drivers/gpio/gpiolib.c:		irqchip->irq_release_resources = gpiochip_irq_relres;
+drivers/gpio/gpiolib.c:	if (WARN_ON(gpiochip->irq.irq_enable))
+drivers/gpio/gpiolib.c:	if (irqchip->irq_enable == gpiochip_irq_enable) {
+drivers/gpio/gpiolib.c:	gpiochip->irq.irq_enable = irqchip->irq_enable;
+drivers/gpio/gpiolib.c:	gpiochip->irq.irq_disable = irqchip->irq_disable;
+drivers/gpio/gpiolib.c:	irqchip->irq_enable = gpiochip_irq_enable;
+drivers/gpio/gpiolib.c:	irqchip->irq_disable = gpiochip_irq_disable;
+drivers/gpio/gpiolib.c:	struct irq_chip *irqchip = gpiochip->irq.chip;
+drivers/gpio/gpiolib.c:	if (gpiochip->irq.parent_handler && gpiochip->can_sleep) {
+drivers/gpio/gpiolib.c:	np = gpiochip->gpiodev->dev.of_node;
+drivers/gpio/gpiolib.c:	type = gpiochip->irq.default_type;
+drivers/gpio/gpiolib.c:	if (has_acpi_companion(gpiochip->parent) && type != IRQ_TYPE_NONE) {
+drivers/gpio/gpiolib.c:		acpi_handle_warn(ACPI_HANDLE(gpiochip->parent),
+drivers/gpio/gpiolib.c:	gpiochip->to_irq = gpiochip_to_irq;
+drivers/gpio/gpiolib.c:	gpiochip->irq.default_type = type;
+drivers/gpio/gpiolib.c:	gpiochip->irq.lock_key = lock_key;
+drivers/gpio/gpiolib.c:	gpiochip->irq.request_key = request_key;
+drivers/gpio/gpiolib.c:		if (gpiochip->irq.domain_ops)
+drivers/gpio/gpiolib.c:			ops = gpiochip->irq.domain_ops;
+drivers/gpio/gpiolib.c:		gpiochip->irq.domain = irq_domain_add_simple(np,
+drivers/gpio/gpiolib.c:			gpiochip->ngpio,
+drivers/gpio/gpiolib.c:			gpiochip->irq.first,
+drivers/gpio/gpiolib.c:		if (!gpiochip->irq.domain)
+drivers/gpio/gpiolib.c:	if (gpiochip->irq.parent_handler) {
+drivers/gpio/gpiolib.c:		void *data = gpiochip->irq.parent_handler_data ?: gpiochip;
+drivers/gpio/gpiolib.c:		for (i = 0; i < gpiochip->irq.num_parents; i++) {
+drivers/gpio/gpiolib.c:			irq_set_chained_handler_and_data(gpiochip->irq.parents[i],
+drivers/gpio/gpiolib.c:							 gpiochip->irq.parent_handler,
+drivers/gpio/gpiolib.c:	struct irq_chip *irqchip = gpiochip->irq.chip;
+drivers/gpio/gpiolib.c:	if (irqchip && gpiochip->irq.parent_handler) {
+drivers/gpio/gpiolib.c:		struct gpio_irq_chip *irq = &gpiochip->irq;
+drivers/gpio/gpiolib.c:	if (gpiochip->irq.domain) {
+drivers/gpio/gpiolib.c:		for (offset = 0; offset < gpiochip->ngpio; offset++) {
+drivers/gpio/gpiolib.c:			irq = irq_find_mapping(gpiochip->irq.domain, offset);
+drivers/gpio/gpiolib.c:		irq_domain_remove(gpiochip->irq.domain);
+drivers/gpio/gpiolib.c:		if (irqchip->irq_request_resources == gpiochip_irq_reqres) {
+drivers/gpio/gpiolib.c:			irqchip->irq_request_resources = NULL;
+drivers/gpio/gpiolib.c:			irqchip->irq_release_resources = NULL;
+drivers/gpio/gpiolib.c:		if (irqchip->irq_enable == gpiochip_irq_enable) {
+drivers/gpio/gpiolib.c:			irqchip->irq_enable = gpiochip->irq.irq_enable;
+drivers/gpio/gpiolib.c:			irqchip->irq_disable = gpiochip->irq.irq_disable;
+drivers/gpio/gpiolib.c:	gpiochip->irq.irq_enable = NULL;
+drivers/gpio/gpiolib.c:	gpiochip->irq.irq_disable = NULL;
+drivers/gpio/gpiolib.c:	gpiochip->irq.chip = NULL;
+drivers/gpio/gpiolib.c:	if (!gpiochip->parent) {
+drivers/gpio/gpiolib.c:	gpiochip->irq.threaded = threaded;
+drivers/gpio/gpiolib.c:	of_node = gpiochip->parent->of_node;
+drivers/gpio/gpiolib.c:	 * FIXME: get rid of this and use gpiochip->parent->of_node
+drivers/gpio/gpiolib.c:	if (gpiochip->of_node)
+drivers/gpio/gpiolib.c:		of_node = gpiochip->of_node;
+drivers/gpio/gpiolib.c:	if (has_acpi_companion(gpiochip->parent) && type != IRQ_TYPE_NONE) {
+drivers/gpio/gpiolib.c:		acpi_handle_warn(ACPI_HANDLE(gpiochip->parent),
+drivers/gpio/gpiolib.c:	gpiochip->irq.chip = irqchip;
+drivers/gpio/gpiolib.c:	gpiochip->irq.handler = handler;
+drivers/gpio/gpiolib.c:	gpiochip->irq.default_type = type;
+drivers/gpio/gpiolib.c:	gpiochip->to_irq = gpiochip_to_irq;
+drivers/gpio/gpiolib.c:	gpiochip->irq.lock_key = lock_key;
+drivers/gpio/gpiolib.c:	gpiochip->irq.request_key = request_key;
+drivers/gpio/gpiolib.c:	gpiochip->irq.domain = irq_domain_add_simple(of_node,
+drivers/gpio/gpiolib.c:					gpiochip->ngpio, first_irq,
+drivers/gpio/gpiolib.c:	if (!gpiochip->irq.domain) {
+drivers/gpio/gpiolib.c:		gpiochip->irq.chip = NULL;
+drivers/gpio/gpiolib.c:	return pinctrl_gpio_request(chip->gpiodev->base + offset);
+drivers/gpio/gpiolib.c:	pinctrl_gpio_free(chip->gpiodev->base + offset);
+drivers/gpio/gpiolib.c:	return pinctrl_gpio_set_config(chip->gpiodev->base + offset, config);
+drivers/gpio/gpiolib.c:	struct gpio_device *gdev = chip->gpiodev;
+drivers/gpio/gpiolib.c:	pin_range->range.name = chip->label;
+drivers/gpio/gpiolib.c:	struct gpio_device *gdev = chip->gpiodev;
+drivers/gpio/gpiolib.c:	pin_range->range.name = chip->label;
+drivers/gpio/gpiolib.c:	struct gpio_device *gdev = chip->gpiodev;
+drivers/gpio/gpiolib.c:	if (chip->request) {
+drivers/gpio/gpiolib.c:		/* chip->request may sleep */
+drivers/gpio/gpiolib.c:			ret = chip->request(chip, offset);
+drivers/gpio/gpiolib.c:	if (chip->get_direction) {
+drivers/gpio/gpiolib.c:		/* chip->get_direction may sleep */
+drivers/gpio/gpiolib.c:		if (chip->free) {
+drivers/gpio/gpiolib.c:			might_sleep_if(chip->can_sleep);
+drivers/gpio/gpiolib.c:			chip->free(chip, gpio_chip_hwgpio(desc));
+drivers/gpio/gpiolib.c:	if (offset >= chip->ngpio)
+drivers/gpio/gpiolib.c:	desc = &chip->gpiodev->descs[offset];
+drivers/gpio/gpiolib.c:	if (!chip->get && chip->direction_input) {
+drivers/gpio/gpiolib.c:	if (chip->direction_input) {
+drivers/gpio/gpiolib.c:		ret = chip->direction_input(chip, gpio_chip_hwgpio(desc));
+drivers/gpio/gpiolib.c:	} else if (chip->get_direction &&
+drivers/gpio/gpiolib.c:		  (chip->get_direction(chip, gpio_chip_hwgpio(desc)) != 1)) {
+drivers/gpio/gpiolib.c:	if (!chip->set || !chip->set_config) {
+drivers/gpio/gpiolib.c:	return chip->set_config(chip, gpio_chip_hwgpio(desc), config);
+drivers/gpio/gpiolib.c:	if (!chip->set_config)
+drivers/gpio/gpiolib.c:	rc = chip->set_config(chip, gpio, packed);
+drivers/gpio/gpiolib.c:	value = chip->get ? chip->get(chip, offset) : -EIO;
+drivers/gpio/gpiolib.c:	if (chip->get_multiple) {
+drivers/gpio/gpiolib.c:		return chip->get_multiple(chip, mask, bits);
+drivers/gpio/gpiolib.c:	} else if (chip->get) {
+drivers/gpio/gpiolib.c:		for_each_set_bit(i, mask, chip->ngpio) {
+drivers/gpio/gpiolib.c:			value = chip->get(chip, i);
+drivers/gpio/gpiolib.c:			WARN_ON(array_info->chip->can_sleep);
+drivers/gpio/gpiolib.c:		if (likely(chip->ngpio <= FASTPATH_NGPIO)) {
+drivers/gpio/gpiolib.c:			mask = kmalloc_array(2 * BITS_TO_LONGS(chip->ngpio),
+drivers/gpio/gpiolib.c:		bits = mask + BITS_TO_LONGS(chip->ngpio);
+drivers/gpio/gpiolib.c:		bitmap_zero(mask, chip->ngpio);
+drivers/gpio/gpiolib.c:			WARN_ON(chip->can_sleep);
+drivers/gpio/gpiolib.c:	WARN_ON(desc->gdev->chip->can_sleep);
+drivers/gpio/gpiolib.c:	WARN_ON(desc->gdev->chip->can_sleep);
+drivers/gpio/gpiolib.c:		ret = chip->direction_input(chip, offset);
+drivers/gpio/gpiolib.c:		ret = chip->direction_output(chip, offset, 0);
+drivers/gpio/gpiolib.c:		ret = chip->direction_output(chip, offset, 1);
+drivers/gpio/gpiolib.c:		ret = chip->direction_input(chip, offset);
+drivers/gpio/gpiolib.c:	chip->set(chip, gpio_chip_hwgpio(desc), value);
+drivers/gpio/gpiolib.c:	if (chip->set_multiple) {
+drivers/gpio/gpiolib.c:		chip->set_multiple(chip, mask, bits);
+drivers/gpio/gpiolib.c:		for_each_set_bit(i, mask, chip->ngpio)
+drivers/gpio/gpiolib.c:			chip->set(chip, i, test_bit(i, bits));
+drivers/gpio/gpiolib.c:			WARN_ON(array_info->chip->can_sleep);
+drivers/gpio/gpiolib.c:		if (likely(chip->ngpio <= FASTPATH_NGPIO)) {
+drivers/gpio/gpiolib.c:			mask = kmalloc_array(2 * BITS_TO_LONGS(chip->ngpio),
+drivers/gpio/gpiolib.c:		bits = mask + BITS_TO_LONGS(chip->ngpio);
+drivers/gpio/gpiolib.c:		bitmap_zero(mask, chip->ngpio);
+drivers/gpio/gpiolib.c:			WARN_ON(chip->can_sleep);
+drivers/gpio/gpiolib.c:	WARN_ON(desc->gdev->chip->can_sleep);
+drivers/gpio/gpiolib.c:	WARN_ON(desc->gdev->chip->can_sleep);
+drivers/gpio/gpiolib.c:	return desc->gdev->chip->can_sleep;
+drivers/gpio/gpiolib.c:	if (chip->to_irq) {
+drivers/gpio/gpiolib.c:		int retirq = chip->to_irq(chip, offset);
+drivers/gpio/gpiolib.c:	if (!chip->can_sleep && chip->get_direction) {
+drivers/gpio/gpiolib.c:	if (offset >= chip->ngpio)
+drivers/gpio/gpiolib.c:	return test_bit(FLAG_USED_AS_IRQ, &chip->gpiodev->descs[offset].flags);
+drivers/gpio/gpiolib.c:	if (!try_module_get(chip->gpiodev->owner))
+drivers/gpio/gpiolib.c:		module_put(chip->gpiodev->owner);
+drivers/gpio/gpiolib.c:	module_put(chip->gpiodev->owner);
+drivers/gpio/gpiolib.c:	if (offset >= chip->ngpio)
+drivers/gpio/gpiolib.c:	return test_bit(FLAG_OPEN_DRAIN, &chip->gpiodev->descs[offset].flags);
+drivers/gpio/gpiolib.c:	if (offset >= chip->ngpio)
+drivers/gpio/gpiolib.c:	return test_bit(FLAG_OPEN_SOURCE, &chip->gpiodev->descs[offset].flags);
+drivers/gpio/gpiolib.c:	if (offset >= chip->ngpio)
+drivers/gpio/gpiolib.c:	return !test_bit(FLAG_TRANSITORY, &chip->gpiodev->descs[offset].flags);
+drivers/gpio/gpiolib.c:		if (chip->ngpio <= p->chip_hwnum) {
+drivers/gpio/gpiolib.c:				idx, p->chip_hwnum, chip->ngpio - 1,
+drivers/gpio/gpiolib.c:				chip->label);
+drivers/gpio/gpiolib.c:		       name, chip->label, hwnum, ret);
+drivers/gpio/gpiolib.c:	for (id = 0; id < chip->ngpio; id++) {
+drivers/gpio/gpiolib.c:		if (test_bit(FLAG_IS_HOGGED, &chip->gpiodev->descs[id].flags))
+drivers/gpio/gpiolib.c:			gpiochip_free_own_desc(&chip->gpiodev->descs[id]);
+drivers/gpio/gpiolib.c:			bitmap_size = BITS_TO_LONGS(chip->ngpio > count ?
+drivers/gpio/gpiolib.c:						    chip->ngpio : count);
+drivers/gpio/gpiolib.c:			array_info->chip->label, array_info->size,
+drivers/gpio/gpiolib.c:			chip->get ? (chip->get(chip, i) ? "hi" : "lo") : "?  ",
+drivers/gpio/gpiolib.c:	parent = chip->parent;
+drivers/gpio/gpiolib.c:	if (chip->label)
+drivers/gpio/gpiolib.c:		seq_printf(s, ", %s", chip->label);
+drivers/gpio/gpiolib.c:	if (chip->can_sleep)
+drivers/gpio/gpiolib.c:	if (chip->dbg_show)
+drivers/gpio/gpiolib.c:		chip->dbg_show(s, chip);
+drivers/gpio/gpiolib.h:	dev_emerg(&chip->gpiodev->dev, "(%s): " fmt, chip->label, ##__VA_ARGS__)
+drivers/gpio/gpiolib.h:	dev_crit(&chip->gpiodev->dev, "(%s): " fmt, chip->label, ##__VA_ARGS__)
+drivers/gpio/gpiolib.h:	dev_err(&chip->gpiodev->dev, "(%s): " fmt, chip->label, ##__VA_ARGS__)
+drivers/gpio/gpiolib.h:	dev_warn(&chip->gpiodev->dev, "(%s): " fmt, chip->label, ##__VA_ARGS__)
+drivers/gpio/gpiolib.h:	dev_info(&chip->gpiodev->dev, "(%s): " fmt, chip->label, ##__VA_ARGS__)
+drivers/gpio/gpiolib.h:	dev_dbg(&chip->gpiodev->dev, "(%s): " fmt, chip->label, ##__VA_ARGS__)
+drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c:	chip->arch_id	= malidp_read32(reg_base, GLB_ARCH_ID);
+drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c:	chip->core_id	= malidp_read32(reg_base, GLB_CORE_ID);
+drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c:	chip->core_info	= malidp_read32(reg_base, GLB_CORE_INFO);
+drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c:	chip->bus_width	= D71_BUS_WIDTH_16_BYTES;
+drivers/gpu/drm/nouveau/dispnv04/nvreg.h:#	define NV_CIO_CRE_59			0x59	/* related to on/off-chip-ness of digital outputs */
+drivers/gpu/drm/nouveau/nvkm/core/firmware.c:	strncpy(cname, device->chip->name, sizeof(cname));
+drivers/gpu/drm/nouveau/nvkm/engine/device/base.c:			   device->chip->name, boot0);
+drivers/gpu/drm/nouveau/nvkm/engine/device/base.c:		device->name = device->chip->name;
+drivers/gpu/drm/nouveau/nvkm/engine/device/base.c:	if (device->chip->m && (subdev_mask & (1ULL << (s)))) {                \
+drivers/gpu/drm/nouveau/nvkm/engine/device/base.c:		ret = device->chip->m(device, (s), &device->m);                \
+drivers/gpu/drm/nouveau/nvkm/engine/device/user.c:	strncpy(args->v0.chip, device->chip->name, sizeof(args->v0.chip));
+drivers/gpu/drm/nouveau/nvkm/subdev/secboot/base.c:	/* Call chip-specific init function */
+drivers/gpu/drm/rockchip/analogix_dp-rockchip.c:		   .name = "rockchip-dp",
+drivers/gpu/drm/rockchip/rk3066_hdmi.c:		.name = "rockchip-rk3066-hdmi",
+drivers/gpu/drm/rockchip/rockchip_drm_drv.c:		.name = "rockchip-drm",
+drivers/gpu/drm/rockchip/rockchip_lvds.c:		   .name = "rockchip-lvds",
+drivers/gpu/drm/rockchip/rockchip_vop_reg.c:		.name = "rockchip-vop",
+drivers/hwmon/ad7314.c:	ret = spi_read(chip->spi_dev, (u8 *)&chip->rx, sizeof(chip->rx));
+drivers/hwmon/ad7314.c:		dev_err(&chip->spi_dev->dev, "SPI read error\n");
+drivers/hwmon/ad7314.c:	return be16_to_cpu(chip->rx);
+drivers/hwmon/ad7314.c:	switch (spi_get_device_id(chip->spi_dev)->driver_data) {
+drivers/hwmon/ad7314.c:	chip->spi_dev = spi_dev;
+drivers/hwmon/dme1737.c:/* chip-dependent features */
+drivers/hwmon/dme1737.c:	/* Create chip-dependent sysfs attributes */
+drivers/hwmon/dme1737.c:		/* Change permissions of chip-dependent sysfs attributes */
+drivers/hwmon/hwmon.c:	ret = hwdev->chip->ops->read(&hwdev->dev, hwmon_temp, hwmon_temp_input,
+drivers/hwmon/hwmon.c:	for (i = 0; chip->info[i]; i++)
+drivers/hwmon/hwmon.c:		nattrs += hwmon_num_channel_attrs(chip->info[i]);
+drivers/hwmon/hwmon.c:	for (i = 0; chip->info[i]; i++) {
+drivers/hwmon/hwmon.c:		ret = hwmon_genattrs(dev, drvdata, &attrs[aindex], chip->ops,
+drivers/hwmon/hwmon.c:				     chip->info[i]);
+drivers/hwmon/hwmon.c:	if (dev && dev->of_node && chip && chip->ops->read &&
+drivers/hwmon/hwmon.c:	    chip->info[0]->type == hwmon_chip &&
+drivers/hwmon/hwmon.c:	    (chip->info[0]->config[0] & HWMON_C_REGISTER_TZ)) {
+drivers/hwmon/hwmon.c:		const struct hwmon_channel_info **info = chip->info;
+drivers/hwmon/hwmon.c:				if (!chip->ops->is_visible(drvdata, hwmon_temp,
+drivers/hwmon/hwmon.c:	if (chip && (!chip->ops || !chip->ops->is_visible || !chip->info))
+drivers/hwmon/ibmpowernv.c:	if (!of_property_read_u32(np, "ibm,chip-id", &id))
+drivers/hwmon/jc42.c:		if (manid == chip->manid &&
+drivers/hwmon/jc42.c:		    (devid & chip->devid_mask) == chip->devid) {
+drivers/hwmon/max6697.c:	for (i = 0; i < data->chip->channels; i++) {
+drivers/hwmon/max6697.c:		if (data->chip->have_ext & (1 << i)) {
+drivers/hwmon/max6697.c:		if (data->chip->have_crit & (1 << i)) {
+drivers/hwmon/max6697.c:	if (data->chip->alarm_map)
+drivers/hwmon/max6697.c:		index = data->chip->alarm_map[index];
+drivers/hwmon/max6697.c:	if (channel >= chip->channels)
+drivers/hwmon/max6697.c:	if ((nr == 3 || nr == 4) && !(chip->have_crit & (1 << channel)))
+drivers/hwmon/max6697.c:	if (nr == 5 && !(chip->have_fault & (1 << channel)))
+drivers/hwmon/max6697.c:	int factor = chip->channels;
+drivers/hwmon/max6697.c:	    (chip->valid_conf & MAX6697_CONF_TIMEOUT)) {
+drivers/hwmon/max6697.c:	    (chip->valid_conf & MAX6581_CONF_EXTENDED)) {
+drivers/hwmon/max6697.c:	    (chip->valid_conf & MAX6697_CONF_RESISTANCE)) {
+drivers/hwmon/max6697.c:	    (chip->valid_conf & MAX6693_CONF_BETA)) {
+drivers/hwmon/tmp401.c: * temperature measured since power-on, chip-reset, or
+drivers/hwmon/w83627hf.c:	/* Register chip-specific device attributes */
+drivers/i2c/busses/i2c-i801.c:	unsigned gpios[2];		/* Relative to gpio_chip->base */
+drivers/i2c/i2c-stub.c:	list_for_each_entry(b, &chip->smbus_blocks, node) {
+drivers/i2c/i2c-stub.c:		list_add(&rb->node, &chip->smbus_blocks);
+drivers/i2c/i2c-stub.c:	if (chip->bank_sel &&
+drivers/i2c/i2c-stub.c:	    offset >= chip->bank_start && offset <= chip->bank_end)
+drivers/i2c/i2c-stub.c:		return chip->bank_words +
+drivers/i2c/i2c-stub.c:		       (chip->bank_sel - 1) * chip->bank_size +
+drivers/i2c/i2c-stub.c:		       offset - chip->bank_start;
+drivers/i2c/i2c-stub.c:		return chip->words + offset;
+drivers/i2c/i2c-stub.c:			chip->pointer = command;
+drivers/i2c/i2c-stub.c:			wordp = stub_get_wordp(chip, chip->pointer++);
+drivers/i2c/i2c-stub.c:			if (chip->bank_words && command == chip->bank_reg) {
+drivers/i2c/i2c-stub.c:				chip->bank_sel =
+drivers/i2c/i2c-stub.c:					(data->byte >> chip->bank_shift)
+drivers/i2c/i2c-stub.c:					& chip->bank_mask;
+drivers/i2c/i2c-stub.c:					chip->bank_sel);
+drivers/i2c/i2c-stub.c:		chip->pointer = command + 1;
+drivers/i2c/i2c-stub.c:				chip->words[command + i] &= 0xff00;
+drivers/i2c/i2c-stub.c:				chip->words[command + i] |= data->block[1 + i];
+drivers/i2c/i2c-stub.c:					chip->words[command + i] & 0xff;
+drivers/i2c/i2c-stub.c:			chip->words[command] = (b->block[0] << 8) | b->len;
+drivers/i2c/i2c-stub.c:	chip->bank_reg = bank_reg[i];
+drivers/i2c/i2c-stub.c:	chip->bank_start = bank_start[i];
+drivers/i2c/i2c-stub.c:	chip->bank_end = bank_end[i];
+drivers/i2c/i2c-stub.c:	chip->bank_size = bank_end[i] - bank_start[i] + 1;
+drivers/i2c/i2c-stub.c:	chip->bank_mask = bank_mask[i];
+drivers/i2c/i2c-stub.c:	while (!(chip->bank_mask & 1)) {
+drivers/i2c/i2c-stub.c:		chip->bank_shift++;
+drivers/i2c/i2c-stub.c:		chip->bank_mask >>= 1;
+drivers/i2c/i2c-stub.c:	chip->bank_words = kcalloc(chip->bank_mask * chip->bank_size,
+drivers/i2c/i2c-stub.c:	if (!chip->bank_words)
+drivers/i2c/i2c-stub.c:		 chip->bank_mask, chip->bank_size, chip->bank_start,
+drivers/i2c/i2c-stub.c:		 chip->bank_end);
+drivers/i2c/muxes/i2c-mux-ltc4306.c:	if (!data->chip->num_gpios)
+drivers/i2c/muxes/i2c-mux-ltc4306.c:	data->gpiochip.ngpio = data->chip->num_gpios;
+drivers/i2c/muxes/i2c-mux-ltc4306.c:			     chip->nchans, sizeof(*data),
+drivers/i2c/muxes/i2c-mux-ltc4306.c:	for (num = 0; num < chip->nchans; num++) {
+drivers/i2c/muxes/i2c-mux-pca954x.c:	if (chip->muxtype == pca954x_ismux)
+drivers/i2c/muxes/i2c-mux-pca954x.c:		regval = chan | chip->enable;
+drivers/i2c/muxes/i2c-mux-pca954x.c:	    (val < 0 || val >= data->chip->nchans))
+drivers/i2c/muxes/i2c-mux-pca954x.c:	for (i = 0; i < data->chip->nchans; i++) {
+drivers/i2c/muxes/i2c-mux-pca954x.c:	if (!data->chip->has_irq || client->irq <= 0)
+drivers/i2c/muxes/i2c-mux-pca954x.c:					  data->chip->nchans,
+drivers/i2c/muxes/i2c-mux-pca954x.c:	for (c = 0; c < data->chip->nchans; c++) {
+drivers/i2c/muxes/i2c-mux-pca954x.c:		for (c = 0; c < data->chip->nchans; c++) {
+drivers/i2c/muxes/i2c-mux-pca954x.c:	if (data->chip->id.manufacturer_id != I2C_DEVICE_ID_NONE) {
+drivers/i2c/muxes/i2c-mux-pca954x.c:		    (id.manufacturer_id != data->chip->id.manufacturer_id ||
+drivers/i2c/muxes/i2c-mux-pca954x.c:		     id.part_id != data->chip->id.part_id)) {
+drivers/i2c/muxes/i2c-mux-pca954x.c:	for (num = 0; num < data->chip->nchans; num++) {
+drivers/i2c/muxes/i2c-mux-pca954x.c:		 num, data->chip->muxtype == pca954x_ismux
+drivers/iio/accel/mc3230.c:	/* First check chip-id and product-id */
+drivers/iio/adc/ad7291.c:	struct i2c_client *client = chip->client;
+drivers/iio/adc/ad7291.c:	return i2c_smbus_write_word_swapped(chip->client, reg, data);
+drivers/iio/adc/ad7291.c:	command = chip->command | AD7291_ALERT_CLEAR;
+drivers/iio/adc/ad7291.c:	command = chip->command & ~AD7291_ALERT_CLEAR;
+drivers/iio/adc/ad7291.c:		return !!(chip->c_mask & BIT(15 - chan->channel));
+drivers/iio/adc/ad7291.c:	mutex_lock(&chip->state_lock);
+drivers/iio/adc/ad7291.c:	regval = chip->command;
+drivers/iio/adc/ad7291.c:		if ((!state) && (chip->c_mask & mask))
+drivers/iio/adc/ad7291.c:			chip->c_mask &= ~mask;
+drivers/iio/adc/ad7291.c:		else if (state && (!(chip->c_mask & mask)))
+drivers/iio/adc/ad7291.c:			chip->c_mask |= mask;
+drivers/iio/adc/ad7291.c:		regval |= chip->c_mask;
+drivers/iio/adc/ad7291.c:		if (chip->c_mask) /* Enable autocycle? */
+drivers/iio/adc/ad7291.c:		chip->command = regval;
+drivers/iio/adc/ad7291.c:	mutex_unlock(&chip->state_lock);
+drivers/iio/adc/ad7291.c:			mutex_lock(&chip->state_lock);
+drivers/iio/adc/ad7291.c:			if (chip->command & AD7291_AUTOCYCLE) {
+drivers/iio/adc/ad7291.c:				mutex_unlock(&chip->state_lock);
+drivers/iio/adc/ad7291.c:			regval = chip->command & (~AD7291_VOLTAGE_MASK);
+drivers/iio/adc/ad7291.c:				mutex_unlock(&chip->state_lock);
+drivers/iio/adc/ad7291.c:			ret = i2c_smbus_read_word_swapped(chip->client,
+drivers/iio/adc/ad7291.c:				mutex_unlock(&chip->state_lock);
+drivers/iio/adc/ad7291.c:			mutex_unlock(&chip->state_lock);
+drivers/iio/adc/ad7291.c:			ret = i2c_smbus_read_word_swapped(chip->client,
+drivers/iio/adc/ad7291.c:		ret = i2c_smbus_read_word_swapped(chip->client,
+drivers/iio/adc/ad7291.c:			if (chip->reg) {
+drivers/iio/adc/ad7291.c:				vref = regulator_get_voltage(chip->reg);
+drivers/iio/adc/ad7291.c:		chip->reg = devm_regulator_get(&client->dev, "vref");
+drivers/iio/adc/ad7291.c:		if (IS_ERR(chip->reg))
+drivers/iio/adc/ad7291.c:			return PTR_ERR(chip->reg);
+drivers/iio/adc/ad7291.c:		ret = regulator_enable(chip->reg);
+drivers/iio/adc/ad7291.c:	mutex_init(&chip->state_lock);
+drivers/iio/adc/ad7291.c:	chip->client = client;
+drivers/iio/adc/ad7291.c:	chip->command = AD7291_NOISE_DELAY |
+drivers/iio/adc/ad7291.c:		chip->command |= AD7291_EXT_REF;
+drivers/iio/adc/ad7291.c:	ret = ad7291_i2c_write(chip, AD7291_COMMAND, chip->command);
+drivers/iio/adc/ad7291.c:	if (chip->reg)
+drivers/iio/adc/ad7291.c:		regulator_disable(chip->reg);
+drivers/iio/adc/ad7291.c:	if (chip->reg)
+drivers/iio/adc/ad7291.c:		regulator_disable(chip->reg);
+drivers/iio/adc/ina2xx-adc.c:		ret = regmap_read(chip->regmap, chan->address, &regval);
+drivers/iio/adc/ina2xx-adc.c:			*val >>= chip->config->bus_voltage_shift;
+drivers/iio/adc/ina2xx-adc.c:		*val = chip->avg;
+drivers/iio/adc/ina2xx-adc.c:			*val2 = chip->int_time_vshunt;
+drivers/iio/adc/ina2xx-adc.c:			*val2 = chip->int_time_vbus;
+drivers/iio/adc/ina2xx-adc.c:			*val = chip->config->shunt_voltage_lsb;
+drivers/iio/adc/ina2xx-adc.c:			*val = chip->config->bus_voltage_lsb;
+drivers/iio/adc/ina2xx-adc.c:			*val = chip->config->shunt_voltage_lsb;
+drivers/iio/adc/ina2xx-adc.c:			*val2 = chip->shunt_resistor_uohm;
+drivers/iio/adc/ina2xx-adc.c:			*val = chip->config->power_lsb_factor *
+drivers/iio/adc/ina2xx-adc.c:			       chip->config->shunt_voltage_lsb;
+drivers/iio/adc/ina2xx-adc.c:			*val2 = chip->shunt_resistor_uohm;
+drivers/iio/adc/ina2xx-adc.c:			*val = chip->pga_gain_vshunt;
+drivers/iio/adc/ina2xx-adc.c:			*val = chip->range_vbus == 32 ? 1 : 2;
+drivers/iio/adc/ina2xx-adc.c:	chip->avg = ina226_avg_tab[bits];
+drivers/iio/adc/ina2xx-adc.c:	chip->int_time_vbus = ina226_conv_time_tab[bits];
+drivers/iio/adc/ina2xx-adc.c:	chip->int_time_vshunt = ina226_conv_time_tab[bits];
+drivers/iio/adc/ina2xx-adc.c:	chip->int_time_vbus = val_us_best;
+drivers/iio/adc/ina2xx-adc.c:	chip->int_time_vshunt = val_us_best;
+drivers/iio/adc/ina2xx-adc.c:		chip->range_vbus = 32;
+drivers/iio/adc/ina2xx-adc.c:		chip->range_vbus = 16;
+drivers/iio/adc/ina2xx-adc.c:	chip->pga_gain_vshunt = ina219_vshunt_gain_tab[bits];
+drivers/iio/adc/ina2xx-adc.c:	mutex_lock(&chip->state_lock);
+drivers/iio/adc/ina2xx-adc.c:	ret = regmap_read(chip->regmap, INA2XX_CONFIG, &config);
+drivers/iio/adc/ina2xx-adc.c:		if (chip->config->chip_id == ina226) {
+drivers/iio/adc/ina2xx-adc.c:		ret = regmap_write(chip->regmap, INA2XX_CONFIG, tmp);
+drivers/iio/adc/ina2xx-adc.c:	mutex_unlock(&chip->state_lock);
+drivers/iio/adc/ina2xx-adc.c:	return sprintf(buf, "%d\n", chip->allow_async_readout);
+drivers/iio/adc/ina2xx-adc.c:	chip->allow_async_readout = val;
+drivers/iio/adc/ina2xx-adc.c:	return regmap_write(chip->regmap, INA2XX_CALIBRATION,
+drivers/iio/adc/ina2xx-adc.c:			    chip->config->calibration_value);
+drivers/iio/adc/ina2xx-adc.c:	chip->shunt_resistor_uohm = val;
+drivers/iio/adc/ina2xx-adc.c:	int vals[2] = { chip->shunt_resistor_uohm, 1000000 };
+drivers/iio/adc/ina2xx-adc.c:	if (chip->config->chip_id == ina226) {
+drivers/iio/adc/ina2xx-adc.c:		ret = regmap_read(chip->regmap,
+drivers/iio/adc/ina2xx-adc.c:		ret = regmap_read(chip->regmap,
+drivers/iio/adc/ina2xx-adc.c:		ret = regmap_read(chip->regmap,
+drivers/iio/adc/ina2xx-adc.c:	if (!chip->allow_async_readout)
+drivers/iio/adc/ina2xx-adc.c:		while (!chip->allow_async_readout) {
+drivers/iio/adc/ina2xx-adc.c:		1000000 / sampling_us, chip->avg);
+drivers/iio/adc/ina2xx-adc.c:		chip->allow_async_readout);
+drivers/iio/adc/ina2xx-adc.c:	chip->task = task;
+drivers/iio/adc/ina2xx-adc.c:	if (chip->task) {
+drivers/iio/adc/ina2xx-adc.c:		kthread_stop(chip->task);
+drivers/iio/adc/ina2xx-adc.c:		put_task_struct(chip->task);
+drivers/iio/adc/ina2xx-adc.c:		chip->task = NULL;
+drivers/iio/adc/ina2xx-adc.c:		return regmap_write(chip->regmap, reg, writeval);
+drivers/iio/adc/ina2xx-adc.c:	return regmap_read(chip->regmap, reg, readval);
+drivers/iio/adc/ina2xx-adc.c:	int ret = regmap_write(chip->regmap, INA2XX_CONFIG, config);
+drivers/iio/adc/ina2xx-adc.c:	chip->regmap = devm_regmap_init_i2c(client, &ina2xx_regmap_config);
+drivers/iio/adc/ina2xx-adc.c:	if (IS_ERR(chip->regmap)) {
+drivers/iio/adc/ina2xx-adc.c:		return PTR_ERR(chip->regmap);
+drivers/iio/adc/ina2xx-adc.c:	chip->config = &ina2xx_config[type];
+drivers/iio/adc/ina2xx-adc.c:	mutex_init(&chip->state_lock);
+drivers/iio/adc/ina2xx-adc.c:	val = chip->config->config_default;
+drivers/iio/adc/ina2xx-adc.c:		chip->avg = 1;
+drivers/iio/adc/ina2xx-adc.c:	return regmap_update_bits(chip->regmap, INA2XX_CONFIG,
+drivers/iio/adc/rockchip_saradc.c:		.name	= "rockchip-saradc",
+drivers/iio/adc/stx104.c:	chip->set(chip, offset, value);
+drivers/iio/chemical/atlas-ph-sensor.c:	ret = regmap_bulk_read(data->regmap, data->chip->data_reg,
+drivers/iio/chemical/atlas-ph-sensor.c:			      sizeof(__be32) * (data->chip->num_channels - 2));
+drivers/iio/chemical/atlas-ph-sensor.c:		msleep(data->chip->delay);
+drivers/iio/chemical/atlas-ph-sensor.c:	indio_dev->channels = chip->channels;
+drivers/iio/chemical/atlas-ph-sensor.c:	indio_dev->num_channels = chip->num_channels;
+drivers/iio/chemical/atlas-ph-sensor.c:	ret = chip->calibration(data);
+drivers/iio/chemical/vz89x.c:	return !!(data->buffer[data->chip->read_size - 1] > 0);
+drivers/iio/chemical/vz89x.c:	for (i = 0; i < (data->chip->read_size - 1); i++) {
+drivers/iio/chemical/vz89x.c:	return !((0xff - crc) == data->buffer[data->chip->read_size - 1]);
+drivers/iio/chemical/vz89x.c:	msg[0].len = chip->write_size;
+drivers/iio/chemical/vz89x.c:	msg[1].len = chip->read_size;
+drivers/iio/chemical/vz89x.c:	for (i = 0; i < data->chip->read_size; i++) {
+drivers/iio/chemical/vz89x.c:	ret = data->xfer(data, chip->cmd);
+drivers/iio/chemical/vz89x.c:	ret = chip->valid(data);
+drivers/iio/chemical/vz89x.c:	indio_dev->channels = data->chip->channels;
+drivers/iio/chemical/vz89x.c:	indio_dev->num_channels = data->chip->num_channels;
+drivers/iio/light/cm3232.c:	struct i2c_client *client = chip->client;
+drivers/iio/light/cm3232.c:	chip->als_info = &cm3232_als_info_default;
+drivers/iio/light/cm3232.c:		dev_err(&chip->client->dev, "Error reading addr_id\n");
+drivers/iio/light/cm3232.c:	if ((ret & 0xFF) != chip->als_info->hw_id)
+drivers/iio/light/cm3232.c:	chip->regs_cmd = CM3232_CMD_ALS_DISABLE | CM3232_CMD_ALS_RESET;
+drivers/iio/light/cm3232.c:					chip->regs_cmd);
+drivers/iio/light/cm3232.c:		dev_err(&chip->client->dev, "Error writing reg_cmd\n");
+drivers/iio/light/cm3232.c:	chip->regs_cmd = chip->als_info->regs_cmd_default;
+drivers/iio/light/cm3232.c:					chip->regs_cmd);
+drivers/iio/light/cm3232.c:		dev_err(&chip->client->dev, "Error writing reg_cmd\n");
+drivers/iio/light/cm3232.c:	als_it = chip->regs_cmd;
+drivers/iio/light/cm3232.c:	struct i2c_client *client = chip->client;
+drivers/iio/light/cm3232.c:			cmd = chip->regs_cmd & ~CM3232_CMD_ALS_IT_MASK;
+drivers/iio/light/cm3232.c:			chip->regs_cmd = cmd;
+drivers/iio/light/cm3232.c:	struct i2c_client *client = chip->client;
+drivers/iio/light/cm3232.c:	struct cm3232_als_info *als_info = chip->als_info;
+drivers/iio/light/cm3232.c:	chip->regs_als = (u16)ret;
+drivers/iio/light/cm3232.c:	lux *= chip->regs_als;
+drivers/iio/light/cm3232.c:	struct cm3232_als_info *als_info = chip->als_info;
+drivers/iio/light/cm3232.c:	struct cm3232_als_info *als_info = chip->als_info;
+drivers/iio/light/cm3232.c:	chip->client = client;
+drivers/iio/light/cm3232.c:	struct i2c_client *client = chip->client;
+drivers/iio/light/cm3232.c:	chip->regs_cmd |= CM3232_CMD_ALS_DISABLE;
+drivers/iio/light/cm3232.c:					chip->regs_cmd);
+drivers/iio/light/cm3232.c:	struct i2c_client *client = chip->client;
+drivers/iio/light/cm3232.c:	chip->regs_cmd &= ~CM3232_CMD_ALS_DISABLE;
+drivers/iio/light/cm3232.c:					chip->regs_cmd | CM3232_CMD_ALS_RESET);
+drivers/iio/light/isl29018.c:	for (i = 0; i < ARRAY_SIZE(isl29018_int_utimes[chip->type]); ++i) {
+drivers/iio/light/isl29018.c:		if (utime == isl29018_int_utimes[chip->type][i]) {
+drivers/iio/light/isl29018.c:	if (i >= ARRAY_SIZE(isl29018_int_utimes[chip->type]))
+drivers/iio/light/isl29018.c:	ret = regmap_update_bits(chip->regmap, ISL29018_REG_ADD_COMMAND2,
+drivers/iio/light/isl29018.c:	int_time = chip->int_time;
+drivers/iio/light/isl29018.c:		if (chip->scale.scale == isl29018_scales[int_time][i].scale &&
+drivers/iio/light/isl29018.c:		    chip->scale.uscale == isl29018_scales[int_time][i].uscale) {
+drivers/iio/light/isl29018.c:			chip->scale = isl29018_scales[new_int_time][i];
+drivers/iio/light/isl29018.c:	chip->int_time = new_int_time;
+drivers/iio/light/isl29018.c:	for (i = 0; i < ARRAY_SIZE(isl29018_scales[chip->int_time]); ++i) {
+drivers/iio/light/isl29018.c:		if (scale == isl29018_scales[chip->int_time][i].scale &&
+drivers/iio/light/isl29018.c:		    uscale == isl29018_scales[chip->int_time][i].uscale) {
+drivers/iio/light/isl29018.c:			new_scale = isl29018_scales[chip->int_time][i];
+drivers/iio/light/isl29018.c:	if (i >= ARRAY_SIZE(isl29018_scales[chip->int_time]))
+drivers/iio/light/isl29018.c:	ret = regmap_update_bits(chip->regmap, ISL29018_REG_ADD_COMMAND2,
+drivers/iio/light/isl29018.c:	chip->scale = new_scale;
+drivers/iio/light/isl29018.c:	struct device *dev = regmap_get_device(chip->regmap);
+drivers/iio/light/isl29018.c:	status = regmap_write(chip->regmap, ISL29018_REG_ADD_COMMAND1,
+drivers/iio/light/isl29018.c:	status = regmap_read(chip->regmap, ISL29018_REG_ADD_DATA_LSB, &lsb);
+drivers/iio/light/isl29018.c:	status = regmap_read(chip->regmap, ISL29018_REG_ADD_DATA_MSB, &msb);
+drivers/iio/light/isl29018.c:	data_x_range = lux_data * chip->scale.scale +
+drivers/iio/light/isl29018.c:		       lux_data * chip->scale.uscale / 1000000;
+drivers/iio/light/isl29018.c:	*lux = data_x_range * chip->calibscale +
+drivers/iio/light/isl29018.c:	       data_x_range * chip->ucalibscale / 1000000;
+drivers/iio/light/isl29018.c:	struct device *dev = regmap_get_device(chip->regmap);
+drivers/iio/light/isl29018.c:	status = regmap_update_bits(chip->regmap, ISL29018_REG_ADD_COMMAND2,
+drivers/iio/light/isl29018.c:	mutex_lock(&chip->lock);
+drivers/iio/light/isl29018.c:	for (i = 0; i < ARRAY_SIZE(isl29018_scales[chip->int_time]); ++i)
+drivers/iio/light/isl29018.c:			       isl29018_scales[chip->int_time][i].scale,
+drivers/iio/light/isl29018.c:			       isl29018_scales[chip->int_time][i].uscale);
+drivers/iio/light/isl29018.c:	mutex_unlock(&chip->lock);
+drivers/iio/light/isl29018.c:	for (i = 0; i < ARRAY_SIZE(isl29018_int_utimes[chip->type]); ++i)
+drivers/iio/light/isl29018.c:			       isl29018_int_utimes[chip->type][i]);
+drivers/iio/light/isl29018.c:	return sprintf(buf, "%d\n", chip->prox_scheme);
+drivers/iio/light/isl29018.c:	mutex_lock(&chip->lock);
+drivers/iio/light/isl29018.c:	chip->prox_scheme = val;
+drivers/iio/light/isl29018.c:	mutex_unlock(&chip->lock);
+drivers/iio/light/isl29018.c:	mutex_lock(&chip->lock);
+drivers/iio/light/isl29018.c:	if (chip->suspended) {
+drivers/iio/light/isl29018.c:			chip->calibscale = val;
+drivers/iio/light/isl29018.c:			chip->ucalibscale = val2;
+drivers/iio/light/isl29018.c:	mutex_unlock(&chip->lock);
+drivers/iio/light/isl29018.c:	mutex_lock(&chip->lock);
+drivers/iio/light/isl29018.c:	if (chip->suspended) {
+drivers/iio/light/isl29018.c:							 chip->prox_scheme,
+drivers/iio/light/isl29018.c:			*val2 = isl29018_int_utimes[chip->type][chip->int_time];
+drivers/iio/light/isl29018.c:			*val = chip->scale.scale;
+drivers/iio/light/isl29018.c:			*val2 = chip->scale.uscale;
+drivers/iio/light/isl29018.c:			*val = chip->calibscale;
+drivers/iio/light/isl29018.c:			*val2 = chip->ucalibscale;
+drivers/iio/light/isl29018.c:	mutex_unlock(&chip->lock);
+drivers/iio/light/isl29018.c:	struct device *dev = regmap_get_device(chip->regmap);
+drivers/iio/light/isl29018.c:	if (chip->type == isl29035) {
+drivers/iio/light/isl29018.c:		status = regmap_read(chip->regmap, ISL29035_REG_DEVICE_ID, &id);
+drivers/iio/light/isl29018.c:		status = regmap_update_bits(chip->regmap,
+drivers/iio/light/isl29018.c:	status = regmap_write(chip->regmap, ISL29018_REG_TEST, 0x0);
+drivers/iio/light/isl29018.c:	status = regmap_write(chip->regmap, ISL29018_REG_ADD_COMMAND1, 0);
+drivers/iio/light/isl29018.c:	status = isl29018_set_scale(chip, chip->scale.scale,
+drivers/iio/light/isl29018.c:				    chip->scale.uscale);
+drivers/iio/light/isl29018.c:			isl29018_int_utimes[chip->type][chip->int_time]);
+drivers/iio/light/isl29018.c:	err = regulator_disable(chip->vcc_reg);
+drivers/iio/light/isl29018.c:	mutex_init(&chip->lock);
+drivers/iio/light/isl29018.c:	chip->type = dev_id;
+drivers/iio/light/isl29018.c:	chip->calibscale = 1;
+drivers/iio/light/isl29018.c:	chip->ucalibscale = 0;
+drivers/iio/light/isl29018.c:	chip->int_time = ISL29018_INT_TIME_16;
+drivers/iio/light/isl29018.c:	chip->scale = isl29018_scales[chip->int_time][0];
+drivers/iio/light/isl29018.c:	chip->suspended = false;
+drivers/iio/light/isl29018.c:	chip->vcc_reg = devm_regulator_get(&client->dev, "vcc");
+drivers/iio/light/isl29018.c:	if (IS_ERR(chip->vcc_reg)) {
+drivers/iio/light/isl29018.c:		err = PTR_ERR(chip->vcc_reg);
+drivers/iio/light/isl29018.c:	err = regulator_enable(chip->vcc_reg);
+drivers/iio/light/isl29018.c:	chip->regmap = devm_regmap_init_i2c(client,
+drivers/iio/light/isl29018.c:	if (IS_ERR(chip->regmap)) {
+drivers/iio/light/isl29018.c:		err = PTR_ERR(chip->regmap);
+drivers/iio/light/isl29018.c:	mutex_lock(&chip->lock);
+drivers/iio/light/isl29018.c:	chip->suspended = true;
+drivers/iio/light/isl29018.c:	ret = regulator_disable(chip->vcc_reg);
+drivers/iio/light/isl29018.c:	mutex_unlock(&chip->lock);
+drivers/iio/light/isl29018.c:	mutex_lock(&chip->lock);
+drivers/iio/light/isl29018.c:	err = regulator_enable(chip->vcc_reg);
+drivers/iio/light/isl29018.c:		mutex_unlock(&chip->lock);
+drivers/iio/light/isl29018.c:		chip->suspended = false;
+drivers/iio/light/isl29018.c:	mutex_unlock(&chip->lock);
+drivers/iio/light/isl29028.c:	struct device *dev = regmap_get_device(chip->regmap);
+drivers/iio/light/isl29028.c:	ret = regmap_update_bits(chip->regmap, ISL29028_REG_CONFIGURE,
+drivers/iio/light/isl29028.c:	chip->prox_sampling_int = sampling_int;
+drivers/iio/light/isl29028.c:	chip->prox_sampling_frac = sampling_fract;
+drivers/iio/light/isl29028.c:	ret = isl29028_set_proxim_sampling(chip, chip->prox_sampling_int,
+drivers/iio/light/isl29028.c:					   chip->prox_sampling_frac);
+drivers/iio/light/isl29028.c:	ret = regmap_update_bits(chip->regmap, ISL29028_REG_CONFIGURE,
+drivers/iio/light/isl29028.c:	prox_index = isl29028_find_prox_sleep_index(chip->prox_sampling_int,
+drivers/iio/light/isl29028.c:						    chip->prox_sampling_frac);
+drivers/iio/light/isl29028.c:	struct device *dev = regmap_get_device(chip->regmap);
+drivers/iio/light/isl29028.c:	ret = regmap_update_bits(chip->regmap, ISL29028_REG_CONFIGURE,
+drivers/iio/light/isl29028.c:	chip->lux_scale = lux_scale;
+drivers/iio/light/isl29028.c:	if (chip->als_ir_mode == mode)
+drivers/iio/light/isl29028.c:	ret = isl29028_set_als_scale(chip, chip->lux_scale);
+drivers/iio/light/isl29028.c:		ret = regmap_update_bits(chip->regmap, ISL29028_REG_CONFIGURE,
+drivers/iio/light/isl29028.c:		ret = regmap_update_bits(chip->regmap, ISL29028_REG_CONFIGURE,
+drivers/iio/light/isl29028.c:		ret = regmap_update_bits(chip->regmap, ISL29028_REG_CONFIGURE,
+drivers/iio/light/isl29028.c:		return regmap_update_bits(chip->regmap, ISL29028_REG_CONFIGURE,
+drivers/iio/light/isl29028.c:	ret = regmap_update_bits(chip->regmap, ISL29028_REG_CONFIGURE,
+drivers/iio/light/isl29028.c:	chip->als_ir_mode = mode;
+drivers/iio/light/isl29028.c:	struct device *dev = regmap_get_device(chip->regmap);
+drivers/iio/light/isl29028.c:	ret = regmap_read(chip->regmap, ISL29028_REG_ALSIR_L, &lsb);
+drivers/iio/light/isl29028.c:	ret = regmap_read(chip->regmap, ISL29028_REG_ALSIR_U, &msb);
+drivers/iio/light/isl29028.c:	struct device *dev = regmap_get_device(chip->regmap);
+drivers/iio/light/isl29028.c:	if (!chip->enable_prox) {
+drivers/iio/light/isl29028.c:		chip->enable_prox = true;
+drivers/iio/light/isl29028.c:	ret = regmap_read(chip->regmap, ISL29028_REG_PROX_DATA, &data);
+drivers/iio/light/isl29028.c:	struct device *dev = regmap_get_device(chip->regmap);
+drivers/iio/light/isl29028.c:	if (chip->lux_scale == 125)
+drivers/iio/light/isl29028.c:	struct device *dev = regmap_get_device(chip->regmap);
+drivers/iio/light/isl29028.c:	struct device *dev = regmap_get_device(chip->regmap);
+drivers/iio/light/isl29028.c:	struct device *dev = regmap_get_device(chip->regmap);
+drivers/iio/light/isl29028.c:	mutex_lock(&chip->lock);
+drivers/iio/light/isl29028.c:	mutex_unlock(&chip->lock);
+drivers/iio/light/isl29028.c:	struct device *dev = regmap_get_device(chip->regmap);
+drivers/iio/light/isl29028.c:	mutex_lock(&chip->lock);
+drivers/iio/light/isl29028.c:		*val = chip->prox_sampling_int;
+drivers/iio/light/isl29028.c:		*val2 = chip->prox_sampling_frac;
+drivers/iio/light/isl29028.c:		*val = chip->lux_scale;
+drivers/iio/light/isl29028.c:	mutex_unlock(&chip->lock);
+drivers/iio/light/isl29028.c:	struct device *dev = regmap_get_device(chip->regmap);
+drivers/iio/light/isl29028.c:	ret = regmap_write(chip->regmap, ISL29028_REG_CONFIGURE, 0x0);
+drivers/iio/light/isl29028.c:	chip->als_ir_mode = ISL29028_MODE_NONE;
+drivers/iio/light/isl29028.c:	chip->enable_prox = false;
+drivers/iio/light/isl29028.c:	mutex_init(&chip->lock);
+drivers/iio/light/isl29028.c:	chip->regmap = devm_regmap_init_i2c(client, &isl29028_regmap_config);
+drivers/iio/light/isl29028.c:	if (IS_ERR(chip->regmap)) {
+drivers/iio/light/isl29028.c:		ret = PTR_ERR(chip->regmap);
+drivers/iio/light/isl29028.c:	chip->enable_prox  = false;
+drivers/iio/light/isl29028.c:	chip->prox_sampling_int = 20;
+drivers/iio/light/isl29028.c:	chip->prox_sampling_frac = 0;
+drivers/iio/light/isl29028.c:	chip->lux_scale = 2000;
+drivers/iio/light/isl29028.c:	ret = regmap_write(chip->regmap, ISL29028_REG_TEST1_MODE, 0x0);
+drivers/iio/light/isl29028.c:	ret = regmap_write(chip->regmap, ISL29028_REG_TEST2_MODE, 0x0);
+drivers/iio/light/isl29028.c:	mutex_lock(&chip->lock);
+drivers/iio/light/isl29028.c:	mutex_unlock(&chip->lock);
+drivers/iio/light/tsl2563.c:	struct i2c_client *client = chip->client;
+drivers/iio/light/tsl2563.c:	struct i2c_client *client = chip->client;
+drivers/iio/light/tsl2563.c:	ret = i2c_smbus_write_byte_data(chip->client,
+drivers/iio/light/tsl2563.c:			chip->gainlevel->gaintime);
+drivers/iio/light/tsl2563.c:	ret = i2c_smbus_write_byte_data(chip->client,
+drivers/iio/light/tsl2563.c:			chip->high_thres & 0xFF);
+drivers/iio/light/tsl2563.c:	ret = i2c_smbus_write_byte_data(chip->client,
+drivers/iio/light/tsl2563.c:			(chip->high_thres >> 8) & 0xFF);
+drivers/iio/light/tsl2563.c:	ret = i2c_smbus_write_byte_data(chip->client,
+drivers/iio/light/tsl2563.c:			chip->low_thres & 0xFF);
+drivers/iio/light/tsl2563.c:	ret = i2c_smbus_write_byte_data(chip->client,
+drivers/iio/light/tsl2563.c:			(chip->low_thres >> 8) & 0xFF);
+drivers/iio/light/tsl2563.c:	struct i2c_client *client = chip->client;
+drivers/iio/light/tsl2563.c:	switch (chip->gainlevel->gaintime & TSL2563_TIMING_MASK) {
+drivers/iio/light/tsl2563.c:	struct i2c_client *client = chip->client;
+drivers/iio/light/tsl2563.c:	if (adc > chip->gainlevel->max || adc < chip->gainlevel->min) {
+drivers/iio/light/tsl2563.c:		(adc > chip->gainlevel->max) ?
+drivers/iio/light/tsl2563.c:			chip->gainlevel++ : chip->gainlevel--;
+drivers/iio/light/tsl2563.c:					  chip->gainlevel->gaintime);
+drivers/iio/light/tsl2563.c:	struct i2c_client *client = chip->client;
+drivers/iio/light/tsl2563.c:	if (chip->suspended)
+drivers/iio/light/tsl2563.c:	if (!chip->int_enabled) {
+drivers/iio/light/tsl2563.c:		cancel_delayed_work(&chip->poweroff_work);
+drivers/iio/light/tsl2563.c:	chip->data0 = tsl2563_normalize_adc(adc0, chip->gainlevel->gaintime);
+drivers/iio/light/tsl2563.c:	chip->data1 = tsl2563_normalize_adc(adc1, chip->gainlevel->gaintime);
+drivers/iio/light/tsl2563.c:	if (!chip->int_enabled)
+drivers/iio/light/tsl2563.c:		schedule_delayed_work(&chip->poweroff_work, 5 * HZ);
+drivers/iio/light/tsl2563.c:		chip->calib0 = tsl2563_calib_from_sysfs(val);
+drivers/iio/light/tsl2563.c:		chip->calib1 = tsl2563_calib_from_sysfs(val);
+drivers/iio/light/tsl2563.c:	mutex_lock(&chip->lock);
+drivers/iio/light/tsl2563.c:			calib0 = tsl2563_calib_adc(chip->data0, chip->calib0) *
+drivers/iio/light/tsl2563.c:				chip->cover_comp_gain;
+drivers/iio/light/tsl2563.c:			calib1 = tsl2563_calib_adc(chip->data1, chip->calib1) *
+drivers/iio/light/tsl2563.c:				chip->cover_comp_gain;
+drivers/iio/light/tsl2563.c:				*val = chip->data0;
+drivers/iio/light/tsl2563.c:				*val = chip->data1;
+drivers/iio/light/tsl2563.c:			*val = tsl2563_calib_to_sysfs(chip->calib0);
+drivers/iio/light/tsl2563.c:			*val = tsl2563_calib_to_sysfs(chip->calib1);
+drivers/iio/light/tsl2563.c:	mutex_unlock(&chip->lock);
+drivers/iio/light/tsl2563.c:		*val = chip->high_thres;
+drivers/iio/light/tsl2563.c:		*val = chip->low_thres;
+drivers/iio/light/tsl2563.c:	mutex_lock(&chip->lock);
+drivers/iio/light/tsl2563.c:	ret = i2c_smbus_write_byte_data(chip->client, TSL2563_CMD | address,
+drivers/iio/light/tsl2563.c:	ret = i2c_smbus_write_byte_data(chip->client,
+drivers/iio/light/tsl2563.c:		chip->high_thres = val;
+drivers/iio/light/tsl2563.c:		chip->low_thres = val;
+drivers/iio/light/tsl2563.c:	mutex_unlock(&chip->lock);
+drivers/iio/light/tsl2563.c:	i2c_smbus_write_byte(chip->client, TSL2563_CMD | TSL2563_CLEARINT);
+drivers/iio/light/tsl2563.c:	mutex_lock(&chip->lock);
+drivers/iio/light/tsl2563.c:	if (state && !(chip->intr & 0x30)) {
+drivers/iio/light/tsl2563.c:		chip->intr &= ~0x30;
+drivers/iio/light/tsl2563.c:		chip->intr |= 0x10;
+drivers/iio/light/tsl2563.c:		cancel_delayed_work(&chip->poweroff_work);
+drivers/iio/light/tsl2563.c:		ret = i2c_smbus_write_byte_data(chip->client,
+drivers/iio/light/tsl2563.c:						chip->intr);
+drivers/iio/light/tsl2563.c:		chip->int_enabled = true;
+drivers/iio/light/tsl2563.c:	if (!state && (chip->intr & 0x30)) {
+drivers/iio/light/tsl2563.c:		chip->intr &= ~0x30;
+drivers/iio/light/tsl2563.c:		ret = i2c_smbus_write_byte_data(chip->client,
+drivers/iio/light/tsl2563.c:						chip->intr);
+drivers/iio/light/tsl2563.c:		chip->int_enabled = false;
+drivers/iio/light/tsl2563.c:		schedule_delayed_work(&chip->poweroff_work, 5 * HZ);
+drivers/iio/light/tsl2563.c:	mutex_unlock(&chip->lock);
+drivers/iio/light/tsl2563.c:	mutex_lock(&chip->lock);
+drivers/iio/light/tsl2563.c:	ret = i2c_smbus_read_byte_data(chip->client,
+drivers/iio/light/tsl2563.c:	mutex_unlock(&chip->lock);
+drivers/iio/light/tsl2563.c:	chip->client = client;
+drivers/iio/light/tsl2563.c:	mutex_init(&chip->lock);
+drivers/iio/light/tsl2563.c:	chip->low_thres = 0x0;
+drivers/iio/light/tsl2563.c:	chip->high_thres = 0xffff;
+drivers/iio/light/tsl2563.c:	chip->gainlevel = tsl2563_gainlevel_table;
+drivers/iio/light/tsl2563.c:	chip->intr = TSL2563_INT_PERSIST(4);
+drivers/iio/light/tsl2563.c:	chip->calib0 = tsl2563_calib_from_sysfs(CALIB_BASE_SYSFS);
+drivers/iio/light/tsl2563.c:	chip->calib1 = tsl2563_calib_from_sysfs(CALIB_BASE_SYSFS);
+drivers/iio/light/tsl2563.c:		chip->cover_comp_gain = pdata->cover_comp_gain;
+drivers/iio/light/tsl2563.c:				     &chip->cover_comp_gain);
+drivers/iio/light/tsl2563.c:		chip->cover_comp_gain = 1;
+drivers/iio/light/tsl2563.c:	INIT_DELAYED_WORK(&chip->poweroff_work, tsl2563_poweroff_work);
+drivers/iio/light/tsl2563.c:	schedule_delayed_work(&chip->poweroff_work, 5 * HZ);
+drivers/iio/light/tsl2563.c:	cancel_delayed_work_sync(&chip->poweroff_work);
+drivers/iio/light/tsl2563.c:	if (!chip->int_enabled)
+drivers/iio/light/tsl2563.c:		cancel_delayed_work(&chip->poweroff_work);
+drivers/iio/light/tsl2563.c:	chip->intr &= ~0x30;
+drivers/iio/light/tsl2563.c:	i2c_smbus_write_byte_data(chip->client, TSL2563_CMD | TSL2563_REG_INT,
+drivers/iio/light/tsl2563.c:				  chip->intr);
+drivers/iio/light/tsl2563.c:	mutex_lock(&chip->lock);
+drivers/iio/light/tsl2563.c:	chip->suspended = true;
+drivers/iio/light/tsl2563.c:	mutex_unlock(&chip->lock);
+drivers/iio/light/tsl2563.c:	mutex_lock(&chip->lock);
+drivers/iio/light/tsl2563.c:	chip->suspended = false;
+drivers/iio/light/tsl2563.c:	mutex_unlock(&chip->lock);
+drivers/iio/light/tsl2583.c:	chip->als_settings.als_time = 100;
+drivers/iio/light/tsl2583.c:	chip->als_settings.als_gain = 0;
+drivers/iio/light/tsl2583.c:	chip->als_settings.als_gain_trim = 1000;
+drivers/iio/light/tsl2583.c:	chip->als_settings.als_cal_target = 130;
+drivers/iio/light/tsl2583.c:	memcpy(chip->als_settings.als_device_lux, tsl2583_default_lux,
+drivers/iio/light/tsl2583.c:	ret = i2c_smbus_read_byte_data(chip->client, TSL2583_CMD_REG);
+drivers/iio/light/tsl2583.c:		dev_err(&chip->client->dev, "%s: failed to read CMD_REG register\n",
+drivers/iio/light/tsl2583.c:		dev_err(&chip->client->dev, "%s: data not valid; returning last value\n",
+drivers/iio/light/tsl2583.c:		ret = chip->als_cur_info.lux; /* return LAST VALUE */
+drivers/iio/light/tsl2583.c:		ret = i2c_smbus_read_byte_data(chip->client, reg);
+drivers/iio/light/tsl2583.c:			dev_err(&chip->client->dev, "%s: failed to read register %x\n",
+drivers/iio/light/tsl2583.c:	ret = i2c_smbus_write_byte(chip->client,
+drivers/iio/light/tsl2583.c:		dev_err(&chip->client->dev, "%s: failed to clear the interrupt bit\n",
+drivers/iio/light/tsl2583.c:	chip->als_cur_info.als_ch0 = ch0;
+drivers/iio/light/tsl2583.c:	chip->als_cur_info.als_ch1 = ch1;
+drivers/iio/light/tsl2583.c:	if ((ch0 >= chip->als_saturation) || (ch1 >= chip->als_saturation))
+drivers/iio/light/tsl2583.c:		chip->als_cur_info.lux = 0;
+drivers/iio/light/tsl2583.c:	for (p = (struct tsl2583_lux *)chip->als_settings.als_device_lux;
+drivers/iio/light/tsl2583.c:			  (gainadj[chip->als_settings.als_gain].ch0 >> 1))
+drivers/iio/light/tsl2583.c:			 / gainadj[chip->als_settings.als_gain].ch0;
+drivers/iio/light/tsl2583.c:			  (gainadj[chip->als_settings.als_gain].ch1 >> 1))
+drivers/iio/light/tsl2583.c:			 / gainadj[chip->als_settings.als_gain].ch1;
+drivers/iio/light/tsl2583.c:			dev_dbg(&chip->client->dev, "%s: No Data - Returning 0\n",
+drivers/iio/light/tsl2583.c:			chip->als_cur_info.lux = 0;
+drivers/iio/light/tsl2583.c:	if (chip->als_time_scale == 0)
+drivers/iio/light/tsl2583.c:		lux = (lux + (chip->als_time_scale >> 1)) /
+drivers/iio/light/tsl2583.c:			chip->als_time_scale;
+drivers/iio/light/tsl2583.c:	lux64 = lux64 * chip->als_settings.als_gain_trim;
+drivers/iio/light/tsl2583.c:	chip->als_cur_info.lux = lux;
+drivers/iio/light/tsl2583.c:	ret = i2c_smbus_read_byte_data(chip->client,
+drivers/iio/light/tsl2583.c:		dev_err(&chip->client->dev,
+drivers/iio/light/tsl2583.c:		dev_err(&chip->client->dev,
+drivers/iio/light/tsl2583.c:		dev_err(&chip->client->dev,
+drivers/iio/light/tsl2583.c:		dev_err(&chip->client->dev, "%s: failed to get lux\n",
+drivers/iio/light/tsl2583.c:	gain_trim_val = (unsigned int)(((chip->als_settings.als_cal_target)
+drivers/iio/light/tsl2583.c:			* chip->als_settings.als_gain_trim) / lux_val);
+drivers/iio/light/tsl2583.c:		dev_err(&chip->client->dev,
+drivers/iio/light/tsl2583.c:	chip->als_settings.als_gain_trim = (int)gain_trim_val;
+drivers/iio/light/tsl2583.c:	als_count = (chip->als_settings.als_time * 100 + 135) / 270;
+drivers/iio/light/tsl2583.c:	ret = i2c_smbus_write_byte_data(chip->client,
+drivers/iio/light/tsl2583.c:		dev_err(&chip->client->dev, "%s: failed to set the als time to %d\n",
+drivers/iio/light/tsl2583.c:	chip->als_saturation = als_count * 922; /* 90% of full scale */
+drivers/iio/light/tsl2583.c:	chip->als_time_scale = (als_time + 25) / 50;
+drivers/iio/light/tsl2583.c:	ret = i2c_smbus_write_byte_data(chip->client,
+drivers/iio/light/tsl2583.c:					chip->als_settings.als_gain);
+drivers/iio/light/tsl2583.c:		dev_err(&chip->client->dev,
+drivers/iio/light/tsl2583.c:			chip->als_settings.als_gain);
+drivers/iio/light/tsl2583.c:	ret = i2c_smbus_write_byte_data(chip->client,
+drivers/iio/light/tsl2583.c:		dev_err(&chip->client->dev,
+drivers/iio/light/tsl2583.c:	ret = i2c_smbus_write_byte_data(chip->client,
+drivers/iio/light/tsl2583.c:		dev_err(&chip->client->dev,
+drivers/iio/light/tsl2583.c:	mutex_lock(&chip->als_mutex);
+drivers/iio/light/tsl2583.c:	ret = sprintf(buf, "%d\n", chip->als_settings.als_cal_target);
+drivers/iio/light/tsl2583.c:	mutex_unlock(&chip->als_mutex);
+drivers/iio/light/tsl2583.c:	mutex_lock(&chip->als_mutex);
+drivers/iio/light/tsl2583.c:	chip->als_settings.als_cal_target = value;
+drivers/iio/light/tsl2583.c:	mutex_unlock(&chip->als_mutex);
+drivers/iio/light/tsl2583.c:	mutex_lock(&chip->als_mutex);
+drivers/iio/light/tsl2583.c:	mutex_unlock(&chip->als_mutex);
+drivers/iio/light/tsl2583.c:	for (i = 0; i < ARRAY_SIZE(chip->als_settings.als_device_lux); i++) {
+drivers/iio/light/tsl2583.c:				  chip->als_settings.als_device_lux[i].ratio,
+drivers/iio/light/tsl2583.c:				  chip->als_settings.als_device_lux[i].ch0,
+drivers/iio/light/tsl2583.c:				  chip->als_settings.als_device_lux[i].ch1);
+drivers/iio/light/tsl2583.c:		if (chip->als_settings.als_device_lux[i].ratio == 0) {
+drivers/iio/light/tsl2583.c:	mutex_lock(&chip->als_mutex);
+drivers/iio/light/tsl2583.c:	memcpy(chip->als_settings.als_device_lux, &value[1],
+drivers/iio/light/tsl2583.c:	mutex_unlock(&chip->als_mutex);
+drivers/iio/light/tsl2583.c:		ret = pm_runtime_get_sync(&chip->client->dev);
+drivers/iio/light/tsl2583.c:			pm_runtime_put_noidle(&chip->client->dev);
+drivers/iio/light/tsl2583.c:		pm_runtime_mark_last_busy(&chip->client->dev);
+drivers/iio/light/tsl2583.c:		ret = pm_runtime_put_autosuspend(&chip->client->dev);
+drivers/iio/light/tsl2583.c:	mutex_lock(&chip->als_mutex);
+drivers/iio/light/tsl2583.c:				*val = chip->als_cur_info.als_ch0;
+drivers/iio/light/tsl2583.c:				*val = chip->als_cur_info.als_ch1;
+drivers/iio/light/tsl2583.c:			*val = chip->als_settings.als_gain_trim;
+drivers/iio/light/tsl2583.c:			*val = gainadj[chip->als_settings.als_gain].mean;
+drivers/iio/light/tsl2583.c:			*val2 = chip->als_settings.als_time;
+drivers/iio/light/tsl2583.c:	mutex_unlock(&chip->als_mutex);
+drivers/iio/light/tsl2583.c:	mutex_lock(&chip->als_mutex);
+drivers/iio/light/tsl2583.c:			chip->als_settings.als_gain_trim = val;
+drivers/iio/light/tsl2583.c:					chip->als_settings.als_gain = i;
+drivers/iio/light/tsl2583.c:			chip->als_settings.als_time = val2;
+drivers/iio/light/tsl2583.c:	mutex_unlock(&chip->als_mutex);
+drivers/iio/light/tsl2583.c:	chip->client = clientp;
+drivers/iio/light/tsl2583.c:	mutex_init(&chip->als_mutex);
+drivers/iio/light/tsl2583.c:	indio_dev->name = chip->client->name;
+drivers/iio/light/tsl2583.c:	mutex_lock(&chip->als_mutex);
+drivers/iio/light/tsl2583.c:	mutex_unlock(&chip->als_mutex);
+drivers/iio/light/tsl2583.c:	mutex_lock(&chip->als_mutex);
+drivers/iio/light/tsl2583.c:	mutex_unlock(&chip->als_mutex);
+drivers/iio/light/tsl2772.c:	ret = i2c_smbus_read_byte_data(chip->client,
+drivers/iio/light/tsl2772.c:		dev_err(&chip->client->dev,
+drivers/iio/light/tsl2772.c:	ret = i2c_smbus_write_byte_data(chip->client,
+drivers/iio/light/tsl2772.c:		dev_err(&chip->client->dev,
+drivers/iio/light/tsl2772.c:	ret = i2c_smbus_write_byte(chip->client,
+drivers/iio/light/tsl2772.c:		dev_err(&chip->client->dev,
+drivers/iio/light/tsl2772.c:	ret = i2c_smbus_read_byte_data(chip->client,
+drivers/iio/light/tsl2772.c:		dev_err(&chip->client->dev,
+drivers/iio/light/tsl2772.c:	ret = i2c_smbus_read_byte_data(chip->client,
+drivers/iio/light/tsl2772.c:		dev_err(&chip->client->dev,
+drivers/iio/light/tsl2772.c:	ret = i2c_smbus_write_byte(chip->client,
+drivers/iio/light/tsl2772.c:		dev_err(&chip->client->dev,
+drivers/iio/light/tsl2772.c:	mutex_lock(&chip->als_mutex);
+drivers/iio/light/tsl2772.c:	if (chip->tsl2772_chip_status != TSL2772_CHIP_WORKING) {
+drivers/iio/light/tsl2772.c:		dev_err(&chip->client->dev, "%s: device is not enabled\n",
+drivers/iio/light/tsl2772.c:		dev_err(&chip->client->dev,
+drivers/iio/light/tsl2772.c:		ret = chip->als_cur_info.lux; /* return LAST VALUE */
+drivers/iio/light/tsl2772.c:	chip->als_cur_info.als_ch0 = ret;
+drivers/iio/light/tsl2772.c:	chip->als_cur_info.als_ch1 = ret;
+drivers/iio/light/tsl2772.c:	if (chip->als_cur_info.als_ch0 >= chip->als_saturation) {
+drivers/iio/light/tsl2772.c:	if (!chip->als_cur_info.als_ch0) {
+drivers/iio/light/tsl2772.c:		ret = chip->als_cur_info.lux;
+drivers/iio/light/tsl2772.c:	for (p = (struct tsl2772_lux *)chip->tsl2772_device_lux; p->ch0 != 0;
+drivers/iio/light/tsl2772.c:		lux = ((chip->als_cur_info.als_ch0 * p->ch0) -
+drivers/iio/light/tsl2772.c:		       (chip->als_cur_info.als_ch1 * p->ch1)) /
+drivers/iio/light/tsl2772.c:			chip->als_gain_time_scale;
+drivers/iio/light/tsl2772.c:		lux = (lux * chip->settings.als_gain_trim) / 1000;
+drivers/iio/light/tsl2772.c:	chip->als_cur_info.lux = max_lux;
+drivers/iio/light/tsl2772.c:	mutex_unlock(&chip->als_mutex);
+drivers/iio/light/tsl2772.c: *                      chip->prox_data.
+drivers/iio/light/tsl2772.c:	mutex_lock(&chip->prox_mutex);
+drivers/iio/light/tsl2772.c:	switch (chip->id) {
+drivers/iio/light/tsl2772.c:	chip->prox_data = ret;
+drivers/iio/light/tsl2772.c:	mutex_unlock(&chip->prox_mutex);
+drivers/iio/light/tsl2772.c:	struct device_node *of_node = chip->client->dev.of_node;
+drivers/iio/light/tsl2772.c:			chip->settings.prox_power = tsl2772_led_currents[i][1];
+drivers/iio/light/tsl2772.c:	dev_err(&chip->client->dev, "Invalid value %d for led-max-microamp\n",
+drivers/iio/light/tsl2772.c:	struct device_node *of_node = chip->client->dev.of_node;
+drivers/iio/light/tsl2772.c:		dev_err(&chip->client->dev,
+drivers/iio/light/tsl2772.c:			dev_err(&chip->client->dev,
+drivers/iio/light/tsl2772.c:	if (chip->pdata && chip->pdata->platform_default_settings)
+drivers/iio/light/tsl2772.c:		memcpy(&chip->settings, chip->pdata->platform_default_settings,
+drivers/iio/light/tsl2772.c:		memcpy(&chip->settings, &tsl2772_default_settings,
+drivers/iio/light/tsl2772.c:	if (chip->pdata && chip->pdata->platform_lux_table[0].ch0 != 0)
+drivers/iio/light/tsl2772.c:		memcpy(chip->tsl2772_device_lux,
+drivers/iio/light/tsl2772.c:		       chip->pdata->platform_lux_table,
+drivers/iio/light/tsl2772.c:		       sizeof(chip->pdata->platform_lux_table));
+drivers/iio/light/tsl2772.c:		memcpy(chip->tsl2772_device_lux,
+drivers/iio/light/tsl2772.c:		       tsl2772_default_lux_table_group[chip->id],
+drivers/iio/light/tsl2772.c:	ret = i2c_smbus_read_byte_data(chip->client,
+drivers/iio/light/tsl2772.c:		dev_err(&chip->client->dev,
+drivers/iio/light/tsl2772.c:		dev_err(&chip->client->dev,
+drivers/iio/light/tsl2772.c:		dev_err(&chip->client->dev,
+drivers/iio/light/tsl2772.c:		dev_err(&chip->client->dev,
+drivers/iio/light/tsl2772.c:	ret = (chip->settings.als_cal_target * chip->settings.als_gain_trim) /
+drivers/iio/light/tsl2772.c:	chip->settings.als_gain_trim = ret;
+drivers/iio/light/tsl2772.c:	regulator_bulk_disable(ARRAY_SIZE(chip->supplies), chip->supplies);
+drivers/iio/light/tsl2772.c:	chip->tsl2772_config[TSL2772_ALS_TIME] = chip->settings.als_time;
+drivers/iio/light/tsl2772.c:	chip->tsl2772_config[TSL2772_PRX_TIME] = chip->settings.prox_time;
+drivers/iio/light/tsl2772.c:	chip->tsl2772_config[TSL2772_WAIT_TIME] = chip->settings.wait_time;
+drivers/iio/light/tsl2772.c:	chip->tsl2772_config[TSL2772_ALS_PRX_CONFIG] =
+drivers/iio/light/tsl2772.c:		chip->settings.als_prox_config;
+drivers/iio/light/tsl2772.c:	chip->tsl2772_config[TSL2772_ALS_MINTHRESHLO] =
+drivers/iio/light/tsl2772.c:		(chip->settings.als_thresh_low) & 0xFF;
+drivers/iio/light/tsl2772.c:	chip->tsl2772_config[TSL2772_ALS_MINTHRESHHI] =
+drivers/iio/light/tsl2772.c:		(chip->settings.als_thresh_low >> 8) & 0xFF;
+drivers/iio/light/tsl2772.c:	chip->tsl2772_config[TSL2772_ALS_MAXTHRESHLO] =
+drivers/iio/light/tsl2772.c:		(chip->settings.als_thresh_high) & 0xFF;
+drivers/iio/light/tsl2772.c:	chip->tsl2772_config[TSL2772_ALS_MAXTHRESHHI] =
+drivers/iio/light/tsl2772.c:		(chip->settings.als_thresh_high >> 8) & 0xFF;
+drivers/iio/light/tsl2772.c:	chip->tsl2772_config[TSL2772_PERSISTENCE] =
+drivers/iio/light/tsl2772.c:		(chip->settings.prox_persistence & 0xFF) << 4 |
+drivers/iio/light/tsl2772.c:		(chip->settings.als_persistence & 0xFF);
+drivers/iio/light/tsl2772.c:	chip->tsl2772_config[TSL2772_PRX_COUNT] =
+drivers/iio/light/tsl2772.c:			chip->settings.prox_pulse_count;
+drivers/iio/light/tsl2772.c:	chip->tsl2772_config[TSL2772_PRX_MINTHRESHLO] =
+drivers/iio/light/tsl2772.c:			(chip->settings.prox_thres_low) & 0xFF;
+drivers/iio/light/tsl2772.c:	chip->tsl2772_config[TSL2772_PRX_MINTHRESHHI] =
+drivers/iio/light/tsl2772.c:			(chip->settings.prox_thres_low >> 8) & 0xFF;
+drivers/iio/light/tsl2772.c:	chip->tsl2772_config[TSL2772_PRX_MAXTHRESHLO] =
+drivers/iio/light/tsl2772.c:			(chip->settings.prox_thres_high) & 0xFF;
+drivers/iio/light/tsl2772.c:	chip->tsl2772_config[TSL2772_PRX_MAXTHRESHHI] =
+drivers/iio/light/tsl2772.c:			(chip->settings.prox_thres_high >> 8) & 0xFF;
+drivers/iio/light/tsl2772.c:	if (chip->tsl2772_chip_status == TSL2772_CHIP_WORKING) {
+drivers/iio/light/tsl2772.c:		dev_info(&chip->client->dev, "device is already enabled\n");
+drivers/iio/light/tsl2772.c:	chip->tsl2772_config[TSL2772_GAIN] =
+drivers/iio/light/tsl2772.c:		(chip->settings.als_gain & 0xFF) |
+drivers/iio/light/tsl2772.c:		((chip->settings.prox_gain & 0xFF) << 2) |
+drivers/iio/light/tsl2772.c:		(chip->settings.prox_diode << 4) |
+drivers/iio/light/tsl2772.c:		(chip->settings.prox_power << 6);
+drivers/iio/light/tsl2772.c:	als_count = 256 - chip->settings.als_time;
+drivers/iio/light/tsl2772.c:	als_time_us = als_count * tsl2772_int_time_avail[chip->id][3];
+drivers/iio/light/tsl2772.c:	chip->als_saturation = als_count * 768; /* 75% of full scale */
+drivers/iio/light/tsl2772.c:	chip->als_gain_time_scale = als_time_us *
+drivers/iio/light/tsl2772.c:		tsl2772_als_gain[chip->settings.als_gain];
+drivers/iio/light/tsl2772.c:	for (i = 0, dev_reg = chip->tsl2772_config;
+drivers/iio/light/tsl2772.c:		ret = i2c_smbus_write_byte_data(chip->client, reg,
+drivers/iio/light/tsl2772.c:			dev_err(&chip->client->dev,
+drivers/iio/light/tsl2772.c:	if (chip->settings.als_interrupt_en)
+drivers/iio/light/tsl2772.c:	if (chip->settings.prox_interrupt_en)
+drivers/iio/light/tsl2772.c:	ret = i2c_smbus_write_byte(chip->client,
+drivers/iio/light/tsl2772.c:		dev_err(&chip->client->dev,
+drivers/iio/light/tsl2772.c:	chip->tsl2772_chip_status = TSL2772_CHIP_WORKING;
+drivers/iio/light/tsl2772.c:	chip->tsl2772_chip_status = TSL2772_CHIP_SUSPENDED;
+drivers/iio/light/tsl2772.c:	int device_status = chip->tsl2772_chip_status;
+drivers/iio/light/tsl2772.c:	mutex_lock(&chip->als_mutex);
+drivers/iio/light/tsl2772.c:	mutex_lock(&chip->prox_mutex);
+drivers/iio/light/tsl2772.c:	mutex_unlock(&chip->prox_mutex);
+drivers/iio/light/tsl2772.c:	mutex_unlock(&chip->als_mutex);
+drivers/iio/light/tsl2772.c:	if (chip->settings.prox_max_samples_cal < 1 ||
+drivers/iio/light/tsl2772.c:	    chip->settings.prox_max_samples_cal > MAX_SAMPLES_CAL)
+drivers/iio/light/tsl2772.c:	for (i = 0; i < chip->settings.prox_max_samples_cal; i++) {
+drivers/iio/light/tsl2772.c:		prox_history[i] = chip->prox_data;
+drivers/iio/light/tsl2772.c:	for (i = 0; i < chip->settings.prox_max_samples_cal; i++) {
+drivers/iio/light/tsl2772.c:	mean = sample_sum / chip->settings.prox_max_samples_cal;
+drivers/iio/light/tsl2772.c:	chip->settings.prox_thres_high = (max << 1) - mean;
+drivers/iio/light/tsl2772.c:		*length = ARRAY_SIZE(tsl2772_int_time_avail[chip->id]);
+drivers/iio/light/tsl2772.c:		*vals = tsl2772_int_time_avail[chip->id];
+drivers/iio/light/tsl2772.c:	return snprintf(buf, PAGE_SIZE, "%d\n", chip->settings.als_cal_target);
+drivers/iio/light/tsl2772.c:	chip->settings.als_cal_target = value;
+drivers/iio/light/tsl2772.c:			chip->tsl2772_device_lux[i].ch0,
+drivers/iio/light/tsl2772.c:			chip->tsl2772_device_lux[i].ch1);
+drivers/iio/light/tsl2772.c:		if (chip->tsl2772_device_lux[i].ch0 == 0) {
+drivers/iio/light/tsl2772.c:	int value[ARRAY_SIZE(chip->tsl2772_device_lux) * 2 + 1];
+drivers/iio/light/tsl2772.c:	    n > ((ARRAY_SIZE(chip->tsl2772_device_lux) - 1) * 2))
+drivers/iio/light/tsl2772.c:	if (chip->tsl2772_chip_status == TSL2772_CHIP_WORKING) {
+drivers/iio/light/tsl2772.c:	memset(chip->tsl2772_device_lux, 0, sizeof(chip->tsl2772_device_lux));
+drivers/iio/light/tsl2772.c:	memcpy(chip->tsl2772_device_lux, &value[1], (value[0] * 4));
+drivers/iio/light/tsl2772.c:		return chip->settings.als_interrupt_en;
+drivers/iio/light/tsl2772.c:		return chip->settings.prox_interrupt_en;
+drivers/iio/light/tsl2772.c:		chip->settings.als_interrupt_en = val ? true : false;
+drivers/iio/light/tsl2772.c:		chip->settings.prox_interrupt_en = val ? true : false;
+drivers/iio/light/tsl2772.c:				chip->settings.als_thresh_high = val;
+drivers/iio/light/tsl2772.c:				chip->settings.als_thresh_low = val;
+drivers/iio/light/tsl2772.c:				chip->settings.prox_thres_high = val;
+drivers/iio/light/tsl2772.c:				chip->settings.prox_thres_low = val;
+drivers/iio/light/tsl2772.c:			time = chip->settings.als_time;
+drivers/iio/light/tsl2772.c:			time = chip->settings.prox_time;
+drivers/iio/light/tsl2772.c:			(count * tsl2772_int_time_avail[chip->id][3]);
+drivers/iio/light/tsl2772.c:			chip->settings.als_persistence = persistence;
+drivers/iio/light/tsl2772.c:			chip->settings.prox_persistence = persistence;
+drivers/iio/light/tsl2772.c:				*val = chip->settings.als_thresh_high;
+drivers/iio/light/tsl2772.c:				*val = chip->settings.als_thresh_low;
+drivers/iio/light/tsl2772.c:				*val = chip->settings.prox_thres_high;
+drivers/iio/light/tsl2772.c:				*val = chip->settings.prox_thres_low;
+drivers/iio/light/tsl2772.c:			time = chip->settings.als_time;
+drivers/iio/light/tsl2772.c:			persistence = chip->settings.als_persistence;
+drivers/iio/light/tsl2772.c:			time = chip->settings.prox_time;
+drivers/iio/light/tsl2772.c:			persistence = chip->settings.prox_persistence;
+drivers/iio/light/tsl2772.c:			tsl2772_int_time_avail[chip->id][3];
+drivers/iio/light/tsl2772.c:			*val = chip->als_cur_info.lux;
+drivers/iio/light/tsl2772.c:				*val = chip->als_cur_info.als_ch0;
+drivers/iio/light/tsl2772.c:				*val = chip->als_cur_info.als_ch1;
+drivers/iio/light/tsl2772.c:			*val = chip->prox_data;
+drivers/iio/light/tsl2772.c:			*val = tsl2772_als_gain[chip->settings.als_gain];
+drivers/iio/light/tsl2772.c:			*val = tsl2772_prox_gain[chip->settings.prox_gain];
+drivers/iio/light/tsl2772.c:		*val = chip->settings.als_gain_trim;
+drivers/iio/light/tsl2772.c:		*val2 = (256 - chip->settings.als_time) *
+drivers/iio/light/tsl2772.c:			tsl2772_int_time_avail[chip->id][3];
+drivers/iio/light/tsl2772.c:				chip->settings.als_gain = 0;
+drivers/iio/light/tsl2772.c:				chip->settings.als_gain = 1;
+drivers/iio/light/tsl2772.c:				chip->settings.als_gain = 2;
+drivers/iio/light/tsl2772.c:				chip->settings.als_gain = 3;
+drivers/iio/light/tsl2772.c:				chip->settings.prox_gain = 0;
+drivers/iio/light/tsl2772.c:				chip->settings.prox_gain = 1;
+drivers/iio/light/tsl2772.c:				chip->settings.prox_gain = 2;
+drivers/iio/light/tsl2772.c:				chip->settings.prox_gain = 3;
+drivers/iio/light/tsl2772.c:		chip->settings.als_gain_trim = val;
+drivers/iio/light/tsl2772.c:		if (val != 0 || val2 < tsl2772_int_time_avail[chip->id][1] ||
+drivers/iio/light/tsl2772.c:		    val2 > tsl2772_int_time_avail[chip->id][5])
+drivers/iio/light/tsl2772.c:		chip->settings.als_time = 256 -
+drivers/iio/light/tsl2772.c:			(val2 / tsl2772_int_time_avail[chip->id][3]);
+drivers/iio/light/tsl2772.c:	ret = i2c_smbus_write_byte(chip->client,
+drivers/iio/light/tsl2772.c:		dev_err(&chip->client->dev,
+drivers/iio/light/tsl2772.c:	chip->client = clientp;
+drivers/iio/light/tsl2772.c:	chip->supplies[TSL2772_SUPPLY_VDD].supply = "vdd";
+drivers/iio/light/tsl2772.c:	chip->supplies[TSL2772_SUPPLY_VDDIO].supply = "vddio";
+drivers/iio/light/tsl2772.c:				      ARRAY_SIZE(chip->supplies),
+drivers/iio/light/tsl2772.c:				      chip->supplies);
+drivers/iio/light/tsl2772.c:	ret = regulator_bulk_enable(ARRAY_SIZE(chip->supplies), chip->supplies);
+drivers/iio/light/tsl2772.c:	ret = i2c_smbus_read_byte_data(chip->client,
+drivers/iio/light/tsl2772.c:		dev_info(&chip->client->dev,
+drivers/iio/light/tsl2772.c:	mutex_init(&chip->als_mutex);
+drivers/iio/light/tsl2772.c:	mutex_init(&chip->prox_mutex);
+drivers/iio/light/tsl2772.c:	chip->tsl2772_chip_status = TSL2772_CHIP_UNKNOWN;
+drivers/iio/light/tsl2772.c:	chip->pdata = dev_get_platdata(&clientp->dev);
+drivers/iio/light/tsl2772.c:	chip->id = id->driver_data;
+drivers/iio/light/tsl2772.c:	chip->chip_info =
+drivers/iio/light/tsl2772.c:	indio_dev->info = chip->chip_info->info;
+drivers/iio/light/tsl2772.c:	indio_dev->name = chip->client->name;
+drivers/iio/light/tsl2772.c:	indio_dev->num_channels = chip->chip_info->chan_table_elements;
+drivers/iio/light/tsl2772.c:		indio_dev->channels = chip->chip_info->channel_with_events;
+drivers/iio/light/tsl2772.c:		indio_dev->channels = chip->chip_info->channel_without_events;
+drivers/iio/light/tsl2772.c:	regulator_bulk_disable(ARRAY_SIZE(chip->supplies), chip->supplies);
+drivers/iio/light/tsl2772.c:	ret = regulator_bulk_enable(ARRAY_SIZE(chip->supplies), chip->supplies);
+drivers/iio/temperature/maxim_thermocouple.c:	unsigned int storage_bytes = data->chip->read_size;
+drivers/iio/temperature/maxim_thermocouple.c:	if (*val & data->chip->status_bit)
+drivers/iio/temperature/maxim_thermocouple.c:	ret = spi_read(data->spi, data->buffer, data->chip->read_size);
+drivers/iio/temperature/maxim_thermocouple.c:	indio_dev->channels = chip->channels;
+drivers/iio/temperature/maxim_thermocouple.c:	indio_dev->available_scan_masks = chip->scan_masks;
+drivers/iio/temperature/maxim_thermocouple.c:	indio_dev->num_channels = chip->num_channels;
+drivers/infiniband/hw/hfi1/chip.c: * chip-specific function pointers for later use.
+drivers/infiniband/hw/hfi1/init.c: * "extra" is for chip-specific data.
+drivers/infiniband/hw/hfi1/init.c: * Do all the generic driver unit- and chip-independent memory
+drivers/infiniband/hw/hfi1/pcie.c: * Do PCIe cleanup related to dd, after chip-specific cleanup, etc.  Just prior
+drivers/infiniband/hw/hfi1/qsfp.h: * differ (in the chip-specific section), we need a pointer to its head.
+drivers/infiniband/hw/qib/qib.h: * is chip-specific, per-port
+drivers/infiniband/hw/qib/qib.h:	struct qib_chippport_specific *cpspec; /* chip-specific per-port */
+drivers/infiniband/hw/qib/qib.h:	/* last ibcstatus.  opaque outside chip-specific code */
+drivers/infiniband/hw/qib/qib.h: * described above) while fields only used by a particular chip-type are in
+drivers/infiniband/hw/qib/qib.h:	struct qib_chip_specific *cspec; /* chip-specific */
+drivers/infiniband/hw/qib/qib.h:	/* fill out chip-specific fields */
+drivers/infiniband/hw/qib/qib.h:	/* Read/modify/write of GPIO pins (potentially chip-specific */
+drivers/infiniband/hw/qib/qib.h:	 * modify rcvctrl shadow[s] and write to appropriate chip-regs.
+drivers/infiniband/hw/qib/qib.h:/* clean up any per-chip chip-specific stuff */
+drivers/infiniband/hw/qib/qib_diag.c: * @offs: the offset in chip-space
+drivers/infiniband/hw/qib/qib_diag.c:	 * chip-specific code here, so should not make many assumptions.
+drivers/infiniband/hw/qib/qib_eeprom.c:	 * figures out device. This will migrate to chip-specific.
+drivers/infiniband/hw/qib/qib_file_ops.c:	 * array for time being.  If rcd->ctxt > chip-supported,
+drivers/infiniband/hw/qib/qib_iba6120.c: * This file contains all the chip-specific register information and
+drivers/infiniband/hw/qib/qib_iba6120.c:	/* chip-specific hardware errors */
+drivers/infiniband/hw/qib/qib_iba6120.c: * This is in chip-specific code because of all of the register accesses,
+drivers/infiniband/hw/qib/qib_iba6120.c: * Only chip-specific because it's all register accesses
+drivers/infiniband/hw/qib/qib_iba6120.c: * qib_6120_setup_cleanup - clean up any per-chip chip-specific stuff
+drivers/infiniband/hw/qib/qib_iba6120.c: * Set up our chip-specific interrupt handler
+drivers/infiniband/hw/qib/qib_iba6120.c: * qib_6120_get_base_info - set chip-specific flags for user code
+drivers/infiniband/hw/qib/qib_iba6120.c: * Modify the RCVCTRL register in chip-specific way. This
+drivers/infiniband/hw/qib/qib_iba6120.c: * location is chip-specific, but the needed operations are
+drivers/infiniband/hw/qib/qib_iba6120.c: * Modify the SENDCTRL register in chip-specific way. This
+drivers/infiniband/hw/qib/qib_iba6120.c: * qib_init_iba6120_funcs - set up the chip-specific function pointers
+drivers/infiniband/hw/qib/qib_iba6120.c: * chip-specific function pointers for later use.
+drivers/infiniband/hw/qib/qib_iba6120.c:	/* initialize chip-specific variables */
+drivers/infiniband/hw/qib/qib_iba7220.c: * This file contains almost all the chip-specific register information and
+drivers/infiniband/hw/qib/qib_iba7220.c:	/* chip-specific hardware errors */
+drivers/infiniband/hw/qib/qib_iba7220.c: * This is in chip-specific code because of all of the register accesses,
+drivers/infiniband/hw/qib/qib_iba7220.c: * Only chip-specific because it's all register accesses
+drivers/infiniband/hw/qib/qib_iba7220.c: * qib_setup_7220_cleanup - clean up any per-chip chip-specific stuff
+drivers/infiniband/hw/qib/qib_iba7220.c: * Set up our chip-specific interrupt handler.
+drivers/infiniband/hw/qib/qib_iba7220.c: * qib_init_7220_get_base_info - set chip-specific flags for user code
+drivers/infiniband/hw/qib/qib_iba7220.c: * Modify the RCVCTRL register in chip-specific way. This
+drivers/infiniband/hw/qib/qib_iba7220.c: * location is chip-specifc, but the needed operations are
+drivers/infiniband/hw/qib/qib_iba7220.c: * Modify the SENDCTRL register in chip-specific way. This
+drivers/infiniband/hw/qib/qib_iba7220.c: * qib_init_iba7220_funcs - set up the chip-specific function pointers
+drivers/infiniband/hw/qib/qib_iba7220.c: * chip-specific function pointers for later use.
+drivers/infiniband/hw/qib/qib_iba7220.c:	/* initialize chip-specific variables */
+drivers/infiniband/hw/qib/qib_iba7322.c: * This file contains almost all the chip-specific register information and
+drivers/infiniband/hw/qib/qib_iba7322.c: * This is in chip-specific code because of all of the register accesses,
+drivers/infiniband/hw/qib/qib_iba7322.c: * Only chip-specific because it's all register accesses
+drivers/infiniband/hw/qib/qib_iba7322.c: * Set up our chip-specific interrupt handler.
+drivers/infiniband/hw/qib/qib_iba7322.c: * qib_init_7322_get_base_info - set chip-specific flags for user code
+drivers/infiniband/hw/qib/qib_iba7322.c: * Modify the RCVCTRL register in chip-specific way. This
+drivers/infiniband/hw/qib/qib_iba7322.c: * location is chip-specifc, but the needed operations are
+drivers/infiniband/hw/qib/qib_iba7322.c: * Modify the SENDCTRL register in chip-specific way. This
+drivers/infiniband/hw/qib/qib_iba7322.c: * qib_init_iba7322_funcs - set up the chip-specific function pointers
+drivers/infiniband/hw/qib/qib_iba7322.c: * chip-specific function pointers for later use.
+drivers/infiniband/hw/qib/qib_iba7322.c:	/* initialize chip-specific variables */
+drivers/infiniband/hw/qib/qib_iba7322.c:	/* Get correct offset in chip-space, and in source table */
+drivers/infiniband/hw/qib/qib_init.c:	 * calculated in chip-specific code because it may cause some
+drivers/infiniband/hw/qib/qib_init.c:	 * chip-specific adjustments to be made.
+drivers/infiniband/hw/qib/qib_init.c:	/* Bypass most chip-init, to get to device creation */
+drivers/infiniband/hw/qib/qib_init.c: * "extra" is for chip-specific data.
+drivers/infiniband/hw/qib/qib_init.c: * Do all the generic driver unit- and chip-independent memory
+drivers/infiniband/hw/qib/qib_init.c:	 * Clean up chip-specific stuff.
+drivers/infiniband/hw/qib/qib_intr.c:	 * call the chip-specific code to take appropriate actions.
+drivers/infiniband/hw/qib/qib_intr.c:			goto skip_ibchange; /* chip-code handled */
+drivers/infiniband/hw/qib/qib_intr.c:			goto skip_ibchange; /* chip-code handled */
+drivers/infiniband/hw/qib/qib_pcie.c: * from qib_pcie_params, which every chip-specific
+drivers/infiniband/hw/qib/qib_pcie.c: * Do PCIe cleanup, after chip-specific cleanup, etc.  Just prior
+drivers/infiniband/hw/qib/qib_pcie.c: * to move all the pcie code out of the chip-specific driver code.
+drivers/infiniband/hw/qib/qib_qsfp.h: * it will be part of port-chip-specific data if a board supports QSFP.
+drivers/infiniband/hw/qib/qib_qsfp.h: * differ (in the chip-specific section), we need a pointer to its head.
+drivers/infiniband/hw/qib/qib_sd7220.c:		 * Suppress it around the reset, both in chip-level
+drivers/infiniband/hw/qib/qib_sd7220.c:			 * loc encodes chip-select as well as address
+drivers/infiniband/hw/qib/qib_twsi.c: * have been moved to chip-specific files.
+drivers/input/keyboard/mcs_touchkey.c:	val = i2c_smbus_read_byte_data(client, chip->status_reg);
+drivers/input/keyboard/mcs_touchkey.c:	pressed = (val & (1 << chip->pressbit)) >> chip->pressbit;
+drivers/input/keyboard/mcs_touchkey.c:	if (chip->press_invert)
+drivers/input/keyboard/mcs_touchkey.c:		pressed ^= chip->press_invert;
+drivers/input/keyboard/mcs_touchkey.c:		key_val = val & (0xff >> (8 - chip->pressbit));
+drivers/input/keyboard/mcs_touchkey.c:		key_val -= chip->baseval;
+drivers/input/keyboard/mtk-pmic-keys.c:	keys->regmap = pmic_chip->regmap;
+drivers/input/keyboard/tca6416-keypad.c:	error = chip->io_size > 8 ?
+drivers/input/keyboard/tca6416-keypad.c:		i2c_smbus_write_word_data(chip->client, reg << 1, val) :
+drivers/input/keyboard/tca6416-keypad.c:		i2c_smbus_write_byte_data(chip->client, reg, val);
+drivers/input/keyboard/tca6416-keypad.c:		dev_err(&chip->client->dev,
+drivers/input/keyboard/tca6416-keypad.c:	retval = chip->io_size > 8 ?
+drivers/input/keyboard/tca6416-keypad.c:		 i2c_smbus_read_word_data(chip->client, reg << 1) :
+drivers/input/keyboard/tca6416-keypad.c:		 i2c_smbus_read_byte_data(chip->client, reg);
+drivers/input/keyboard/tca6416-keypad.c:		dev_err(&chip->client->dev, "%s failed, reg: %d, error: %d\n",
+drivers/input/keyboard/tca6416-keypad.c:	struct input_dev *input = chip->input;
+drivers/input/keyboard/tca6416-keypad.c:	reg_val &= chip->pinmask;
+drivers/input/keyboard/tca6416-keypad.c:	val = reg_val ^ chip->reg_input;
+drivers/input/keyboard/tca6416-keypad.c:	chip->reg_input = reg_val;
+drivers/input/keyboard/tca6416-keypad.c:			struct tca6416_button *button = &chip->buttons[pin_index];
+drivers/input/keyboard/tca6416-keypad.c:		if (chip->pinmask & (1 << i))
+drivers/input/keyboard/tca6416-keypad.c:	schedule_delayed_work(&chip->dwork, msecs_to_jiffies(100));
+drivers/input/keyboard/tca6416-keypad.c:	if (chip->use_polling)
+drivers/input/keyboard/tca6416-keypad.c:		schedule_delayed_work(&chip->dwork, msecs_to_jiffies(100));
+drivers/input/keyboard/tca6416-keypad.c:		enable_irq(chip->irqnum);
+drivers/input/keyboard/tca6416-keypad.c:	if (chip->use_polling)
+drivers/input/keyboard/tca6416-keypad.c:		cancel_delayed_work_sync(&chip->dwork);
+drivers/input/keyboard/tca6416-keypad.c:		disable_irq(chip->irqnum);
+drivers/input/keyboard/tca6416-keypad.c:	error = tca6416_read_reg(chip, TCA6416_OUTPUT, &chip->reg_output);
+drivers/input/keyboard/tca6416-keypad.c:	error = tca6416_read_reg(chip, TCA6416_DIRECTION, &chip->reg_direction);
+drivers/input/keyboard/tca6416-keypad.c:				  chip->reg_direction | chip->pinmask);
+drivers/input/keyboard/tca6416-keypad.c:	error = tca6416_read_reg(chip, TCA6416_DIRECTION, &chip->reg_direction);
+drivers/input/keyboard/tca6416-keypad.c:	error = tca6416_read_reg(chip, TCA6416_INPUT, &chip->reg_input);
+drivers/input/keyboard/tca6416-keypad.c:	chip->reg_input &= chip->pinmask;
+drivers/input/keyboard/tca6416-keypad.c:	chip->client = client;
+drivers/input/keyboard/tca6416-keypad.c:	chip->input = input;
+drivers/input/keyboard/tca6416-keypad.c:	chip->io_size = id->driver_data;
+drivers/input/keyboard/tca6416-keypad.c:	chip->pinmask = pdata->pinmask;
+drivers/input/keyboard/tca6416-keypad.c:	chip->use_polling = pdata->use_polling;
+drivers/input/keyboard/tca6416-keypad.c:	INIT_DELAYED_WORK(&chip->dwork, tca6416_keys_work_func);
+drivers/input/keyboard/tca6416-keypad.c:		chip->buttons[i] = pdata->buttons[i];
+drivers/input/keyboard/tca6416-keypad.c:	if (!chip->use_polling) {
+drivers/input/keyboard/tca6416-keypad.c:			chip->irqnum = gpio_to_irq(client->irq);
+drivers/input/keyboard/tca6416-keypad.c:			chip->irqnum = client->irq;
+drivers/input/keyboard/tca6416-keypad.c:		error = request_threaded_irq(chip->irqnum, NULL,
+drivers/input/keyboard/tca6416-keypad.c:				chip->irqnum, error);
+drivers/input/keyboard/tca6416-keypad.c:		disable_irq(chip->irqnum);
+drivers/input/keyboard/tca6416-keypad.c:	if (!chip->use_polling) {
+drivers/input/keyboard/tca6416-keypad.c:		free_irq(chip->irqnum, chip);
+drivers/input/keyboard/tca6416-keypad.c:		enable_irq(chip->irqnum);
+drivers/input/keyboard/tca6416-keypad.c:	if (!chip->use_polling) {
+drivers/input/keyboard/tca6416-keypad.c:		free_irq(chip->irqnum, chip);
+drivers/input/keyboard/tca6416-keypad.c:		enable_irq(chip->irqnum);
+drivers/input/keyboard/tca6416-keypad.c:	input_unregister_device(chip->input);
+drivers/input/keyboard/tca6416-keypad.c:		enable_irq_wake(chip->irqnum);
+drivers/input/keyboard/tca6416-keypad.c:		disable_irq_wake(chip->irqnum);
+drivers/input/misc/88pm860x_onkey.c:	info->i2c = (chip->id == CHIP_PM8607) ? chip->client : chip->companion;
+drivers/input/misc/88pm860x_onkey.c:		dev_err(chip->dev, "Failed to allocate input dev\n");
+drivers/input/misc/88pm860x_onkey.c:		dev_err(chip->dev, "Can't register input device: %d\n", ret);
+drivers/input/misc/88pm860x_onkey.c:		dev_err(chip->dev, "Failed to request IRQ: #%d: %d\n",
+drivers/input/misc/88pm860x_onkey.c:		chip->wakeup_flag |= 1 << PM8607_IRQ_ONKEY;
+drivers/input/misc/88pm860x_onkey.c:		chip->wakeup_flag &= ~(1 << PM8607_IRQ_ONKEY);
+drivers/input/misc/ad714x-i2c.c:	struct i2c_client *client = to_i2c_client(chip->dev);
+drivers/input/misc/ad714x-i2c.c:	chip->xfer_buf[0] = cpu_to_be16(reg);
+drivers/input/misc/ad714x-i2c.c:	chip->xfer_buf[1] = cpu_to_be16(data);
+drivers/input/misc/ad714x-i2c.c:	error = i2c_master_send(client, (u8 *)chip->xfer_buf,
+drivers/input/misc/ad714x-i2c.c:				2 * sizeof(*chip->xfer_buf));
+drivers/input/misc/ad714x-i2c.c:	struct i2c_client *client = to_i2c_client(chip->dev);
+drivers/input/misc/ad714x-i2c.c:	chip->xfer_buf[0] = cpu_to_be16(reg);
+drivers/input/misc/ad714x-i2c.c:	error = i2c_master_send(client, (u8 *)chip->xfer_buf,
+drivers/input/misc/ad714x-i2c.c:				sizeof(*chip->xfer_buf));
+drivers/input/misc/ad714x-i2c.c:		error = i2c_master_recv(client, (u8 *)chip->xfer_buf,
+drivers/input/misc/ad714x-i2c.c:					len * sizeof(*chip->xfer_buf));
+drivers/input/misc/ad714x-i2c.c:		data[i] = be16_to_cpu(chip->xfer_buf[i]);
+drivers/input/misc/ad714x-spi.c:	struct spi_device *spi = to_spi_device(chip->dev);
+drivers/input/misc/ad714x-spi.c:	chip->xfer_buf[0] = cpu_to_be16(AD714x_SPI_CMD_PREFIX |
+drivers/input/misc/ad714x-spi.c:	xfer[0].tx_buf = &chip->xfer_buf[0];
+drivers/input/misc/ad714x-spi.c:	xfer[0].len = sizeof(chip->xfer_buf[0]);
+drivers/input/misc/ad714x-spi.c:	xfer[1].rx_buf = &chip->xfer_buf[1];
+drivers/input/misc/ad714x-spi.c:	xfer[1].len = sizeof(chip->xfer_buf[1]) * len;
+drivers/input/misc/ad714x-spi.c:		dev_err(chip->dev, "SPI read error: %d\n", error);
+drivers/input/misc/ad714x-spi.c:		data[i] = be16_to_cpu(chip->xfer_buf[i + 1]);
+drivers/input/misc/ad714x-spi.c:	struct spi_device *spi = to_spi_device(chip->dev);
+drivers/input/misc/ad714x-spi.c:	chip->xfer_buf[0] = cpu_to_be16(AD714x_SPI_CMD_PREFIX | reg);
+drivers/input/misc/ad714x-spi.c:	chip->xfer_buf[1] = cpu_to_be16(data);
+drivers/input/misc/ad714x-spi.c:	error = spi_write(spi, (u8 *)chip->xfer_buf,
+drivers/input/misc/ad714x-spi.c:			  2 * sizeof(*chip->xfer_buf));
+drivers/input/misc/ad714x-spi.c:		dev_err(chip->dev, "SPI write error: %d\n", error);
+drivers/input/misc/max8925_onkey.c:	info->i2c = chip->i2c;
+drivers/input/misc/max8925_onkey.c:		dev_err(chip->dev, "Failed to request IRQ: #%d: %d\n",
+drivers/input/misc/max8925_onkey.c:		dev_err(chip->dev, "Failed to request IRQ: #%d: %d\n",
+drivers/input/misc/max8925_onkey.c:		dev_err(chip->dev, "Can't register input device: %d\n", error);
+drivers/input/misc/max8925_onkey.c:		chip->wakeup_flag |= 1 << info->irq[0];
+drivers/input/misc/max8925_onkey.c:		chip->wakeup_flag |= 1 << info->irq[1];
+drivers/input/misc/max8925_onkey.c:		chip->wakeup_flag &= ~(1 << info->irq[0]);
+drivers/input/misc/max8925_onkey.c:		chip->wakeup_flag &= ~(1 << info->irq[1]);
+drivers/input/misc/max8997_haptic.c:	if (chip->mode == MAX8997_EXTERNAL_MODE) {
+drivers/input/misc/max8997_haptic.c:		unsigned int duty = chip->pwm_period * chip->level / 100;
+drivers/input/misc/max8997_haptic.c:		ret = pwm_config(chip->pwm, duty, chip->pwm_period);
+drivers/input/misc/max8997_haptic.c:			if (chip->level <= i * 100 / 64) {
+drivers/input/misc/max8997_haptic.c:		switch (chip->internal_mode_pattern) {
+drivers/input/misc/max8997_haptic.c:			max8997_write_reg(chip->client,
+drivers/input/misc/max8997_haptic.c:			max8997_write_reg(chip->client,
+drivers/input/misc/max8997_haptic.c:			max8997_write_reg(chip->client,
+drivers/input/misc/max8997_haptic.c:			max8997_write_reg(chip->client,
+drivers/input/misc/max8997_haptic.c:	value = chip->type << MAX8997_MOTOR_TYPE_SHIFT |
+drivers/input/misc/max8997_haptic.c:		chip->enabled << MAX8997_ENABLE_SHIFT |
+drivers/input/misc/max8997_haptic.c:		chip->mode << MAX8997_MODE_SHIFT | chip->pwm_divisor;
+drivers/input/misc/max8997_haptic.c:	max8997_write_reg(chip->client, MAX8997_HAPTIC_REG_CONF2, value);
+drivers/input/misc/max8997_haptic.c:	if (chip->mode == MAX8997_INTERNAL_MODE && chip->enabled) {
+drivers/input/misc/max8997_haptic.c:		value = chip->internal_mode_pattern << MAX8997_CYCLE_SHIFT |
+drivers/input/misc/max8997_haptic.c:			chip->internal_mode_pattern << MAX8997_SIG_PERIOD_SHIFT |
+drivers/input/misc/max8997_haptic.c:			chip->internal_mode_pattern << MAX8997_SIG_DUTY_SHIFT |
+drivers/input/misc/max8997_haptic.c:			chip->internal_mode_pattern << MAX8997_PWM_DUTY_SHIFT;
+drivers/input/misc/max8997_haptic.c:		max8997_write_reg(chip->client,
+drivers/input/misc/max8997_haptic.c:		switch (chip->internal_mode_pattern) {
+drivers/input/misc/max8997_haptic.c:			value = chip->pattern_cycle << 4;
+drivers/input/misc/max8997_haptic.c:			max8997_write_reg(chip->client,
+drivers/input/misc/max8997_haptic.c:			value = chip->pattern_signal_period;
+drivers/input/misc/max8997_haptic.c:			max8997_write_reg(chip->client,
+drivers/input/misc/max8997_haptic.c:			value = chip->pattern_cycle;
+drivers/input/misc/max8997_haptic.c:			max8997_write_reg(chip->client,
+drivers/input/misc/max8997_haptic.c:			value = chip->pattern_signal_period;
+drivers/input/misc/max8997_haptic.c:			max8997_write_reg(chip->client,
+drivers/input/misc/max8997_haptic.c:			value = chip->pattern_cycle << 4;
+drivers/input/misc/max8997_haptic.c:			max8997_write_reg(chip->client,
+drivers/input/misc/max8997_haptic.c:			value = chip->pattern_signal_period;
+drivers/input/misc/max8997_haptic.c:			max8997_write_reg(chip->client,
+drivers/input/misc/max8997_haptic.c:			value = chip->pattern_cycle;
+drivers/input/misc/max8997_haptic.c:			max8997_write_reg(chip->client,
+drivers/input/misc/max8997_haptic.c:			value = chip->pattern_signal_period;
+drivers/input/misc/max8997_haptic.c:			max8997_write_reg(chip->client,
+drivers/input/misc/max8997_haptic.c:	mutex_lock(&chip->mutex);
+drivers/input/misc/max8997_haptic.c:		dev_err(chip->dev, "set_pwm_cycle failed, error: %d\n", error);
+drivers/input/misc/max8997_haptic.c:	if (!chip->enabled) {
+drivers/input/misc/max8997_haptic.c:		error = regulator_enable(chip->regulator);
+drivers/input/misc/max8997_haptic.c:			dev_err(chip->dev, "Failed to enable regulator\n");
+drivers/input/misc/max8997_haptic.c:		if (chip->mode == MAX8997_EXTERNAL_MODE) {
+drivers/input/misc/max8997_haptic.c:			error = pwm_enable(chip->pwm);
+drivers/input/misc/max8997_haptic.c:				dev_err(chip->dev, "Failed to enable PWM\n");
+drivers/input/misc/max8997_haptic.c:				regulator_disable(chip->regulator);
+drivers/input/misc/max8997_haptic.c:		chip->enabled = true;
+drivers/input/misc/max8997_haptic.c:	mutex_unlock(&chip->mutex);
+drivers/input/misc/max8997_haptic.c:	mutex_lock(&chip->mutex);
+drivers/input/misc/max8997_haptic.c:	if (chip->enabled) {
+drivers/input/misc/max8997_haptic.c:		chip->enabled = false;
+drivers/input/misc/max8997_haptic.c:		if (chip->mode == MAX8997_EXTERNAL_MODE)
+drivers/input/misc/max8997_haptic.c:			pwm_disable(chip->pwm);
+drivers/input/misc/max8997_haptic.c:		regulator_disable(chip->regulator);
+drivers/input/misc/max8997_haptic.c:	mutex_unlock(&chip->mutex);
+drivers/input/misc/max8997_haptic.c:	if (chip->level)
+drivers/input/misc/max8997_haptic.c:	chip->level = effect->u.rumble.strong_magnitude;
+drivers/input/misc/max8997_haptic.c:	if (!chip->level)
+drivers/input/misc/max8997_haptic.c:		chip->level = effect->u.rumble.weak_magnitude;
+drivers/input/misc/max8997_haptic.c:	schedule_work(&chip->work);
+drivers/input/misc/max8997_haptic.c:	cancel_work_sync(&chip->work);
+drivers/input/misc/max8997_haptic.c:	INIT_WORK(&chip->work, max8997_haptic_play_effect_work);
+drivers/input/misc/max8997_haptic.c:	mutex_init(&chip->mutex);
+drivers/input/misc/max8997_haptic.c:	chip->client = iodev->haptic;
+drivers/input/misc/max8997_haptic.c:	chip->dev = &pdev->dev;
+drivers/input/misc/max8997_haptic.c:	chip->input_dev = input_dev;
+drivers/input/misc/max8997_haptic.c:	chip->pwm_period = haptic_pdata->pwm_period;
+drivers/input/misc/max8997_haptic.c:	chip->type = haptic_pdata->type;
+drivers/input/misc/max8997_haptic.c:	chip->mode = haptic_pdata->mode;
+drivers/input/misc/max8997_haptic.c:	chip->pwm_divisor = haptic_pdata->pwm_divisor;
+drivers/input/misc/max8997_haptic.c:	switch (chip->mode) {
+drivers/input/misc/max8997_haptic.c:		chip->internal_mode_pattern =
+drivers/input/misc/max8997_haptic.c:		chip->pattern_cycle = haptic_pdata->pattern_cycle;
+drivers/input/misc/max8997_haptic.c:		chip->pattern_signal_period =
+drivers/input/misc/max8997_haptic.c:		chip->pwm = pwm_request(haptic_pdata->pwm_channel_id,
+drivers/input/misc/max8997_haptic.c:		if (IS_ERR(chip->pwm)) {
+drivers/input/misc/max8997_haptic.c:			error = PTR_ERR(chip->pwm);
+drivers/input/misc/max8997_haptic.c:		pwm_apply_args(chip->pwm);
+drivers/input/misc/max8997_haptic.c:			"Invalid chip mode specified (%d)\n", chip->mode);
+drivers/input/misc/max8997_haptic.c:	chip->regulator = regulator_get(&pdev->dev, "inmotor");
+drivers/input/misc/max8997_haptic.c:	if (IS_ERR(chip->regulator)) {
+drivers/input/misc/max8997_haptic.c:		error = PTR_ERR(chip->regulator);
+drivers/input/misc/max8997_haptic.c:	regulator_put(chip->regulator);
+drivers/input/misc/max8997_haptic.c:	if (chip->mode == MAX8997_EXTERNAL_MODE)
+drivers/input/misc/max8997_haptic.c:		pwm_free(chip->pwm);
+drivers/input/misc/max8997_haptic.c:	input_unregister_device(chip->input_dev);
+drivers/input/misc/max8997_haptic.c:	regulator_put(chip->regulator);
+drivers/input/misc/max8997_haptic.c:	if (chip->mode == MAX8997_EXTERNAL_MODE)
+drivers/input/misc/max8997_haptic.c:		pwm_free(chip->pwm);
+drivers/input/touchscreen/88pm860x-ts.c:			dev_dbg(chip->dev, "z1:%d, z2:%d, rt:%d\n",
+drivers/input/touchscreen/88pm860x-ts.c:		dev_dbg(chip->dev, "pen down at [%d, %d].\n", x, y);
+drivers/input/touchscreen/88pm860x-ts.c:		dev_dbg(chip->dev, "pen release\n");
+drivers/input/touchscreen/88pm860x-ts.c:	struct i2c_client *i2c = (chip->id == CHIP_PM8607) ? chip->client \
+drivers/input/touchscreen/88pm860x-ts.c:				 : chip->companion;
+drivers/input/touchscreen/88pm860x-ts.c:	struct i2c_client *i2c = (chip->id == CHIP_PM8607) ? chip->client \
+drivers/input/touchscreen/88pm860x-ts.c:				 : chip->companion;
+drivers/input/touchscreen/88pm860x-ts.c:		dev_err(chip->dev, "Failed to register touch!\n");
+drivers/input/touchscreen/goodix.c:	return ts->chip->check_config(ts, cfg);
+drivers/input/touchscreen/goodix.c:	error = goodix_i2c_write(ts->client, ts->chip->config_addr, cfg->data,
+drivers/input/touchscreen/goodix.c:	error = goodix_i2c_read(ts->client, ts->chip->config_addr,
+drivers/input/touchscreen/goodix.c:				config, ts->chip->config_len);
+drivers/input/touchscreen/ili210x.c:	for (i = 0; i < priv->chip->max_touches; i++) {
+drivers/input/touchscreen/ili210x.c:		touch = priv->chip->parse_touch_data(touchdata, i, &x, &y);
+drivers/input/touchscreen/ili210x.c:		error = chip->get_touch_data(client, touchdata);
+drivers/input/touchscreen/ili210x.c:		keep_polling = chip->continue_polling(touchdata, touch);
+drivers/input/touchscreen/ili210x.c:	return priv->chip->has_calibrate_reg;
+drivers/input/touchscreen/ili210x.c:	max_xy = (chip->resolution ?: SZ_64K) - 1;
+drivers/input/touchscreen/ili210x.c:	error = input_mt_init_slots(input, priv->chip->max_touches,
+drivers/input/touchscreen/pixcir_i2c_ts.c:	i = chip->has_hw_ids ? 1 : 0;
+drivers/input/touchscreen/pixcir_i2c_ts.c:	readsize = 2 + tsdata->chip->max_fingers * (4 + i);
+drivers/input/touchscreen/pixcir_i2c_ts.c:	if (touch > tsdata->chip->max_fingers)
+drivers/input/touchscreen/pixcir_i2c_ts.c:		touch = tsdata->chip->max_fingers;
+drivers/input/touchscreen/pixcir_i2c_ts.c:		if (chip->has_hw_ids) {
+drivers/input/touchscreen/pixcir_i2c_ts.c:	if (!ts->chip->has_hw_ids)
+drivers/input/touchscreen/pixcir_i2c_ts.c:		if (chip->has_hw_ids) {
+drivers/input/touchscreen/pixcir_i2c_ts.c:	error = input_mt_init_slots(input, tsdata->chip->max_fingers,
+drivers/iommu/Makefile:obj-$(CONFIG_ROCKCHIP_IOMMU) += rockchip-iommu.o
+drivers/iommu/amd_iommu.c:	ret = parent->chip->irq_set_affinity(parent, mask, force);
+drivers/iommu/hyperv-iommu.c:	ret = parent->chip->irq_set_affinity(parent, mask, force);
+drivers/iommu/intel_irq_remapping.c:	ret = parent->chip->irq_set_affinity(parent, mask, force);
+drivers/irqchip/exynos-combiner.c:	if (chip && chip->irq_set_affinity)
+drivers/irqchip/exynos-combiner.c:		return chip->irq_set_affinity(data, mask_val, force);
+drivers/irqchip/irq-alpine-msi.c:	d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);
+drivers/irqchip/irq-gic-v2m.c:	d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);
+drivers/irqchip/irq-gic-v3-mbi.c:	return d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);
+drivers/irqchip/irq-gic.c:IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init);
+drivers/irqchip/irq-mbigen.c:				      &mbigen_irq_chip, mgn_chip->base);
+drivers/irqchip/irq-mbigen.c:	mgn_chip->pdev = pdev;
+drivers/irqchip/irq-mbigen.c:	mgn_chip->base = devm_ioremap(&pdev->dev, res->start,
+drivers/irqchip/irq-mbigen.c:	if (!mgn_chip->base) {
+drivers/irqchip/irq-mtk-cirq.c:	ret = data->chip->irq_set_type(data, type);
+drivers/irqchip/irq-mtk-sysirq.c:	ret = data->chip->irq_set_type(data, type);
+drivers/irqchip/irq-mvebu-odmi.c:	d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);
+drivers/irqchip/irq-mvebu-pic.c:	irq_chip->name = dev_name(&pdev->dev);
+drivers/irqchip/irq-mvebu-pic.c:	irq_chip->irq_mask = mvebu_pic_mask_irq;
+drivers/irqchip/irq-mvebu-pic.c:	irq_chip->irq_unmask = mvebu_pic_unmask_irq;
+drivers/irqchip/irq-mvebu-pic.c:	irq_chip->irq_eoi = mvebu_pic_eoi_irq;
+drivers/irqchip/irq-partition-percpu.c:	    chip->irq_mask)
+drivers/irqchip/irq-partition-percpu.c:		chip->irq_mask(data);
+drivers/irqchip/irq-partition-percpu.c:	    chip->irq_unmask)
+drivers/irqchip/irq-partition-percpu.c:		chip->irq_unmask(data);
+drivers/irqchip/irq-partition-percpu.c:	    chip->irq_set_irqchip_state)
+drivers/irqchip/irq-partition-percpu.c:		return chip->irq_set_irqchip_state(data, which, val);
+drivers/irqchip/irq-partition-percpu.c:	    chip->irq_get_irqchip_state)
+drivers/irqchip/irq-partition-percpu.c:		return chip->irq_get_irqchip_state(data, which, val);
+drivers/irqchip/irq-partition-percpu.c:	if (chip->irq_set_type)
+drivers/irqchip/irq-partition-percpu.c:		return chip->irq_set_type(data, type);
+drivers/irqchip/irq-partition-percpu.c:	seq_printf(p, " %5s-%lu", chip->name, data->hwirq);
+drivers/irqchip/irq-renesas-intc-irqpin.c:	irq_chip->name = "intc-irqpin";
+drivers/irqchip/irq-renesas-intc-irqpin.c:	irq_chip->parent_device = dev;
+drivers/irqchip/irq-renesas-intc-irqpin.c:	irq_chip->irq_mask = disable_fn;
+drivers/irqchip/irq-renesas-intc-irqpin.c:	irq_chip->irq_unmask = enable_fn;
+drivers/irqchip/irq-renesas-intc-irqpin.c:	irq_chip->irq_set_type = intc_irqpin_irq_set_type;
+drivers/irqchip/irq-renesas-intc-irqpin.c:	irq_chip->irq_set_wake = intc_irqpin_irq_set_wake;
+drivers/irqchip/irq-renesas-intc-irqpin.c:	irq_chip->flags	= IRQCHIP_MASK_ON_SUSPEND;
+drivers/irqchip/irq-tango.c:	return readl_relaxed(chip->base + reg);
+drivers/irqchip/irq-tango.c:	writel_relaxed(val, chip->base + reg);
+drivers/irqchip/irq-tango.c:	status_lo = intc_readl(chip, chip->ctl + IRQ_STATUS);
+drivers/irqchip/irq-tango.c:	status_hi = intc_readl(chip, chip->ctl + IRQ_CTL_HI + IRQ_STATUS);
+drivers/irqchip/irq-tango.c:	unsigned long ctl_base = chip->ctl + ctl_offs;
+drivers/irqchip/irq-tango.c:	gc->reg_base = chip->base;
+drivers/irqchip/irq-tango.c:	chip->ctl = res.start - baseres->start;
+drivers/irqchip/irq-tango.c:	chip->base = base;
+drivers/irqchip/irq-ts4800.c:	irq_chip->name = dev_name(&pdev->dev);
+drivers/irqchip/irq-ts4800.c:	irq_chip->irq_mask = ts4800_irq_mask;
+drivers/irqchip/irq-ts4800.c:	irq_chip->irq_unmask = ts4800_irq_unmask;
+drivers/leds/leds-88pm860x.c:	dev_dbg(chip->dev, "Update LED. (reg:%d, brightness:%d)\n",
+drivers/leds/leds-88pm860x.c:	data->i2c = (chip->id == CHIP_PM8606) ? chip->client : chip->companion;
+drivers/leds/leds-88pm860x.c:	ret = devm_led_classdev_register(chip->dev, &data->cdev);
+drivers/leds/leds-an30259a.c:	mutex_lock(&led->chip->mutex);
+drivers/leds/leds-an30259a.c:	ret = regmap_read(led->chip->regmap, AN30259A_REG_LED_ON, &led_on);
+drivers/leds/leds-an30259a.c:		ret = regmap_write(led->chip->regmap,
+drivers/leds/leds-an30259a.c:	ret = regmap_write(led->chip->regmap, AN30259A_REG_LED_ON, led_on);
+drivers/leds/leds-an30259a.c:	ret = regmap_write(led->chip->regmap, AN30259A_REG_LEDCC(led->num),
+drivers/leds/leds-an30259a.c:	mutex_unlock(&led->chip->mutex);
+drivers/leds/leds-an30259a.c:	mutex_lock(&led->chip->mutex);
+drivers/leds/leds-an30259a.c:	ret = regmap_write(led->chip->regmap, AN30259A_REG_LEDCNT2(num),
+drivers/leds/leds-an30259a.c:	ret = regmap_write(led->chip->regmap, AN30259A_REG_LEDCNT3(num),
+drivers/leds/leds-an30259a.c:	ret = regmap_write(led->chip->regmap, AN30259A_REG_LEDCNT4(num),
+drivers/leds/leds-an30259a.c:	ret = regmap_write(led->chip->regmap, AN30259A_REG_SLOPE(num),
+drivers/leds/leds-an30259a.c:	ret = regmap_read(led->chip->regmap, AN30259A_REG_LED_ON, &led_on);
+drivers/leds/leds-an30259a.c:	ret = regmap_write(led->chip->regmap, AN30259A_REG_LED_ON, led_on);
+drivers/leds/leds-an30259a.c:	mutex_unlock(&led->chip->mutex);
+drivers/leds/leds-an30259a.c:		led = &chip->leds[i];
+drivers/leds/leds-an30259a.c:	chip->num_leds = i;
+drivers/leds/leds-an30259a.c:		err = regmap_read(chip->regmap, AN30259A_REG_LED_ON, &led_on);
+drivers/leds/leds-an30259a.c:		regmap_read(chip->regmap, AN30259A_REG_LEDCC(led->num),
+drivers/leds/leds-an30259a.c:	mutex_init(&chip->mutex);
+drivers/leds/leds-an30259a.c:	chip->client = client;
+drivers/leds/leds-an30259a.c:	chip->regmap = devm_regmap_init_i2c(client, &an30259a_regmap_config);
+drivers/leds/leds-an30259a.c:	if (IS_ERR(chip->regmap)) {
+drivers/leds/leds-an30259a.c:		err = PTR_ERR(chip->regmap);
+drivers/leds/leds-an30259a.c:	for (i = 0; i < chip->num_leds; i++) {
+drivers/leds/leds-an30259a.c:		an30259a_init_default_state(&chip->leds[i]);
+drivers/leds/leds-an30259a.c:		chip->leds[i].cdev.brightness_set_blocking =
+drivers/leds/leds-an30259a.c:		chip->leds[i].cdev.blink_set = an30259a_blink_set;
+drivers/leds/leds-an30259a.c:		init_data.fwnode = chip->leds[i].fwnode;
+drivers/leds/leds-an30259a.c:						 &chip->leds[i].cdev,
+drivers/leds/leds-an30259a.c:	mutex_destroy(&chip->mutex);
+drivers/leds/leds-an30259a.c:	mutex_destroy(&chip->mutex);
+drivers/leds/leds-is31fl32xx.c: * struct is31fl32xx_chipdef - chip-specific attributes
+drivers/leds/leds-lm355x.c:	struct lm355x_platform_data *pdata = chip->pdata;
+drivers/leds/leds-lm355x.c:	switch (chip->type) {
+drivers/leds/leds-lm355x.c:		ret = regmap_update_bits(chip->regmap, 0xE0, 0x28, reg_val);
+drivers/leds/leds-lm355x.c:		ret = regmap_update_bits(chip->regmap, 0xA0, 0x04, reg_val);
+drivers/leds/leds-lm355x.c:		ret = regmap_update_bits(chip->regmap, 0x0A, 0xC4, reg_val);
+drivers/leds/leds-lm355x.c:	dev_err(chip->dev, "%s:i2c access fail to register\n", __func__);
+drivers/leds/leds-lm355x.c:	struct lm355x_platform_data *pdata = chip->pdata;
+drivers/leds/leds-lm355x.c:	struct lm355x_reg_data *preg = chip->regs;
+drivers/leds/leds-lm355x.c:	ret = regmap_read(chip->regmap, preg[REG_FLAG].regno, &chip->last_flag);
+drivers/leds/leds-lm355x.c:	if (chip->last_flag & preg[REG_FLAG].mask)
+drivers/leds/leds-lm355x.c:		dev_info(chip->dev, "%s Last FLAG is 0x%x\n",
+drivers/leds/leds-lm355x.c:			 lm355x_name[chip->type],
+drivers/leds/leds-lm355x.c:			 chip->last_flag & preg[REG_FLAG].mask);
+drivers/leds/leds-lm355x.c:		    regmap_update_bits(chip->regmap, preg[REG_TORCH_CTRL].regno,
+drivers/leds/leds-lm355x.c:			    regmap_update_bits(chip->regmap,
+drivers/leds/leds-lm355x.c:			dev_info(chip->dev,
+drivers/leds/leds-lm355x.c:		    regmap_update_bits(chip->regmap, preg[REG_FLASH_CTRL].regno,
+drivers/leds/leds-lm355x.c:			if (chip->type == CHIP_LM3554)
+drivers/leds/leds-lm355x.c:			    regmap_update_bits(chip->regmap,
+drivers/leds/leds-lm355x.c:			dev_info(chip->dev,
+drivers/leds/leds-lm355x.c:		    regmap_update_bits(chip->regmap, preg[REG_INDI_CTRL].regno,
+drivers/leds/leds-lm355x.c:			    regmap_update_bits(chip->regmap,
+drivers/leds/leds-lm355x.c:	ret = regmap_update_bits(chip->regmap, preg[REG_OPMODE].regno,
+drivers/leds/leds-lm355x.c:	dev_err(chip->dev, "%s:i2c access fail to register\n", __func__);
+drivers/leds/leds-lm355x.c:	mutex_lock(&chip->lock);
+drivers/leds/leds-lm355x.c:	mutex_unlock(&chip->lock);
+drivers/leds/leds-lm355x.c:	mutex_lock(&chip->lock);
+drivers/leds/leds-lm355x.c:	mutex_unlock(&chip->lock);
+drivers/leds/leds-lm355x.c:	mutex_lock(&chip->lock);
+drivers/leds/leds-lm355x.c:	mutex_unlock(&chip->lock);
+drivers/leds/leds-lm355x.c:	ret = regmap_write(chip->regmap, 0x04,
+drivers/leds/leds-lm355x.c:	ret = regmap_write(chip->regmap, 0x05,
+drivers/leds/leds-lm355x.c:	dev_err(chip->dev, "%s:i2c access fail to register\n", __func__);
+drivers/leds/leds-lm355x.c:	chip->dev = &client->dev;
+drivers/leds/leds-lm355x.c:	chip->type = id->driver_data;
+drivers/leds/leds-lm355x.c:		chip->regs = lm3554_regs;
+drivers/leds/leds-lm355x.c:		chip->regs = lm3556_regs;
+drivers/leds/leds-lm355x.c:	chip->pdata = pdata;
+drivers/leds/leds-lm355x.c:	chip->regmap = devm_regmap_init_i2c(client, &lm355x_regmap);
+drivers/leds/leds-lm355x.c:	if (IS_ERR(chip->regmap)) {
+drivers/leds/leds-lm355x.c:		err = PTR_ERR(chip->regmap);
+drivers/leds/leds-lm355x.c:	mutex_init(&chip->lock);
+drivers/leds/leds-lm355x.c:	chip->cdev_flash.name = "flash";
+drivers/leds/leds-lm355x.c:	chip->cdev_flash.max_brightness = 16;
+drivers/leds/leds-lm355x.c:	chip->cdev_flash.brightness_set_blocking = lm355x_strobe_brightness_set;
+drivers/leds/leds-lm355x.c:	chip->cdev_flash.default_trigger = "flash";
+drivers/leds/leds-lm355x.c:				    &client->dev, &chip->cdev_flash);
+drivers/leds/leds-lm355x.c:	chip->cdev_torch.name = "torch";
+drivers/leds/leds-lm355x.c:	chip->cdev_torch.max_brightness = 8;
+drivers/leds/leds-lm355x.c:	chip->cdev_torch.brightness_set_blocking = lm355x_torch_brightness_set;
+drivers/leds/leds-lm355x.c:	chip->cdev_torch.default_trigger = "torch";
+drivers/leds/leds-lm355x.c:				    &client->dev, &chip->cdev_torch);
+drivers/leds/leds-lm355x.c:	chip->cdev_indicator.name = "indicator";
+drivers/leds/leds-lm355x.c:		chip->cdev_indicator.max_brightness = 4;
+drivers/leds/leds-lm355x.c:		chip->cdev_indicator.max_brightness = 8;
+drivers/leds/leds-lm355x.c:	chip->cdev_indicator.brightness_set_blocking =
+drivers/leds/leds-lm355x.c:		chip->cdev_indicator.groups = lm355x_indicator_groups;
+drivers/leds/leds-lm355x.c:				    &client->dev, &chip->cdev_indicator);
+drivers/leds/leds-lm355x.c:	led_classdev_unregister(&chip->cdev_torch);
+drivers/leds/leds-lm355x.c:	led_classdev_unregister(&chip->cdev_flash);
+drivers/leds/leds-lm355x.c:	struct lm355x_reg_data *preg = chip->regs;
+drivers/leds/leds-lm355x.c:	regmap_write(chip->regmap, preg[REG_OPMODE].regno, 0);
+drivers/leds/leds-lm355x.c:	led_classdev_unregister(&chip->cdev_indicator);
+drivers/leds/leds-lm355x.c:	led_classdev_unregister(&chip->cdev_torch);
+drivers/leds/leds-lm355x.c:	led_classdev_unregister(&chip->cdev_flash);
+drivers/leds/leds-lm355x.c:	dev_info(&client->dev, "%s is removed\n", lm355x_name[chip->type]);
+drivers/leds/leds-lm3642.c:	struct lm3642_platform_data *pdata = chip->pdata;
+drivers/leds/leds-lm3642.c:	ret = regmap_update_bits(chip->regmap, REG_ENABLE, EX_PIN_ENABLE_MASK,
+drivers/leds/leds-lm3642.c:		dev_err(chip->dev, "Failed to update REG_ENABLE Register\n");
+drivers/leds/leds-lm3642.c:	ret = regmap_read(chip->regmap, REG_FLAG, &chip->last_flag);
+drivers/leds/leds-lm3642.c:		dev_err(chip->dev, "Failed to read REG_FLAG Register\n");
+drivers/leds/leds-lm3642.c:	if (chip->last_flag)
+drivers/leds/leds-lm3642.c:		dev_info(chip->dev, "Last FLAG is 0x%x\n", chip->last_flag);
+drivers/leds/leds-lm3642.c:		ret = regmap_update_bits(chip->regmap, REG_I_CTRL,
+drivers/leds/leds-lm3642.c:		if (chip->torch_pin)
+drivers/leds/leds-lm3642.c:		ret = regmap_update_bits(chip->regmap, REG_I_CTRL,
+drivers/leds/leds-lm3642.c:		if (chip->strobe_pin)
+drivers/leds/leds-lm3642.c:		ret = regmap_update_bits(chip->regmap, REG_I_CTRL,
+drivers/leds/leds-lm3642.c:		dev_err(chip->dev, "Failed to write REG_I_CTRL Register\n");
+drivers/leds/leds-lm3642.c:	if (chip->tx_pin)
+drivers/leds/leds-lm3642.c:	ret = regmap_update_bits(chip->regmap, REG_ENABLE,
+drivers/leds/leds-lm3642.c:	chip->torch_pin = state;
+drivers/leds/leds-lm3642.c:	ret = regmap_update_bits(chip->regmap, REG_ENABLE,
+drivers/leds/leds-lm3642.c:	dev_err(chip->dev, "%s:i2c access fail to register\n", __func__);
+drivers/leds/leds-lm3642.c:	dev_err(chip->dev, "%s: fail to change str to int\n", __func__);
+drivers/leds/leds-lm3642.c:	mutex_lock(&chip->lock);
+drivers/leds/leds-lm3642.c:	chip->br_torch = brightness;
+drivers/leds/leds-lm3642.c:	ret = lm3642_control(chip, chip->br_torch, MODES_TORCH);
+drivers/leds/leds-lm3642.c:	mutex_unlock(&chip->lock);
+drivers/leds/leds-lm3642.c:	chip->strobe_pin = state;
+drivers/leds/leds-lm3642.c:	ret = regmap_update_bits(chip->regmap, REG_ENABLE,
+drivers/leds/leds-lm3642.c:	dev_err(chip->dev, "%s:i2c access fail to register\n", __func__);
+drivers/leds/leds-lm3642.c:	dev_err(chip->dev, "%s: fail to change str to int\n", __func__);
+drivers/leds/leds-lm3642.c:	mutex_lock(&chip->lock);
+drivers/leds/leds-lm3642.c:	chip->br_flash = brightness;
+drivers/leds/leds-lm3642.c:	ret = lm3642_control(chip, chip->br_flash, MODES_FLASH);
+drivers/leds/leds-lm3642.c:	mutex_unlock(&chip->lock);
+drivers/leds/leds-lm3642.c:	mutex_lock(&chip->lock);
+drivers/leds/leds-lm3642.c:	chip->br_indicator = brightness;
+drivers/leds/leds-lm3642.c:	ret = lm3642_control(chip, chip->br_indicator, MODES_INDIC);
+drivers/leds/leds-lm3642.c:	mutex_unlock(&chip->lock);
+drivers/leds/leds-lm3642.c:	chip->dev = &client->dev;
+drivers/leds/leds-lm3642.c:	chip->pdata = pdata;
+drivers/leds/leds-lm3642.c:	chip->tx_pin = pdata->tx_pin;
+drivers/leds/leds-lm3642.c:	chip->torch_pin = pdata->torch_pin;
+drivers/leds/leds-lm3642.c:	chip->strobe_pin = pdata->strobe_pin;
+drivers/leds/leds-lm3642.c:	chip->regmap = devm_regmap_init_i2c(client, &lm3642_regmap);
+drivers/leds/leds-lm3642.c:	if (IS_ERR(chip->regmap)) {
+drivers/leds/leds-lm3642.c:		err = PTR_ERR(chip->regmap);
+drivers/leds/leds-lm3642.c:	mutex_init(&chip->lock);
+drivers/leds/leds-lm3642.c:	chip->cdev_flash.name = "flash";
+drivers/leds/leds-lm3642.c:	chip->cdev_flash.max_brightness = 16;
+drivers/leds/leds-lm3642.c:	chip->cdev_flash.brightness_set_blocking = lm3642_strobe_brightness_set;
+drivers/leds/leds-lm3642.c:	chip->cdev_flash.default_trigger = "flash";
+drivers/leds/leds-lm3642.c:	chip->cdev_flash.groups = lm3642_flash_groups,
+drivers/leds/leds-lm3642.c:				    &client->dev, &chip->cdev_flash);
+drivers/leds/leds-lm3642.c:		dev_err(chip->dev, "failed to register flash\n");
+drivers/leds/leds-lm3642.c:	chip->cdev_torch.name = "torch";
+drivers/leds/leds-lm3642.c:	chip->cdev_torch.max_brightness = 8;
+drivers/leds/leds-lm3642.c:	chip->cdev_torch.brightness_set_blocking = lm3642_torch_brightness_set;
+drivers/leds/leds-lm3642.c:	chip->cdev_torch.default_trigger = "torch";
+drivers/leds/leds-lm3642.c:	chip->cdev_torch.groups = lm3642_torch_groups,
+drivers/leds/leds-lm3642.c:				    &client->dev, &chip->cdev_torch);
+drivers/leds/leds-lm3642.c:		dev_err(chip->dev, "failed to register torch\n");
+drivers/leds/leds-lm3642.c:	chip->cdev_indicator.name = "indicator";
+drivers/leds/leds-lm3642.c:	chip->cdev_indicator.max_brightness = 8;
+drivers/leds/leds-lm3642.c:	chip->cdev_indicator.brightness_set_blocking =
+drivers/leds/leds-lm3642.c:				    &client->dev, &chip->cdev_indicator);
+drivers/leds/leds-lm3642.c:		dev_err(chip->dev, "failed to register indicator\n");
+drivers/leds/leds-lm3642.c:	led_classdev_unregister(&chip->cdev_torch);
+drivers/leds/leds-lm3642.c:	led_classdev_unregister(&chip->cdev_flash);
+drivers/leds/leds-lm3642.c:	led_classdev_unregister(&chip->cdev_indicator);
+drivers/leds/leds-lm3642.c:	led_classdev_unregister(&chip->cdev_torch);
+drivers/leds/leds-lm3642.c:	led_classdev_unregister(&chip->cdev_flash);
+drivers/leds/leds-lm3642.c:	regmap_write(chip->regmap, REG_ENABLE, 0);
+drivers/leds/leds-lp5521.c:	enum lp55xx_engine_index idx = chip->engine_idx;
+drivers/leds/leds-lp5521.c:	enum lp55xx_engine_index idx = chip->engine_idx;
+drivers/leds/leds-lp5521.c:	enum lp55xx_engine_index idx = chip->engine_idx;
+drivers/leds/leds-lp5521.c:	dev_err(&chip->cl->dev, "wrong pattern format\n");
+drivers/leds/leds-lp5521.c:	const struct firmware *fw = chip->fw;
+drivers/leds/leds-lp5521.c:		dev_err(&chip->cl->dev, "firmware data size overflow: %zu\n",
+drivers/leds/leds-lp5521.c:		dev_err(&chip->cl->dev, "error in resetting chip\n");
+drivers/leds/leds-lp5521.c:		dev_err(&chip->cl->dev,
+drivers/leds/leds-lp5521.c:	struct lp55xx_platform_data *pdata = chip->pdata;
+drivers/leds/leds-lp5521.c:	mutex_lock(&chip->lock);
+drivers/leds/leds-lp5521.c:	mutex_unlock(&chip->lock);
+drivers/leds/leds-lp5521.c:	enum lp55xx_engine_mode mode = chip->engines[nr - 1].mode;
+drivers/leds/leds-lp5521.c:	struct lp55xx_engine *engine = &chip->engines[nr - 1];
+drivers/leds/leds-lp5521.c:	mutex_lock(&chip->lock);
+drivers/leds/leds-lp5521.c:	chip->engine_idx = nr;
+drivers/leds/leds-lp5521.c:	mutex_unlock(&chip->lock);
+drivers/leds/leds-lp5521.c:	mutex_lock(&chip->lock);
+drivers/leds/leds-lp5521.c:	chip->engine_idx = nr;
+drivers/leds/leds-lp5521.c:	mutex_unlock(&chip->lock);
+drivers/leds/leds-lp5521.c:	mutex_lock(&chip->lock);
+drivers/leds/leds-lp5521.c:	mutex_unlock(&chip->lock);
+drivers/leds/leds-lp5521.c:	chip->cl = client;
+drivers/leds/leds-lp5521.c:	chip->pdata = pdata;
+drivers/leds/leds-lp5521.c:	chip->cfg = &lp5521_cfg;
+drivers/leds/leds-lp5521.c:	mutex_init(&chip->lock);
+drivers/leds/leds-lp5523.c:	enum lp55xx_engine_index idx = chip->engine_idx;
+drivers/leds/leds-lp5523.c:	enum lp55xx_engine_index idx = chip->engine_idx;
+drivers/leds/leds-lp5523.c:	enum lp55xx_engine_index idx = chip->engine_idx;
+drivers/leds/leds-lp5523.c:		chip->engine_idx = i;
+drivers/leds/leds-lp5523.c:		dev_err(&chip->cl->dev,
+drivers/leds/leds-lp5523.c:	dev_err(&chip->cl->dev, "wrong pattern format\n");
+drivers/leds/leds-lp5523.c:	const struct firmware *fw = chip->fw;
+drivers/leds/leds-lp5523.c:		dev_err(&chip->cl->dev, "firmware data size overflow: %zu\n",
+drivers/leds/leds-lp5523.c:	enum lp55xx_engine_mode mode = chip->engines[nr - 1].mode;
+drivers/leds/leds-lp5523.c:	struct lp55xx_engine *engine = &chip->engines[nr - 1];
+drivers/leds/leds-lp5523.c:	mutex_lock(&chip->lock);
+drivers/leds/leds-lp5523.c:	chip->engine_idx = nr;
+drivers/leds/leds-lp5523.c:	mutex_unlock(&chip->lock);
+drivers/leds/leds-lp5523.c:	lp5523_mux_to_array(chip->engines[nr - 1].led_mux, mux);
+drivers/leds/leds-lp5523.c:	struct lp55xx_engine *engine = &chip->engines[nr - 1];
+drivers/leds/leds-lp5523.c:	struct lp55xx_engine *engine = &chip->engines[nr - 1];
+drivers/leds/leds-lp5523.c:	mutex_lock(&chip->lock);
+drivers/leds/leds-lp5523.c:	chip->engine_idx = nr;
+drivers/leds/leds-lp5523.c:	mutex_unlock(&chip->lock);
+drivers/leds/leds-lp5523.c:	mutex_lock(&chip->lock);
+drivers/leds/leds-lp5523.c:	chip->engine_idx = nr;
+drivers/leds/leds-lp5523.c:	mutex_unlock(&chip->lock);
+drivers/leds/leds-lp5523.c:	struct lp55xx_platform_data *pdata = chip->pdata;
+drivers/leds/leds-lp5523.c:	mutex_lock(&chip->lock);
+drivers/leds/leds-lp5523.c:	mutex_unlock(&chip->lock);
+drivers/leds/leds-lp5523.c:	mutex_lock(&chip->lock);
+drivers/leds/leds-lp5523.c:	mutex_unlock(&chip->lock);
+drivers/leds/leds-lp5523.c:	mutex_lock(&chip->lock);
+drivers/leds/leds-lp5523.c:	mutex_unlock(&chip->lock);
+drivers/leds/leds-lp5523.c:	mutex_lock(&chip->lock);
+drivers/leds/leds-lp5523.c:	mutex_unlock(&chip->lock);
+drivers/leds/leds-lp5523.c:	mutex_lock(&chip->lock);
+drivers/leds/leds-lp5523.c:	mutex_unlock(&chip->lock);
+drivers/leds/leds-lp5523.c:	mutex_lock(&chip->lock);
+drivers/leds/leds-lp5523.c:	mutex_unlock(&chip->lock);
+drivers/leds/leds-lp5523.c:	chip->cl = client;
+drivers/leds/leds-lp5523.c:	chip->pdata = pdata;
+drivers/leds/leds-lp5523.c:	chip->cfg = &lp5523_cfg;
+drivers/leds/leds-lp5523.c:	mutex_init(&chip->lock);
+drivers/leds/leds-lp5562.c:	enum lp55xx_engine_index idx = chip->engine_idx;
+drivers/leds/leds-lp5562.c:	enum lp55xx_engine_index idx = chip->engine_idx;
+drivers/leds/leds-lp5562.c:	dev_err(&chip->cl->dev, "wrong pattern format\n");
+drivers/leds/leds-lp5562.c:	const struct firmware *fw = chip->fw;
+drivers/leds/leds-lp5562.c:		dev_err(&chip->cl->dev, "firmware data size overflow: %zu\n",
+drivers/leds/leds-lp5562.c:	mutex_lock(&chip->lock);
+drivers/leds/leds-lp5562.c:	mutex_unlock(&chip->lock);
+drivers/leds/leds-lp5562.c:	ptn = chip->pdata->patterns + (mode - 1);
+drivers/leds/leds-lp5562.c:		dev_err(&chip->cl->dev, "invalid pattern data\n");
+drivers/leds/leds-lp5562.c:		chip->engine_idx = i;
+drivers/leds/leds-lp5562.c:	struct lp55xx_predef_pattern *ptn = chip->pdata->patterns;
+drivers/leds/leds-lp5562.c:	int num_patterns = chip->pdata->num_patterns;
+drivers/leds/leds-lp5562.c:	mutex_lock(&chip->lock);
+drivers/leds/leds-lp5562.c:	mutex_unlock(&chip->lock);
+drivers/leds/leds-lp5562.c:		enum lp55xx_engine_index idx = chip->engine_idx;
+drivers/leds/leds-lp5562.c:	mutex_lock(&chip->lock);
+drivers/leds/leds-lp5562.c:	mutex_unlock(&chip->lock);
+drivers/leds/leds-lp5562.c:	chip->cl = client;
+drivers/leds/leds-lp5562.c:	chip->pdata = pdata;
+drivers/leds/leds-lp5562.c:	chip->cfg = &lp5562_cfg;
+drivers/leds/leds-lp5562.c:	mutex_init(&chip->lock);
+drivers/leds/leds-lp55xx-common.c:	struct lp55xx_device_config *cfg = chip->cfg;
+drivers/leds/leds-lp55xx-common.c:	struct lp55xx_device_config *cfg = chip->cfg;
+drivers/leds/leds-lp55xx-common.c:	struct lp55xx_device_config *cfg = chip->cfg;
+drivers/leds/leds-lp55xx-common.c:	if (!chip->cfg->set_led_current)
+drivers/leds/leds-lp55xx-common.c:	mutex_lock(&chip->lock);
+drivers/leds/leds-lp55xx-common.c:	chip->cfg->set_led_current(led, (u8)curr);
+drivers/leds/leds-lp55xx-common.c:	mutex_unlock(&chip->lock);
+drivers/leds/leds-lp55xx-common.c:	struct lp55xx_device_config *cfg = led->chip->cfg;
+drivers/leds/leds-lp55xx-common.c:	struct lp55xx_platform_data *pdata = chip->pdata;
+drivers/leds/leds-lp55xx-common.c:	struct lp55xx_device_config *cfg = chip->cfg;
+drivers/leds/leds-lp55xx-common.c:	struct device *dev = &chip->cl->dev;
+drivers/leds/leds-lp55xx-common.c:			pdata->label ? : chip->cl->name, chan);
+drivers/leds/leds-lp55xx-common.c:	struct device *dev = &chip->cl->dev;
+drivers/leds/leds-lp55xx-common.c:	enum lp55xx_engine_index idx = chip->engine_idx;
+drivers/leds/leds-lp55xx-common.c:	mutex_lock(&chip->lock);
+drivers/leds/leds-lp55xx-common.c:	chip->engines[idx - 1].mode = LP55XX_ENGINE_LOAD;
+drivers/leds/leds-lp55xx-common.c:	chip->fw = fw;
+drivers/leds/leds-lp55xx-common.c:	if (chip->cfg->firmware_cb)
+drivers/leds/leds-lp55xx-common.c:		chip->cfg->firmware_cb(chip);
+drivers/leds/leds-lp55xx-common.c:	mutex_unlock(&chip->lock);
+drivers/leds/leds-lp55xx-common.c:	release_firmware(chip->fw);
+drivers/leds/leds-lp55xx-common.c:	chip->fw = NULL;
+drivers/leds/leds-lp55xx-common.c:	const char *name = chip->cl->name;
+drivers/leds/leds-lp55xx-common.c:	struct device *dev = &chip->cl->dev;
+drivers/leds/leds-lp55xx-common.c:	return sprintf(buf, "%d\n", chip->engine_idx);
+drivers/leds/leds-lp55xx-common.c:		mutex_lock(&chip->lock);
+drivers/leds/leds-lp55xx-common.c:		chip->engine_idx = val;
+drivers/leds/leds-lp55xx-common.c:		mutex_unlock(&chip->lock);
+drivers/leds/leds-lp55xx-common.c:	if (chip->cfg->run_engine)
+drivers/leds/leds-lp55xx-common.c:		chip->cfg->run_engine(chip, start);
+drivers/leds/leds-lp55xx-common.c:	mutex_lock(&chip->lock);
+drivers/leds/leds-lp55xx-common.c:	mutex_unlock(&chip->lock);
+drivers/leds/leds-lp55xx-common.c:	return i2c_smbus_write_byte_data(chip->cl, reg, val);
+drivers/leds/leds-lp55xx-common.c:	ret = i2c_smbus_read_byte_data(chip->cl, reg);
+drivers/leds/leds-lp55xx-common.c:	clk = devm_clk_get(&chip->cl->dev, "32k_clk");
+drivers/leds/leds-lp55xx-common.c:	dev_info(&chip->cl->dev, "%dHz external clock used\n",	LP55XX_CLK_32K);
+drivers/leds/leds-lp55xx-common.c:	chip->clk = clk;
+drivers/leds/leds-lp55xx-common.c:	dev_info(&chip->cl->dev, "internal clock used\n");
+drivers/leds/leds-lp55xx-common.c:	struct device *dev = &chip->cl->dev;
+drivers/leds/leds-lp55xx-common.c:	pdata = chip->pdata;
+drivers/leds/leds-lp55xx-common.c:	cfg = chip->cfg;
+drivers/leds/leds-lp55xx-common.c:	struct lp55xx_platform_data *pdata = chip->pdata;
+drivers/leds/leds-lp55xx-common.c:	if (chip->clk)
+drivers/leds/leds-lp55xx-common.c:		clk_disable_unprepare(chip->clk);
+drivers/leds/leds-lp55xx-common.c:	struct lp55xx_platform_data *pdata = chip->pdata;
+drivers/leds/leds-lp55xx-common.c:	struct lp55xx_device_config *cfg = chip->cfg;
+drivers/leds/leds-lp55xx-common.c:		dev_err(&chip->cl->dev, "empty brightness configuration\n");
+drivers/leds/leds-lp55xx-common.c:		chip->num_leds++;
+drivers/leds/leds-lp55xx-common.c:	for (i = 0; i < chip->num_leds; i++) {
+drivers/leds/leds-lp55xx-common.c:	struct device *dev = &chip->cl->dev;
+drivers/leds/leds-lp55xx-common.c:	struct lp55xx_device_config *cfg = chip->cfg;
+drivers/leds/leds-lp55xx-common.c:	struct device *dev = &chip->cl->dev;
+drivers/leds/leds-lp55xx-common.c:	struct lp55xx_device_config *cfg = chip->cfg;
+drivers/leds/leds-lp8501.c:	if (chip->pdata->clock_mode != LP55XX_CLOCK_EXT)
+drivers/leds/leds-lp8501.c:				LP8501_PWR_CONFIG_M, chip->pdata->pwr_sel);
+drivers/leds/leds-lp8501.c:	enum lp55xx_engine_index idx = chip->engine_idx;
+drivers/leds/leds-lp8501.c:	dev_err(&chip->cl->dev, "wrong pattern format\n");
+drivers/leds/leds-lp8501.c:	const struct firmware *fw = chip->fw;
+drivers/leds/leds-lp8501.c:		dev_err(&chip->cl->dev, "firmware data size overflow: %zu\n",
+drivers/leds/leds-lp8501.c:	mutex_lock(&chip->lock);
+drivers/leds/leds-lp8501.c:	mutex_unlock(&chip->lock);
+drivers/leds/leds-lp8501.c:	chip->cl = client;
+drivers/leds/leds-lp8501.c:	chip->pdata = pdata;
+drivers/leds/leds-lp8501.c:	chip->cfg = &lp8501_cfg;
+drivers/leds/leds-lp8501.c:	mutex_init(&chip->lock);
+drivers/leds/leds-pca955x.c:	if (!count || count > chip->bits)
+drivers/leds/leds-pca955x.c:				   chip->bits, sizeof(struct pca955x_led),
+drivers/leds/leds-pca955x.c:		if ((res != 0) || (reg >= chip->bits))
+drivers/leds/leds-pca955x.c:	pdata->num_leds = chip->bits;
+drivers/leds/leds-pca955x.c:	if ((client->addr & ~((1 << chip->slv_addr_shift) - 1)) !=
+drivers/leds/leds-pca955x.c:	    chip->slv_addr) {
+drivers/leds/leds-pca955x.c:			client->name, chip->bits, client->addr);
+drivers/leds/leds-pca955x.c:	if (pdata->num_leds != chip->bits) {
+drivers/leds/leds-pca955x.c:			pdata->num_leds, chip->bits);
+drivers/leds/leds-pca955x.c:			chip->bits, sizeof(*pca955x_led), GFP_KERNEL);
+drivers/leds/leds-pca955x.c:	for (i = 0; i < chip->bits; i++) {
+drivers/leds/leds-pca963x.c:	u8 ledout_addr = pca963x->chip->chipdef->ledout_base
+drivers/leds/leds-pca963x.c:	ledout = i2c_smbus_read_byte_data(pca963x->chip->client, ledout_addr);
+drivers/leds/leds-pca963x.c:		ret = i2c_smbus_write_byte_data(pca963x->chip->client,
+drivers/leds/leds-pca963x.c:		ret = i2c_smbus_write_byte_data(pca963x->chip->client,
+drivers/leds/leds-pca963x.c:		ret = i2c_smbus_write_byte_data(pca963x->chip->client,
+drivers/leds/leds-pca963x.c:		ret = i2c_smbus_write_byte_data(pca963x->chip->client,
+drivers/leds/leds-pca963x.c:	u8 ledout_addr = pca963x->chip->chipdef->ledout_base +
+drivers/leds/leds-pca963x.c:	u8 mode2 = i2c_smbus_read_byte_data(pca963x->chip->client,
+drivers/leds/leds-pca963x.c:	i2c_smbus_write_byte_data(pca963x->chip->client,
+drivers/leds/leds-pca963x.c:			pca963x->chip->chipdef->grppwm,	pca963x->gdc);
+drivers/leds/leds-pca963x.c:	i2c_smbus_write_byte_data(pca963x->chip->client,
+drivers/leds/leds-pca963x.c:			pca963x->chip->chipdef->grpfreq, pca963x->gfrq);
+drivers/leds/leds-pca963x.c:		i2c_smbus_write_byte_data(pca963x->chip->client, PCA963X_MODE2,
+drivers/leds/leds-pca963x.c:	mutex_lock(&pca963x->chip->mutex);
+drivers/leds/leds-pca963x.c:	ledout = i2c_smbus_read_byte_data(pca963x->chip->client, ledout_addr);
+drivers/leds/leds-pca963x.c:		i2c_smbus_write_byte_data(pca963x->chip->client, ledout_addr,
+drivers/leds/leds-pca963x.c:	mutex_unlock(&pca963x->chip->mutex);
+drivers/leds/leds-pca963x.c:	unsigned long *leds_on = &pca963x->chip->leds_on;
+drivers/leds/leds-pca963x.c:	unsigned long cached_leds = pca963x->chip->leds_on;
+drivers/leds/leds-pca963x.c:		return i2c_smbus_write_byte_data(pca963x->chip->client,
+drivers/leds/leds-pca963x.c:	mutex_lock(&pca963x->chip->mutex);
+drivers/leds/leds-pca963x.c:	mutex_unlock(&pca963x->chip->mutex);
+drivers/leds/leds-pca963x.c:	unsigned int scaling = pca963x->chip->chipdef->scaling;
+drivers/leds/leds-pca963x.c:	if (!count || count > chip->n_leds)
+drivers/leds/leds-pca963x.c:			chip->n_leds, sizeof(struct led_info), GFP_KERNEL);
+drivers/leds/leds-pca963x.c:		if ((res != 0) || (reg >= chip->n_leds))
+drivers/leds/leds-pca963x.c:	pdata->leds.num_leds = chip->n_leds;
+drivers/leds/leds-pca963x.c:				     &chip->scaling))
+drivers/leds/leds-pca963x.c:		chip->scaling = 1000;
+drivers/leds/leds-pca963x.c:				 pdata->leds.num_leds > chip->n_leds)) {
+drivers/leds/leds-pca963x.c:								chip->n_leds);
+drivers/leds/leds-pca963x.c:	pca963x = devm_kcalloc(&client->dev, chip->n_leds, sizeof(*pca963x),
+drivers/leds/leds-pca963x.c:	mutex_init(&pca963x_chip->mutex);
+drivers/leds/leds-pca963x.c:	pca963x_chip->chipdef = chip;
+drivers/leds/leds-pca963x.c:	pca963x_chip->client = client;
+drivers/leds/leds-pca963x.c:	pca963x_chip->leds = pca963x;
+drivers/leds/leds-pca963x.c:	for (i = 0; i < chip->n_leds / 4; i++)
+drivers/leds/leds-pca963x.c:		i2c_smbus_write_byte_data(client, chip->ledout_base + i, 0x00);
+drivers/leds/leds-pca963x.c:	for (i = 0; i < chip->n_leds; i++) {
+drivers/leds/leds-pca963x.c:		u8 mode2 = i2c_smbus_read_byte_data(pca963x->chip->client,
+drivers/leds/leds-pca963x.c:		i2c_smbus_write_byte_data(pca963x->chip->client, PCA963X_MODE2,
+drivers/macintosh/macio_asic.c:	if (dev->bus->chip->type != macio_gatwick)
+drivers/macintosh/macio_asic.c:	dev->bus = &chip->lbus;
+drivers/macintosh/macio_asic.c:	dev->ofdev.dev.archdata = chip->lbus.pdev->dev.archdata;
+drivers/macintosh/macio_asic.c:	dev->ofdev.dev.dma_ops = chip->lbus.pdev->dev.dma_ops;
+drivers/macintosh/macio_asic.c:	if (np == chip->of_node) {
+drivers/macintosh/macio_asic.c:			     chip->lbus.index,
+drivers/macintosh/macio_asic.c:			(unsigned int)pci_resource_start(chip->lbus.pdev, 0),
+drivers/macintosh/macio_asic.c:			     chip->lbus.index,
+drivers/macintosh/macio_asic.c:	if (chip->lbus.pdev) {
+drivers/macintosh/macio_asic.c:		parent = &chip->lbus.pdev->dev;
+drivers/macintosh/macio_asic.c:		root_res = &chip->lbus.pdev->resource[0];
+drivers/macintosh/macio_asic.c:	pnode = of_node_get(chip->of_node);
+drivers/macintosh/macio_asic.c:	if (chip->lbus.pdev == NULL) {
+drivers/macintosh/macio_asic.c:		chip->lbus.pdev = pdev;
+drivers/macintosh/macio_asic.c:		chip->lbus.chip = chip;
+drivers/macintosh/macio_asic.c:		pci_set_drvdata(pdev, &chip->lbus);
+drivers/macintosh/macio_asic.c:		chip->name);
+drivers/macintosh/macio_asic.c:	if (chip->type == macio_gatwick || chip->type == macio_ohareII)
+drivers/mailbox/Makefile:obj-$(CONFIG_ROCKCHIP_MBOX)	+= rockchip-mailbox.o
+drivers/mailbox/rockchip-mailbox.c:		.name = "rockchip-mailbox",
+drivers/media/common/b2c2/flexcop.h: * flexcop.h - private header file for all flexcop-chip-source files
+drivers/media/common/saa7146/saa7146_core.c:	/* get chip-revision; this is needed to enable bug-fixes */
+drivers/media/dvb-frontends/mn88443x.c:	struct regmap *r_t = chip->regmap_t;
+drivers/media/dvb-frontends/mn88443x.c:	clk_prepare_enable(chip->mclk);
+drivers/media/dvb-frontends/mn88443x.c:	gpiod_set_value_cansleep(chip->reset_gpio, 1);
+drivers/media/dvb-frontends/mn88443x.c:	gpiod_set_value_cansleep(chip->reset_gpio, 0);
+drivers/media/dvb-frontends/mn88443x.c:	if (chip->spec->primary) {
+drivers/media/dvb-frontends/mn88443x.c:	gpiod_set_value_cansleep(chip->reset_gpio, 1);
+drivers/media/dvb-frontends/mn88443x.c:	clk_disable_unprepare(chip->mclk);
+drivers/media/dvb-frontends/mn88443x.c:	struct regmap *r_t = chip->regmap_t;
+drivers/media/dvb-frontends/mn88443x.c:	struct regmap *r_t = chip->regmap_t;
+drivers/media/dvb-frontends/mn88443x.c:	struct regmap *r_s = chip->regmap_s;
+drivers/media/dvb-frontends/mn88443x.c:	struct regmap *r_s = chip->regmap_s;
+drivers/media/dvb-frontends/mn88443x.c:	struct regmap *r_t = chip->regmap_t;
+drivers/media/dvb-frontends/mn88443x.c:	struct regmap *r_t = chip->regmap_t;
+drivers/media/dvb-frontends/mn88443x.c:	struct device *dev = &chip->client_s->dev;
+drivers/media/dvb-frontends/mn88443x.c:	struct regmap *r_t = chip->regmap_t;
+drivers/media/dvb-frontends/mn88443x.c:	if (chip->clk_freq >= CLK_LOW && chip->clk_freq < CLK_DIRECT) {
+drivers/media/dvb-frontends/mn88443x.c:		chip->use_clkbuf = true;
+drivers/media/dvb-frontends/mn88443x.c:		chip->use_clkbuf = false;
+drivers/media/dvb-frontends/mn88443x.c:		adckt = chip->clk_freq;
+drivers/media/dvb-frontends/mn88443x.c:	if (!mn88443x_t_is_valid_clk(adckt, chip->if_freq)) {
+drivers/media/dvb-frontends/mn88443x.c:			chip->clk_freq, adckt, chip->if_freq);
+drivers/media/dvb-frontends/mn88443x.c:	if (chip->if_freq == DIRECT_IF_57MHZ ||
+drivers/media/dvb-frontends/mn88443x.c:	    chip->if_freq == DIRECT_IF_44MHZ)
+drivers/media/dvb-frontends/mn88443x.c:		nco = adckt * 2 - chip->if_freq;
+drivers/media/dvb-frontends/mn88443x.c:		nco = -((s64)chip->if_freq);
+drivers/media/dvb-frontends/mn88443x.c:	struct regmap *r_t = chip->regmap_t;
+drivers/media/dvb-frontends/mn88443x.c:	struct regmap *r_t = chip->regmap_t;
+drivers/media/dvb-frontends/mn88443x.c:	struct regmap *r_s = chip->regmap_s;
+drivers/media/dvb-frontends/mn88443x.c:	struct regmap *r_t = chip->regmap_t;
+drivers/media/dvb-frontends/mn88443x.c:		chip->spec = of_device_get_match_data(dev);
+drivers/media/dvb-frontends/mn88443x.c:		chip->spec = (struct mn88443x_spec *)id->driver_data;
+drivers/media/dvb-frontends/mn88443x.c:	if (!chip->spec)
+drivers/media/dvb-frontends/mn88443x.c:	chip->mclk = devm_clk_get(dev, "mclk");
+drivers/media/dvb-frontends/mn88443x.c:	if (IS_ERR(chip->mclk) && !conf) {
+drivers/media/dvb-frontends/mn88443x.c:			PTR_ERR(chip->mclk));
+drivers/media/dvb-frontends/mn88443x.c:		return PTR_ERR(chip->mclk);
+drivers/media/dvb-frontends/mn88443x.c:				   &chip->if_freq);
+drivers/media/dvb-frontends/mn88443x.c:	chip->reset_gpio = devm_gpiod_get_optional(dev, "reset",
+drivers/media/dvb-frontends/mn88443x.c:	if (IS_ERR(chip->reset_gpio)) {
+drivers/media/dvb-frontends/mn88443x.c:			PTR_ERR(chip->reset_gpio));
+drivers/media/dvb-frontends/mn88443x.c:		return PTR_ERR(chip->reset_gpio);
+drivers/media/dvb-frontends/mn88443x.c:		chip->mclk = conf->mclk;
+drivers/media/dvb-frontends/mn88443x.c:		chip->if_freq = conf->if_freq;
+drivers/media/dvb-frontends/mn88443x.c:		chip->reset_gpio = conf->reset_gpio;
+drivers/media/dvb-frontends/mn88443x.c:		*conf->fe = &chip->fe;
+drivers/media/dvb-frontends/mn88443x.c:	chip->client_s = client;
+drivers/media/dvb-frontends/mn88443x.c:	chip->regmap_s = devm_regmap_init_i2c(chip->client_s, &regmap_config);
+drivers/media/dvb-frontends/mn88443x.c:	if (IS_ERR(chip->regmap_s))
+drivers/media/dvb-frontends/mn88443x.c:		return PTR_ERR(chip->regmap_s);
+drivers/media/dvb-frontends/mn88443x.c:	chip->client_t = i2c_new_dummy_device(client->adapter, client->addr + 4);
+drivers/media/dvb-frontends/mn88443x.c:	if (IS_ERR(chip->client_t))
+drivers/media/dvb-frontends/mn88443x.c:		return PTR_ERR(chip->client_t);
+drivers/media/dvb-frontends/mn88443x.c:	chip->regmap_t = devm_regmap_init_i2c(chip->client_t, &regmap_config);
+drivers/media/dvb-frontends/mn88443x.c:	if (IS_ERR(chip->regmap_t)) {
+drivers/media/dvb-frontends/mn88443x.c:		ret = PTR_ERR(chip->regmap_t);
+drivers/media/dvb-frontends/mn88443x.c:	chip->clk_freq = clk_get_rate(chip->mclk);
+drivers/media/dvb-frontends/mn88443x.c:	memcpy(&chip->fe.ops, &mn88443x_ops, sizeof(mn88443x_ops));
+drivers/media/dvb-frontends/mn88443x.c:	chip->fe.demodulator_priv = chip;
+drivers/media/dvb-frontends/mn88443x.c:	i2c_unregister_device(chip->client_t);
+drivers/media/dvb-frontends/mn88443x.c:	i2c_unregister_device(chip->client_t);
+drivers/media/dvb-frontends/stv0900_core.c:			((temp_chip->internal->i2c_adap != i2c_adap) ||
+drivers/media/dvb-frontends/stv0900_core.c:			(temp_chip->internal->i2c_addr != i2c_addr)))
+drivers/media/dvb-frontends/stv0900_core.c:			temp_chip = temp_chip->next_inode;
+drivers/media/i2c/mt9m111.c:	/* receiver samples on falling edge, chip-hw default is rising */
+drivers/media/i2c/tvaudio.c:	/* chip-specific description - should point to
+drivers/media/i2c/tvaudio.c:	struct v4l2_subdev *sd = &chip->sd;
+drivers/media/i2c/tvaudio.c:		chip->shadow.bytes[1] = val;
+drivers/media/i2c/tvaudio.c:		if (subaddr + 1 >= ARRAY_SIZE(chip->shadow.bytes)) {
+drivers/media/i2c/tvaudio.c:		chip->shadow.bytes[subaddr+1] = val;
+drivers/media/i2c/tvaudio.c:	struct v4l2_subdev *sd = &chip->sd;
+drivers/media/i2c/tvaudio.c:			val = (chip->shadow.bytes[1] & ~mask) | (val & mask);
+drivers/media/i2c/tvaudio.c:			if (subaddr + 1 >= ARRAY_SIZE(chip->shadow.bytes)) {
+drivers/media/i2c/tvaudio.c:			val = (chip->shadow.bytes[subaddr+1] & ~mask) | (val & mask);
+drivers/media/i2c/tvaudio.c:	struct v4l2_subdev *sd = &chip->sd;
+drivers/media/i2c/tvaudio.c:	struct v4l2_subdev *sd = &chip->sd;
+drivers/media/i2c/tvaudio.c:	struct v4l2_subdev *sd = &chip->sd;
+drivers/media/i2c/tvaudio.c:	if (cmd->count + cmd->bytes[0] - 1 >= ARRAY_SIZE(chip->shadow.bytes)) {
+drivers/media/i2c/tvaudio.c:		chip->shadow.bytes[i+cmd->bytes[0]] = cmd->bytes[i];
+drivers/media/i2c/tvaudio.c:	wake_up_process(chip->thread);
+drivers/media/i2c/tvaudio.c:	struct CHIPDESC  *desc = chip->desc;
+drivers/media/i2c/tvaudio.c:	struct v4l2_subdev *sd = &chip->sd;
+drivers/media/i2c/tvaudio.c:		if (chip->radio)
+drivers/media/i2c/tvaudio.c:		if (mode == chip->prevmode)
+drivers/media/i2c/tvaudio.c:		chip->prevmode = mode;
+drivers/media/i2c/tvaudio.c:		switch (chip->audmode) {
+drivers/media/i2c/tvaudio.c:		mod_timer(&chip->wt, jiffies+msecs_to_jiffies(2000));
+drivers/media/i2c/tvaudio.c:	struct v4l2_subdev *sd = &chip->sd;
+drivers/media/i2c/tvaudio.c:	int t = chip->shadow.bytes[TDA9840_SW + 1] & ~0x7e;
+drivers/media/i2c/tvaudio.c:	int c6 = chip->shadow.bytes[TDA985x_C6+1] & 0x3f;
+drivers/media/i2c/tvaudio.c:	struct v4l2_subdev *sd = &chip->sd;
+drivers/media/i2c/tvaudio.c:	struct v4l2_subdev *sd = &chip->sd;
+drivers/media/i2c/tvaudio.c:	int sw_data  = chip->shadow.bytes[TDA9873_SW+1] & ~ TDA9873_TR_MASK;
+drivers/media/i2c/tvaudio.c:	/*	int adj_data = chip->shadow.bytes[TDA9873_AD+1] ; */
+drivers/media/i2c/tvaudio.c:		 "tda9873_setaudmode(): chip->shadow.bytes[%d] = %d\n",
+drivers/media/i2c/tvaudio.c:		 TDA9873_SW+1, chip->shadow.bytes[TDA9873_SW+1]);
+drivers/media/i2c/tvaudio.c:	struct v4l2_subdev *sd = &chip->sd;
+drivers/media/i2c/tvaudio.c:	struct v4l2_subdev *sd = &chip->sd;
+drivers/media/i2c/tvaudio.c:	chip->shadow.bytes[MAXREGS-2] = dsr;
+drivers/media/i2c/tvaudio.c:	chip->shadow.bytes[MAXREGS-1] = nsr;
+drivers/media/i2c/tvaudio.c:	struct v4l2_subdev *sd = &chip->sd;
+drivers/media/i2c/tvaudio.c:		if(chip->shadow.bytes[MAXREGS-2] & 0x20) /* DSR.RSSF=1 */
+drivers/media/i2c/tvaudio.c:	struct v4l2_subdev *sd = &chip->sd;
+drivers/media/i2c/tvaudio.c:	struct v4l2_subdev *sd = &chip->sd;
+drivers/media/i2c/tvaudio.c:	int s1 = chip->shadow.bytes[TDA8425_S1+1] & 0xe1;
+drivers/media/i2c/tvaudio.c:	/* v4l2_dbg(1, debug, &chip->sd,
+drivers/media/i2c/tvaudio.c:	struct v4l2_subdev *sd = &chip->sd;
+drivers/media/i2c/tvaudio.c:	struct CHIPDESC *desc = chip->desc;
+drivers/media/i2c/tvaudio.c:		chip->muted = ctrl->val;
+drivers/media/i2c/tvaudio.c:		if (chip->muted)
+drivers/media/i2c/tvaudio.c:					desc->inputmap[chip->input],desc->inputmask);
+drivers/media/i2c/tvaudio.c:		volume = chip->volume->val;
+drivers/media/i2c/tvaudio.c:		balance = chip->balance->val;
+drivers/media/i2c/tvaudio.c:	chip->radio = 1;
+drivers/media/i2c/tvaudio.c:	/* del_timer(&chip->wt); */
+drivers/media/i2c/tvaudio.c:	struct CHIPDESC *desc = chip->desc;
+drivers/media/i2c/tvaudio.c:	chip->input = input;
+drivers/media/i2c/tvaudio.c:	if (chip->muted)
+drivers/media/i2c/tvaudio.c:			desc->inputmap[chip->input], desc->inputmask);
+drivers/media/i2c/tvaudio.c:	struct CHIPDESC *desc = chip->desc;
+drivers/media/i2c/tvaudio.c:	if (chip->radio)
+drivers/media/i2c/tvaudio.c:	chip->audmode = vt->audmode;
+drivers/media/i2c/tvaudio.c:	if (chip->thread)
+drivers/media/i2c/tvaudio.c:		wake_up_process(chip->thread);
+drivers/media/i2c/tvaudio.c:	struct CHIPDESC *desc = chip->desc;
+drivers/media/i2c/tvaudio.c:	if (chip->radio)
+drivers/media/i2c/tvaudio.c:	vt->audmode = chip->audmode;
+drivers/media/i2c/tvaudio.c:	chip->radio = 0;
+drivers/media/i2c/tvaudio.c:	struct CHIPDESC *desc = chip->desc;
+drivers/media/i2c/tvaudio.c:	if (chip->thread) {
+drivers/media/i2c/tvaudio.c:		chip->prevmode = -1; /* reset previous mode */
+drivers/media/i2c/tvaudio.c:		mod_timer(&chip->wt, jiffies+msecs_to_jiffies(2000));
+drivers/media/i2c/tvaudio.c:	struct CHIPDESC *desc = chip->desc;
+drivers/media/i2c/tvaudio.c:	v4l2_ctrl_handler_log_status(&chip->hdl, sd->name);
+drivers/media/i2c/tvaudio.c:	sd = &chip->sd;
+drivers/media/i2c/tvaudio.c:	chip->desc = desc;
+drivers/media/i2c/tvaudio.c:	chip->shadow.count = desc->registers+1;
+drivers/media/i2c/tvaudio.c:	chip->prevmode = -1;
+drivers/media/i2c/tvaudio.c:	chip->audmode = V4L2_TUNER_MODE_LANG1;
+drivers/media/i2c/tvaudio.c:	v4l2_ctrl_handler_init(&chip->hdl, 5);
+drivers/media/i2c/tvaudio.c:		v4l2_ctrl_new_std(&chip->hdl, &tvaudio_ctrl_ops,
+drivers/media/i2c/tvaudio.c:			chip->volume = v4l2_ctrl_new_std(&chip->hdl,
+drivers/media/i2c/tvaudio.c:			chip->balance = v4l2_ctrl_new_std(&chip->hdl,
+drivers/media/i2c/tvaudio.c:			v4l2_ctrl_cluster(2, &chip->volume);
+drivers/media/i2c/tvaudio.c:			v4l2_ctrl_new_std(&chip->hdl,
+drivers/media/i2c/tvaudio.c:			v4l2_ctrl_new_std(&chip->hdl,
+drivers/media/i2c/tvaudio.c:	sd->ctrl_handler = &chip->hdl;
+drivers/media/i2c/tvaudio.c:	if (chip->hdl.error) {
+drivers/media/i2c/tvaudio.c:		int err = chip->hdl.error;
+drivers/media/i2c/tvaudio.c:		v4l2_ctrl_handler_free(&chip->hdl);
+drivers/media/i2c/tvaudio.c:	v4l2_ctrl_handler_setup(&chip->hdl);
+drivers/media/i2c/tvaudio.c:	chip->thread = NULL;
+drivers/media/i2c/tvaudio.c:	timer_setup(&chip->wt, chip_thread_wake, 0);
+drivers/media/i2c/tvaudio.c:		chip->thread = kthread_run(chip_thread, chip, "%s",
+drivers/media/i2c/tvaudio.c:		if (IS_ERR(chip->thread)) {
+drivers/media/i2c/tvaudio.c:			chip->thread = NULL;
+drivers/media/i2c/tvaudio.c:	del_timer_sync(&chip->wt);
+drivers/media/i2c/tvaudio.c:	if (chip->thread) {
+drivers/media/i2c/tvaudio.c:		kthread_stop(chip->thread);
+drivers/media/i2c/tvaudio.c:		chip->thread = NULL;
+drivers/media/i2c/tvaudio.c:	v4l2_ctrl_handler_free(&chip->hdl);
+drivers/media/i2c/video-i2c.c:				data->chip->buffer_size);
+drivers/media/i2c/video-i2c.c:				data->chip->buffer_size);
+drivers/media/i2c/video-i2c.c:	for (n = 0; n < data->chip->num_frame_intervals - 1; n++) {
+drivers/media/i2c/video-i2c.c:				       data->chip->frame_intervals[n]))
+drivers/media/i2c/video-i2c.c:	idx = data->chip->num_frame_intervals - n - 1;
+drivers/media/i2c/video-i2c.c:	unsigned int size = data->chip->buffer_size;
+drivers/media/i2c/video-i2c.c:	unsigned int size = data->chip->buffer_size;
+drivers/media/i2c/video-i2c.c:			ret = data->chip->xfer(data, vbuf);
+drivers/media/i2c/video-i2c.c:	ret = data->chip->setup(data);
+drivers/media/i2c/video-i2c.c:	*fmt = *data->chip->format;
+drivers/media/i2c/video-i2c.c:	const struct v4l2_frmsize_discrete *size = data->chip->size;
+drivers/media/i2c/video-i2c.c:	if (fsize->pixel_format != data->chip->format->pixelformat)
+drivers/media/i2c/video-i2c.c:	const struct v4l2_frmsize_discrete *size = data->chip->size;
+drivers/media/i2c/video-i2c.c:	if (fe->index >= data->chip->num_frame_intervals)
+drivers/media/i2c/video-i2c.c:	fe->discrete = data->chip->frame_intervals[fe->index];
+drivers/media/i2c/video-i2c.c:	const struct v4l2_frmsize_discrete *size = data->chip->size;
+drivers/media/i2c/video-i2c.c:	unsigned int bpp = data->chip->bpp / 8;
+drivers/media/i2c/video-i2c.c:	pix->pixelformat = data->chip->format->pixelformat;
+drivers/media/i2c/video-i2c.c:	for (i = 0; i < data->chip->num_frame_intervals - 1; i++) {
+drivers/media/i2c/video-i2c.c:				       data->chip->frame_intervals[i]))
+drivers/media/i2c/video-i2c.c:	data->frame_interval = data->chip->frame_intervals[i];
+drivers/media/i2c/video-i2c.c:	data->regmap = regmap_init_i2c(client, data->chip->regmap_config);
+drivers/media/i2c/video-i2c.c:	data->frame_interval = data->chip->frame_intervals[0];
+drivers/media/i2c/video-i2c.c:	if (data->chip->set_power) {
+drivers/media/i2c/video-i2c.c:		ret = data->chip->set_power(data, true);
+drivers/media/i2c/video-i2c.c:	if (data->chip->hwmon_init) {
+drivers/media/i2c/video-i2c.c:		ret = data->chip->hwmon_init(data);
+drivers/media/i2c/video-i2c.c:	if (data->chip->nvmem_config) {
+drivers/media/i2c/video-i2c.c:		struct nvmem_config *config = data->chip->nvmem_config;
+drivers/media/i2c/video-i2c.c:	if (data->chip->set_power)
+drivers/media/i2c/video-i2c.c:		data->chip->set_power(data, false);
+drivers/media/i2c/video-i2c.c:	if (data->chip->set_power)
+drivers/media/i2c/video-i2c.c:		data->chip->set_power(data, false);
+drivers/media/i2c/video-i2c.c:	if (!data->chip->set_power)
+drivers/media/i2c/video-i2c.c:	return data->chip->set_power(data, false);
+drivers/media/i2c/video-i2c.c:	if (!data->chip->set_power)
+drivers/media/i2c/video-i2c.c:	return data->chip->set_power(data, true);
+drivers/media/pci/cx23885/altera-ci.c:				(temp_chip->internal->dev != dev))
+drivers/media/pci/cx23885/altera-ci.c:		temp_chip = temp_chip->next_inode;
+drivers/media/pci/cx23885/altera-ci.c:		if (temp_chip->internal != NULL) {
+drivers/media/pci/cx23885/altera-ci.c:			temp_int = temp_chip->internal;
+drivers/media/pci/cx23885/altera-ci.c:		temp_chip = temp_chip->next_inode;
+drivers/media/pci/cx23885/cx23885-alsa.c:			chip->dev->name, ##arg); \
+drivers/media/pci/cx23885/cx23885-alsa.c:	struct cx23885_audio_buffer *buf = chip->buf;
+drivers/media/pci/cx23885/cx23885-alsa.c:	struct cx23885_audio_buffer *buf = chip->buf;
+drivers/media/pci/cx23885/cx23885-alsa.c:	struct cx23885_dev *dev  = chip->dev;
+drivers/media/pci/cx23885/cx23885-alsa.c:	cx23885_sram_channel_setup(chip->dev, audio_ch, buf->bpl,
+drivers/media/pci/cx23885/cx23885-alsa.c:	atomic_set(&chip->count, 0);
+drivers/media/pci/cx23885/cx23885-alsa.c:		chip->num_periods, buf->bpl * chip->num_periods);
+drivers/media/pci/cx23885/cx23885-alsa.c:	cx_set(PCI_INT_MSK, chip->dev->pci_irqmask | PCI_MSK_AUD_INT);
+drivers/media/pci/cx23885/cx23885-alsa.c:		cx23885_sram_channel_dump(chip->dev, audio_ch);
+drivers/media/pci/cx23885/cx23885-alsa.c:	struct cx23885_dev *dev = chip->dev;
+drivers/media/pci/cx23885/cx23885-alsa.c:		cx23885_sram_channel_dump(chip->dev,
+drivers/media/pci/cx23885/cx23885-alsa.c:		atomic_set(&chip->count, cx_read(AUD_INT_A_GPCNT));
+drivers/media/pci/cx23885/cx23885-alsa.c:		snd_pcm_period_elapsed(chip->substream);
+drivers/media/pci/cx23885/cx23885-alsa.c:	BUG_ON(!chip->dma_size);
+drivers/media/pci/cx23885/cx23885-alsa.c:	cx23885_alsa_dma_free(chip->buf);
+drivers/media/pci/cx23885/cx23885-alsa.c:	risc = &chip->buf->risc;
+drivers/media/pci/cx23885/cx23885-alsa.c:	pci_free_consistent(chip->pci, risc->size, risc->cpu, risc->dma);
+drivers/media/pci/cx23885/cx23885-alsa.c:	kfree(chip->buf);
+drivers/media/pci/cx23885/cx23885-alsa.c:	chip->buf = NULL;
+drivers/media/pci/cx23885/cx23885-alsa.c:	chip->dma_size = 0;
+drivers/media/pci/cx23885/cx23885-alsa.c:	chip->substream = substream;
+drivers/media/pci/cx23885/cx23885-alsa.c:	if (chip->dev->sram_channels[AUDIO_SRAM_CHANNEL].fifo_size !=
+drivers/media/pci/cx23885/cx23885-alsa.c:		unsigned int bpl = chip->dev->
+drivers/media/pci/cx23885/cx23885-alsa.c:	chip->period_size = params_period_bytes(hw_params);
+drivers/media/pci/cx23885/cx23885-alsa.c:	chip->num_periods = params_periods(hw_params);
+drivers/media/pci/cx23885/cx23885-alsa.c:	chip->dma_size = chip->period_size * params_periods(hw_params);
+drivers/media/pci/cx23885/cx23885-alsa.c:	BUG_ON(!chip->dma_size);
+drivers/media/pci/cx23885/cx23885-alsa.c:	BUG_ON(chip->num_periods & (chip->num_periods-1));
+drivers/media/pci/cx23885/cx23885-alsa.c:	buf->bpl = chip->period_size;
+drivers/media/pci/cx23885/cx23885-alsa.c:	chip->buf = buf;
+drivers/media/pci/cx23885/cx23885-alsa.c:			(PAGE_ALIGN(chip->dma_size) >> PAGE_SHIFT));
+drivers/media/pci/cx23885/cx23885-alsa.c:	ret = cx23885_risc_databuffer(chip->pci, &buf->risc, buf->sglist,
+drivers/media/pci/cx23885/cx23885-alsa.c:				   chip->period_size, chip->num_periods, 1);
+drivers/media/pci/cx23885/cx23885-alsa.c:	substream->runtime->dma_area = chip->buf->vaddr;
+drivers/media/pci/cx23885/cx23885-alsa.c:	substream->runtime->dma_bytes = chip->dma_size;
+drivers/media/pci/cx23885/cx23885-alsa.c:	chip->buf = NULL;
+drivers/media/pci/cx23885/cx23885-alsa.c:	spin_lock(&chip->lock);
+drivers/media/pci/cx23885/cx23885-alsa.c:	spin_unlock(&chip->lock);
+drivers/media/pci/cx23885/cx23885-alsa.c:	count = atomic_read(&chip->count);
+drivers/media/pci/cx23885/cx23885-alsa.c:	err = snd_pcm_new(chip->card, name, device, 0, 1, &pcm);
+drivers/media/pci/cx23885/cx23885-alsa.c:	chip->dev = dev;
+drivers/media/pci/cx23885/cx23885-alsa.c:	chip->pci = dev->pci;
+drivers/media/pci/cx23885/cx23885-alsa.c:	chip->card = card;
+drivers/media/pci/cx23885/cx23885-alsa.c:	spin_lock_init(&chip->lock);
+drivers/media/pci/cx23885/cx23885-alsa.c:	snd_card_free(chip->card);
+drivers/media/pci/cx23885/cx23885-ioctl.c:	if (chip->match.addr > 1)
+drivers/media/pci/cx23885/cx23885-ioctl.c:	if (chip->match.addr == 1) {
+drivers/media/pci/cx23885/cx23885-ioctl.c:		strscpy(chip->name, "cx23417", sizeof(chip->name));
+drivers/media/pci/cx23885/cx23885-ioctl.c:		strscpy(chip->name, dev->v4l2_dev.name, sizeof(chip->name));
+drivers/media/pci/cx25821/cx25821-alsa.c:		pr_info("%s/1: " fmt, chip->dev->name, ##arg);	\
+drivers/media/pci/cx25821/cx25821-alsa.c:		printk(KERN_DEBUG "%s/1: " fmt, chip->dev->name, ##arg); \
+drivers/media/pci/cx25821/cx25821-alsa.c:	struct cx25821_audio_buffer *buf = chip->buf;
+drivers/media/pci/cx25821/cx25821-alsa.c:	struct cx25821_audio_buffer *buf = chip->buf;
+drivers/media/pci/cx25821/cx25821-alsa.c:	struct cx25821_dev *dev = chip->dev;
+drivers/media/pci/cx25821/cx25821-alsa.c:	cx25821_set_gpiopin_direction(chip->dev, 0, 0);
+drivers/media/pci/cx25821/cx25821-alsa.c:	cx25821_sram_channel_setup_audio(chip->dev, audio_ch, buf->bpl,
+drivers/media/pci/cx25821/cx25821-alsa.c:	atomic_set(&chip->count, 0);
+drivers/media/pci/cx25821/cx25821-alsa.c:		chip->num_periods, buf->bpl * chip->num_periods);
+drivers/media/pci/cx25821/cx25821-alsa.c:	cx_set(PCI_INT_MSK, chip->dev->pci_irqmask | PCI_MSK_AUD_INT);
+drivers/media/pci/cx25821/cx25821-alsa.c:	struct cx25821_dev *dev = chip->dev;
+drivers/media/pci/cx25821/cx25821-alsa.c:	struct cx25821_dev *dev = chip->dev;
+drivers/media/pci/cx25821/cx25821-alsa.c:		atomic_set(&chip->count, cx_read(AUD_A_GPCNT));
+drivers/media/pci/cx25821/cx25821-alsa.c:		snd_pcm_period_elapsed(chip->substream);
+drivers/media/pci/cx25821/cx25821-alsa.c:	struct cx25821_dev *dev = chip->dev;
+drivers/media/pci/cx25821/cx25821-alsa.c:	struct cx25821_riscmem *risc = &chip->buf->risc;
+drivers/media/pci/cx25821/cx25821-alsa.c:	BUG_ON(!chip->dma_size);
+drivers/media/pci/cx25821/cx25821-alsa.c:	cx25821_alsa_dma_free(chip->buf);
+drivers/media/pci/cx25821/cx25821-alsa.c:	pci_free_consistent(chip->pci, risc->size, risc->cpu, risc->dma);
+drivers/media/pci/cx25821/cx25821-alsa.c:	kfree(chip->buf);
+drivers/media/pci/cx25821/cx25821-alsa.c:	chip->buf = NULL;
+drivers/media/pci/cx25821/cx25821-alsa.c:	chip->dma_size = 0;
+drivers/media/pci/cx25821/cx25821-alsa.c:	chip->substream = substream;
+drivers/media/pci/cx25821/cx25821-alsa.c:	chip->period_size = params_period_bytes(hw_params);
+drivers/media/pci/cx25821/cx25821-alsa.c:	chip->num_periods = params_periods(hw_params);
+drivers/media/pci/cx25821/cx25821-alsa.c:	chip->dma_size = chip->period_size * params_periods(hw_params);
+drivers/media/pci/cx25821/cx25821-alsa.c:	BUG_ON(!chip->dma_size);
+drivers/media/pci/cx25821/cx25821-alsa.c:	BUG_ON(chip->num_periods & (chip->num_periods - 1));
+drivers/media/pci/cx25821/cx25821-alsa.c:	if (chip->period_size > AUDIO_LINE_SIZE)
+drivers/media/pci/cx25821/cx25821-alsa.c:		chip->period_size = AUDIO_LINE_SIZE;
+drivers/media/pci/cx25821/cx25821-alsa.c:	buf->bpl = chip->period_size;
+drivers/media/pci/cx25821/cx25821-alsa.c:	chip->buf = buf;
+drivers/media/pci/cx25821/cx25821-alsa.c:			(PAGE_ALIGN(chip->dma_size) >> PAGE_SHIFT));
+drivers/media/pci/cx25821/cx25821-alsa.c:	ret = cx25821_risc_databuffer_audio(chip->pci, &buf->risc, buf->sglist,
+drivers/media/pci/cx25821/cx25821-alsa.c:			chip->period_size, chip->num_periods, 1);
+drivers/media/pci/cx25821/cx25821-alsa.c:	substream->runtime->dma_area = chip->buf->vaddr;
+drivers/media/pci/cx25821/cx25821-alsa.c:	substream->runtime->dma_bytes = chip->dma_size;
+drivers/media/pci/cx25821/cx25821-alsa.c:	chip->buf = NULL;
+drivers/media/pci/cx25821/cx25821-alsa.c:	spin_lock(&chip->reg_lock);
+drivers/media/pci/cx25821/cx25821-alsa.c:	spin_unlock(&chip->reg_lock);
+drivers/media/pci/cx25821/cx25821-alsa.c:	count = atomic_read(&chip->count);
+drivers/media/pci/cx25821/cx25821-alsa.c:	err = snd_pcm_new(chip->card, name, device, 0, 1, &pcm);
+drivers/media/pci/cx25821/cx25821-alsa.c:	spin_lock_init(&chip->reg_lock);
+drivers/media/pci/cx25821/cx25821-alsa.c:	chip->dev = dev;
+drivers/media/pci/cx25821/cx25821-alsa.c:	chip->card = card;
+drivers/media/pci/cx25821/cx25821-alsa.c:	chip->pci = dev->pci;
+drivers/media/pci/cx25821/cx25821-alsa.c:	chip->iobase = pci_resource_start(dev->pci, 0);
+drivers/media/pci/cx25821/cx25821-alsa.c:	chip->irq = dev->pci->irq;
+drivers/media/pci/cx25821/cx25821-alsa.c:			  IRQF_SHARED, chip->dev->name, chip);
+drivers/media/pci/cx25821/cx25821-alsa.c:		pr_err("ERROR %s: can't get IRQ %d for ALSA\n", chip->dev->name,
+drivers/media/pci/cx25821/cx25821-alsa.c:	sprintf(card->longname, "%s at 0x%lx irq %d", chip->dev->name,
+drivers/media/pci/cx25821/cx25821-alsa.c:		chip->iobase, chip->irq);
+drivers/media/pci/cx88/cx88-alsa.c:			chip->core->name, ##arg);			\
+drivers/media/pci/cx88/cx88-alsa.c:	struct cx88_audio_buffer *buf = chip->buf;
+drivers/media/pci/cx88/cx88-alsa.c:	struct cx88_core *core = chip->core;
+drivers/media/pci/cx88/cx88-alsa.c:	cx88_sram_channel_setup(chip->core, audio_ch, buf->bpl, buf->risc.dma);
+drivers/media/pci/cx88/cx88-alsa.c:	atomic_set(&chip->count, 0);
+drivers/media/pci/cx88/cx88-alsa.c:		chip->num_periods, buf->bpl * chip->num_periods);
+drivers/media/pci/cx88/cx88-alsa.c:	cx_set(MO_PCI_INTMSK, chip->core->pci_irqmask | PCI_INT_AUDINT);
+drivers/media/pci/cx88/cx88-alsa.c:		cx88_sram_channel_dump(chip->core, audio_ch);
+drivers/media/pci/cx88/cx88-alsa.c:	struct cx88_core *core = chip->core;
+drivers/media/pci/cx88/cx88-alsa.c:		cx88_sram_channel_dump(chip->core,
+drivers/media/pci/cx88/cx88-alsa.c:	struct cx88_core *core = chip->core;
+drivers/media/pci/cx88/cx88-alsa.c:		atomic_set(&chip->count, cx_read(MO_AUDD_GPCNT));
+drivers/media/pci/cx88/cx88-alsa.c:		snd_pcm_period_elapsed(chip->substream);
+drivers/media/pci/cx88/cx88-alsa.c:	struct cx88_core *core = chip->core;
+drivers/media/pci/cx88/cx88-alsa.c:	struct cx88_audio_buffer *buf = chip->buf;
+drivers/media/pci/cx88/cx88-alsa.c:	struct cx88_riscmem *risc = &chip->buf->risc;
+drivers/media/pci/cx88/cx88-alsa.c:	WARN_ON(!chip->dma_size);
+drivers/media/pci/cx88/cx88-alsa.c:	cx88_alsa_dma_free(chip->buf);
+drivers/media/pci/cx88/cx88-alsa.c:		pci_free_consistent(chip->pci, risc->size,
+drivers/media/pci/cx88/cx88-alsa.c:	kfree(chip->buf);
+drivers/media/pci/cx88/cx88-alsa.c:	chip->buf = NULL;
+drivers/media/pci/cx88/cx88-alsa.c:	chip->substream = substream;
+drivers/media/pci/cx88/cx88-alsa.c:	chip->period_size = params_period_bytes(hw_params);
+drivers/media/pci/cx88/cx88-alsa.c:	chip->num_periods = params_periods(hw_params);
+drivers/media/pci/cx88/cx88-alsa.c:	chip->dma_size = chip->period_size * params_periods(hw_params);
+drivers/media/pci/cx88/cx88-alsa.c:	WARN_ON(!chip->dma_size);
+drivers/media/pci/cx88/cx88-alsa.c:	WARN_ON(chip->num_periods & (chip->num_periods - 1));
+drivers/media/pci/cx88/cx88-alsa.c:	chip->buf = buf;
+drivers/media/pci/cx88/cx88-alsa.c:	buf->bpl = chip->period_size;
+drivers/media/pci/cx88/cx88-alsa.c:				 (PAGE_ALIGN(chip->dma_size) >> PAGE_SHIFT));
+drivers/media/pci/cx88/cx88-alsa.c:	ret = cx88_risc_databuffer(chip->pci, &buf->risc, buf->sglist,
+drivers/media/pci/cx88/cx88-alsa.c:				   chip->period_size, chip->num_periods, 1);
+drivers/media/pci/cx88/cx88-alsa.c:	substream->runtime->dma_area = chip->buf->vaddr;
+drivers/media/pci/cx88/cx88-alsa.c:	substream->runtime->dma_bytes = chip->dma_size;
+drivers/media/pci/cx88/cx88-alsa.c:	spin_lock(&chip->reg_lock);
+drivers/media/pci/cx88/cx88-alsa.c:	spin_unlock(&chip->reg_lock);
+drivers/media/pci/cx88/cx88-alsa.c:	count = atomic_read(&chip->count);
+drivers/media/pci/cx88/cx88-alsa.c:	err = snd_pcm_new(chip->card, name, device, 0, 1, &pcm);
+drivers/media/pci/cx88/cx88-alsa.c:	struct cx88_core *core = chip->core;
+drivers/media/pci/cx88/cx88-alsa.c:	struct cx88_core *core = chip->core;
+drivers/media/pci/cx88/cx88-alsa.c:	struct cx88_core *core = chip->core;
+drivers/media/pci/cx88/cx88-alsa.c:	spin_lock_irq(&chip->reg_lock);
+drivers/media/pci/cx88/cx88-alsa.c:	spin_unlock_irq(&chip->reg_lock);
+drivers/media/pci/cx88/cx88-alsa.c:	struct cx88_core *core = chip->core;
+drivers/media/pci/cx88/cx88-alsa.c:	struct cx88_core *core = chip->core;
+drivers/media/pci/cx88/cx88-alsa.c:	spin_lock_irq(&chip->reg_lock);
+drivers/media/pci/cx88/cx88-alsa.c:	spin_unlock_irq(&chip->reg_lock);
+drivers/media/pci/cx88/cx88-alsa.c:	struct cx88_core *core = chip->core;
+drivers/media/pci/cx88/cx88-alsa.c:	struct cx88_core *core = chip->core;
+drivers/media/pci/cx88/cx88-alsa.c:	if (chip->irq >= 0)
+drivers/media/pci/cx88/cx88-alsa.c:		free_irq(chip->irq, chip);
+drivers/media/pci/cx88/cx88-alsa.c:	cx88_core_put(chip->core, chip->pci);
+drivers/media/pci/cx88/cx88-alsa.c:	pci_disable_device(chip->pci);
+drivers/media/pci/cx88/cx88-alsa.c:	chip->card = card;
+drivers/media/pci/cx88/cx88-alsa.c:	chip->pci = pci;
+drivers/media/pci/cx88/cx88-alsa.c:	chip->irq = -1;
+drivers/media/pci/cx88/cx88-alsa.c:	spin_lock_init(&chip->reg_lock);
+drivers/media/pci/cx88/cx88-alsa.c:	chip->core = core;
+drivers/media/pci/cx88/cx88-alsa.c:	err = request_irq(chip->pci->irq, cx8801_irq,
+drivers/media/pci/cx88/cx88-alsa.c:			  IRQF_SHARED, chip->core->name, chip);
+drivers/media/pci/cx88/cx88-alsa.c:			chip->core->name, chip->pci->irq);
+drivers/media/pci/cx88/cx88-alsa.c:	chip->irq = pci->irq;
+drivers/media/pci/cx88/cx88-alsa.c:	synchronize_irq(chip->irq);
+drivers/media/pci/saa7134/saa7134-alsa.c:	dev = chip->dev;
+drivers/media/pci/saa7134/saa7134-alsa.c:	spin_lock_irq(&chip->mixer_lock);
+drivers/media/pci/saa7134/saa7134-alsa.c:	old_addr = chip->capture_source_addr;
+drivers/media/pci/saa7134/saa7134-alsa.c:			 chip->capture_source[0] != left ||
+drivers/media/pci/saa7134/saa7134-alsa.c:			 chip->capture_source[1] != right;
+drivers/media/pci/saa7134/saa7134-alsa.c:		chip->capture_source[0] = left;
+drivers/media/pci/saa7134/saa7134-alsa.c:		chip->capture_source[1] = right;
+drivers/media/pci/saa7134/saa7134-alsa.c:		chip->capture_source_addr = addr;
+drivers/media/pci/saa7134/saa7134-alsa.c:	spin_unlock_irq(&chip->mixer_lock);
+drivers/media/pci/saa7134/saa7134-alsa.c:			snd_ctl_notify(chip->card,
+drivers/media/pci/saa7134/saa7134-alsa.c:				       &chip->capture_ctl[addr]->id);
+drivers/media/pci/saa7134/saa7134-alsa.c:			snd_ctl_notify(chip->card,
+drivers/media/pci/saa7134/saa7134-alsa.c:				       &chip->capture_ctl[old_addr]->id);
+drivers/media/pci/saa7134/saa7134-alsa.c:	ucontrol->value.integer.value[0] = chip->mixer_volume[addr][0];
+drivers/media/pci/saa7134/saa7134-alsa.c:	ucontrol->value.integer.value[1] = chip->mixer_volume[addr][1];
+drivers/media/pci/saa7134/saa7134-alsa.c:	struct saa7134_dev *dev = chip->dev;
+drivers/media/pci/saa7134/saa7134-alsa.c:	spin_lock_irq(&chip->mixer_lock);
+drivers/media/pci/saa7134/saa7134-alsa.c:	if (chip->mixer_volume[addr][0] != left) {
+drivers/media/pci/saa7134/saa7134-alsa.c:	if (chip->mixer_volume[addr][1] != right) {
+drivers/media/pci/saa7134/saa7134-alsa.c:		chip->mixer_volume[addr][0] = left;
+drivers/media/pci/saa7134/saa7134-alsa.c:		chip->mixer_volume[addr][1] = right;
+drivers/media/pci/saa7134/saa7134-alsa.c:	spin_unlock_irq(&chip->mixer_lock);
+drivers/media/pci/saa7134/saa7134-alsa.c:	spin_lock_irq(&chip->mixer_lock);
+drivers/media/pci/saa7134/saa7134-alsa.c:	if (chip->capture_source_addr == addr) {
+drivers/media/pci/saa7134/saa7134-alsa.c:		ucontrol->value.integer.value[0] = chip->capture_source[0];
+drivers/media/pci/saa7134/saa7134-alsa.c:		ucontrol->value.integer.value[1] = chip->capture_source[1];
+drivers/media/pci/saa7134/saa7134-alsa.c:	spin_unlock_irq(&chip->mixer_lock);
+drivers/media/pci/saa7134/saa7134-alsa.c:	struct snd_card *card = chip->card;
+drivers/media/pci/saa7134/saa7134-alsa.c:		chip->capture_ctl[addr] = kcontrol;
+drivers/media/pci/saa7134/saa7134-alsa.c:	chip->capture_source_addr = MIXER_ADDR_UNSELECTED;
+drivers/media/pci/saa7134/saa7134-alsa.c:	if (chip->dev->dmasound.priv_data == NULL)
+drivers/media/pci/saa7134/saa7134-alsa.c:	if (chip->irq >= 0)
+drivers/media/pci/saa7134/saa7134-alsa.c:		free_irq(chip->irq, &chip->dev->dmasound);
+drivers/media/pci/saa7134/saa7134-alsa.c:	chip->dev->dmasound.priv_data = NULL;
+drivers/media/pci/saa7134/saa7134-alsa.c:	spin_lock_init(&chip->lock);
+drivers/media/pci/saa7134/saa7134-alsa.c:	spin_lock_init(&chip->mixer_lock);
+drivers/media/pci/saa7134/saa7134-alsa.c:	chip->dev = dev;
+drivers/media/pci/saa7134/saa7134-alsa.c:	chip->card = card;
+drivers/media/pci/saa7134/saa7134-alsa.c:	chip->pci = dev->pci;
+drivers/media/pci/saa7134/saa7134-alsa.c:	chip->iobase = pci_resource_start(dev->pci, 0);
+drivers/media/pci/saa7134/saa7134-alsa.c:	chip->irq = dev->pci->irq;
+drivers/media/pci/saa7134/saa7134-alsa.c:		chip->dev->name, chip->iobase, chip->irq);
+drivers/media/platform/rockchip/rga/Makefile:rockchip-rga-objs := rga.o rga-hw.o rga-buf.o
+drivers/media/platform/rockchip/rga/Makefile:obj-$(CONFIG_VIDEO_ROCKCHIP_RGA) += rockchip-rga.o
+drivers/media/platform/rockchip/rga/rga.c:	strscpy(cap->card, "rockchip-rga", sizeof(cap->card));
+drivers/media/platform/rockchip/rga/rga.c:	.name = "rockchip-rga",
+drivers/media/platform/rockchip/rga/rga.h:#define RGA_NAME "rockchip-rga"
+drivers/media/usb/cx231xx/cx231xx-video.c:	switch (chip->match.addr) {
+drivers/media/usb/cx231xx/cx231xx-video.c:		strscpy(chip->name, "AFE (byte)", sizeof(chip->name));
+drivers/media/usb/cx231xx/cx231xx-video.c:		strscpy(chip->name, "Video (byte)", sizeof(chip->name));
+drivers/media/usb/cx231xx/cx231xx-video.c:		strscpy(chip->name, "I2S (byte)", sizeof(chip->name));
+drivers/media/usb/cx231xx/cx231xx-video.c:		strscpy(chip->name, "AFE (dword)", sizeof(chip->name));
+drivers/media/usb/cx231xx/cx231xx-video.c:		strscpy(chip->name, "Video (dword)", sizeof(chip->name));
+drivers/media/usb/cx231xx/cx231xx-video.c:		strscpy(chip->name, "I2S (dword)", sizeof(chip->name));
+drivers/media/usb/em28xx/em28xx-video.c:	if (chip->match.addr > 1)
+drivers/media/usb/em28xx/em28xx-video.c:	if (chip->match.addr == 1)
+drivers/media/usb/em28xx/em28xx-video.c:		strscpy(chip->name, "ac97", sizeof(chip->name));
+drivers/media/usb/em28xx/em28xx-video.c:		strscpy(chip->name,
+drivers/media/usb/em28xx/em28xx-video.c:			dev->v4l2->v4l2_dev.name, sizeof(chip->name));
+drivers/media/usb/gspca/gspca.c:	return chip->match.addr ? -EINVAL : 0;
+drivers/media/usb/gspca/sn9c20x.c:	if (chip->match.addr > 1)
+drivers/media/usb/gspca/sn9c20x.c:	if (chip->match.addr == 1)
+drivers/media/usb/gspca/sn9c20x.c:		strscpy(chip->name, "sensor", sizeof(chip->name));
+drivers/media/usb/pvrusb2/pvrusb2-devattr.h:	   interpreted by logic which must send commands to the chip-level
+drivers/media/usb/pvrusb2/pvrusb2-i2c-core.c:		   that the normal i2c chip-level driver expects. */
+drivers/media/usb/tm6000/tm6000-alsa.c:		printk(KERN_INFO "%s/1: " fmt, chip->core->name , ## arg); \
+drivers/media/usb/tm6000/tm6000-alsa.c:	struct tm6000_core *core = chip->core;
+drivers/media/usb/tm6000/tm6000-alsa.c:	struct tm6000_core *core = chip->core;
+drivers/media/usb/tm6000/tm6000-alsa.c:	chip->substream = substream;
+drivers/media/usb/tm6000/tm6000-alsa.c:	struct tm6000_core *core = chip->core;
+drivers/media/usb/tm6000/tm6000-alsa.c:	struct snd_pcm_substream *substream = chip->substream;
+drivers/media/usb/tm6000/tm6000-alsa.c:	buf_pos = chip->buf_pos;
+drivers/media/usb/tm6000/tm6000-alsa.c:	chip->buf_pos += length;
+drivers/media/usb/tm6000/tm6000-alsa.c:	if (chip->buf_pos >= runtime->buffer_size)
+drivers/media/usb/tm6000/tm6000-alsa.c:		chip->buf_pos -= runtime->buffer_size;
+drivers/media/usb/tm6000/tm6000-alsa.c:	chip->period_pos += length;
+drivers/media/usb/tm6000/tm6000-alsa.c:	if (chip->period_pos >= runtime->period_size) {
+drivers/media/usb/tm6000/tm6000-alsa.c:		chip->period_pos -= runtime->period_size;
+drivers/media/usb/tm6000/tm6000-alsa.c:	struct tm6000_core *core = chip->core;
+drivers/media/usb/tm6000/tm6000-alsa.c:	chip->buf_pos = 0;
+drivers/media/usb/tm6000/tm6000-alsa.c:	chip->period_pos = 0;
+drivers/media/usb/tm6000/tm6000-alsa.c:	struct tm6000_core *core = chip->core;
+drivers/media/usb/tm6000/tm6000-alsa.c:	return chip->buf_pos;
+drivers/media/usb/tm6000/tm6000-alsa.c:	chip->core = dev;
+drivers/media/usb/tm6000/tm6000-alsa.c:	chip->card = card;
+drivers/media/usb/tm6000/tm6000-alsa.c:	spin_lock_init(&chip->reg_lock);
+drivers/media/usb/tm6000/tm6000-alsa.c:	if (!chip->card)
+drivers/media/usb/tm6000/tm6000-alsa.c:	snd_card_free(chip->card);
+drivers/media/usb/tm6000/tm6000-alsa.c:	chip->card = NULL;
+drivers/media/usb/usbtv/usbtv-audio.c:	chip->snd_substream = substream;
+drivers/media/usb/usbtv/usbtv-audio.c:	if (atomic_read(&chip->snd_stream)) {
+drivers/media/usb/usbtv/usbtv-audio.c:		atomic_set(&chip->snd_stream, 0);
+drivers/media/usb/usbtv/usbtv-audio.c:		schedule_work(&chip->snd_trigger);
+drivers/media/usb/usbtv/usbtv-audio.c:		dev_warn(chip->dev, "pcm audio buffer allocation failure %i\n",
+drivers/media/usb/usbtv/usbtv-audio.c:	chip->snd_buffer_pos = 0;
+drivers/media/usb/usbtv/usbtv-audio.c:	chip->snd_period_pos = 0;
+drivers/media/usb/usbtv/usbtv-audio.c:	struct snd_pcm_substream *substream = chip->snd_substream;
+drivers/media/usb/usbtv/usbtv-audio.c:		dev_warn(chip->dev, "unknown audio urb status %i\n",
+drivers/media/usb/usbtv/usbtv-audio.c:	if (!atomic_read(&chip->snd_stream))
+drivers/media/usb/usbtv/usbtv-audio.c:	buffer_pos = chip->snd_buffer_pos;
+drivers/media/usb/usbtv/usbtv-audio.c:	period_pos = chip->snd_period_pos;
+drivers/media/usb/usbtv/usbtv-audio.c:	chip->snd_buffer_pos = buffer_pos;
+drivers/media/usb/usbtv/usbtv-audio.c:	chip->snd_period_pos = period_pos;
+drivers/media/usb/usbtv/usbtv-audio.c:	chip->snd_bulk_urb = usb_alloc_urb(0, GFP_KERNEL);
+drivers/media/usb/usbtv/usbtv-audio.c:	if (chip->snd_bulk_urb == NULL)
+drivers/media/usb/usbtv/usbtv-audio.c:	pipe = usb_rcvbulkpipe(chip->udev, USBTV_AUDIO_ENDP);
+drivers/media/usb/usbtv/usbtv-audio.c:	chip->snd_bulk_urb->transfer_buffer = kzalloc(
+drivers/media/usb/usbtv/usbtv-audio.c:	if (chip->snd_bulk_urb->transfer_buffer == NULL)
+drivers/media/usb/usbtv/usbtv-audio.c:	usb_fill_bulk_urb(chip->snd_bulk_urb, chip->udev, pipe,
+drivers/media/usb/usbtv/usbtv-audio.c:		chip->snd_bulk_urb->transfer_buffer, USBTV_AUDIO_URBSIZE,
+drivers/media/usb/usbtv/usbtv-audio.c:	usb_clear_halt(chip->udev, pipe);
+drivers/media/usb/usbtv/usbtv-audio.c:	usb_submit_urb(chip->snd_bulk_urb, GFP_ATOMIC);
+drivers/media/usb/usbtv/usbtv-audio.c:	usb_free_urb(chip->snd_bulk_urb);
+drivers/media/usb/usbtv/usbtv-audio.c:	chip->snd_bulk_urb = NULL;
+drivers/media/usb/usbtv/usbtv-audio.c:	if (chip->snd_bulk_urb) {
+drivers/media/usb/usbtv/usbtv-audio.c:		usb_kill_urb(chip->snd_bulk_urb);
+drivers/media/usb/usbtv/usbtv-audio.c:		kfree(chip->snd_bulk_urb->transfer_buffer);
+drivers/media/usb/usbtv/usbtv-audio.c:		usb_free_urb(chip->snd_bulk_urb);
+drivers/media/usb/usbtv/usbtv-audio.c:		chip->snd_bulk_urb = NULL;
+drivers/media/usb/usbtv/usbtv-audio.c:	if (!chip->snd)
+drivers/media/usb/usbtv/usbtv-audio.c:	if (atomic_read(&chip->snd_stream))
+drivers/media/usb/usbtv/usbtv-audio.c:		atomic_set(&chip->snd_stream, 1);
+drivers/media/usb/usbtv/usbtv-audio.c:		atomic_set(&chip->snd_stream, 0);
+drivers/media/usb/usbtv/usbtv-audio.c:	schedule_work(&chip->snd_trigger);
+drivers/media/usb/usbtv/usbtv-audio.c:	return chip->snd_buffer_pos;
+drivers/memory/emif.h: * ZQ Calibration simultaneously on both chip-selects:
+drivers/memory/omap-gpmc.c:/* Define chip-selects as reserved by default until probe completes */
+drivers/memory/omap-gpmc.c: * gpmc_cs_remap - remaps a chip-select physical base address
+drivers/memory/omap-gpmc.c: * @cs:		chip-select to remap
+drivers/memory/omap-gpmc.c: * @base:	physical base address to re-map chip-select to
+drivers/memory/omap-gpmc.c: * Re-maps a chip-select to a new physical base address specified by
+drivers/memory/omap-gpmc.c:		pr_err("%s: requested chip-select is disabled\n", __func__);
+drivers/memory/omap-gpmc.c:		pr_err("%s: requested chip-select is disabled\n", __func__);
+drivers/memory/omap-gpmc.c: * @cs:		GPMC chip-select to program
+drivers/memory/omap-gpmc.c: * Programs non-timing related settings for a GPMC chip-select, such as
+drivers/memory/omap-gpmc.c: * for each chip-select that is being used and must be called before
+drivers/memory/omap-gpmc.c: * Allocates and configures a GPMC chip-select for a child device.
+drivers/memory/omap-gpmc.c:		pr_err("%s: number of chip-selects not defined\n", __func__);
+drivers/memory/omap-gpmc.c:		pr_err("%s: all chip-selects are disabled\n", __func__);
+drivers/memory/omap-gpmc.c:		pr_err("%s: number of supported chip-selects cannot be > %d\n",
+drivers/memory/ti-aemif.c: * @cs: chip-select number
+drivers/memory/ti-aemif.c: * @num_cs: number of assigned chip-selects
+drivers/memory/ti-aemif.c: * @cs_data: array of chip-select settings
+drivers/memory/ti-aemif.c: * chip-select.
+drivers/memstick/host/jmb38x_ms.c:		if (1 != dma_map_sg(&host->chip->pdev->dev, &host->req->sg, 1,
+drivers/memstick/host/jmb38x_ms.c:		dma_unmap_sg(&host->chip->pdev->dev, &host->req->sg, 1,
+drivers/memstick/host/jmb38x_ms.c:	dev_dbg(&host->chip->pdev->dev, "irq_status = %08x\n", irq_status);
+drivers/memstick/host/jmb38x_ms.c:				dev_dbg(&host->chip->pdev->dev, "TPC_ERR\n");
+drivers/memstick/host/jmb38x_ms.c:		dev_dbg(&host->chip->pdev->dev, "media changed\n");
+drivers/memstick/host/jmb38x_ms.c:	dev_dbg(&host->chip->pdev->dev, "abort\n");
+drivers/memstick/host/jmb38x_ms.c:			dev_dbg(&host->chip->pdev->dev, "tasklet req %d\n", rc);
+drivers/memstick/host/jmb38x_ms.c:	dev_dbg(&host->chip->pdev->dev, "reset_req timeout\n");
+drivers/memstick/host/jmb38x_ms.c:	dev_dbg(&host->chip->pdev->dev, "reset timeout\n");
+drivers/memstick/host/jmb38x_ms.c:			dev_dbg(&host->chip->pdev->dev, "power on\n");
+drivers/memstick/host/jmb38x_ms.c:			dev_dbg(&host->chip->pdev->dev, "power off\n");
+drivers/memstick/host/jmb38x_ms.c:		dev_dbg(&host->chip->pdev->dev,
+drivers/memstick/host/jmb38x_ms.c:		pci_write_config_byte(host->chip->pdev,
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->ReplyFifo, pa);
+drivers/message/fusion/mptbase.c:	u32 pa = CHIPREG_READ32_dmasync(&ioc->chip->ReplyFifo);
+drivers/message/fusion/mptbase.c:		pa = CHIPREG_READ32_dmasync(&ioc->chip->ReplyFifo);
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->RequestFifo, mf_dma_addr);
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->RequestHiPriFifo, mf_dma_addr);
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->Doorbell,
+drivers/message/fusion/mptbase.c:	if (!(CHIPREG_READ32(&ioc->chip->Doorbell) & MPI_DOORBELL_ACTIVE))
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
+drivers/message/fusion/mptbase.c:		CHIPREG_WRITE32(&ioc->chip->Doorbell, word);
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
+drivers/message/fusion/mptbase.c:	if (CHIPREG_READ32(&ioc->chip->Doorbell)
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->Doorbell,
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
+drivers/message/fusion/mptbase.c:	CHIPREG_READ32(&ioc->chip->IntStatus);
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
+drivers/message/fusion/mptbase.c:	    CHIPREG_READ32(&ioc->chip->Doorbell));
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
+drivers/message/fusion/mptbase.c:			CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask,
+drivers/message/fusion/mptbase.c:				CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask, MPI_HIM_DIM);
+drivers/message/fusion/mptbase.c:		CHIPREG_WRITE32(&ioc->chip->IntMask, MPI_HIM_DIM);
+drivers/message/fusion/mptbase.c:			CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask,
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
+drivers/message/fusion/mptbase.c:	CHIPREG_READ32(&ioc->chip->IntStatus);
+drivers/message/fusion/mptbase.c:	s = CHIPREG_READ32(&ioc->chip->Doorbell);
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->Diagnostic, (MPI_DIAG_PREVENT_IOC_BOOT | MPI_DIAG_DISABLE_ARM));
+drivers/message/fusion/mptbase.c:	diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_RESET_ADAPTER);
+drivers/message/fusion/mptbase.c:		diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->Diagnostic, (MPI_DIAG_RW_ENABLE | MPI_DIAG_DISABLE_ARM));
+drivers/message/fusion/mptbase.c:	CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, pFwHeader->LoadStartAddress);
+drivers/message/fusion/mptbase.c:		CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, *ptrFw++);
+drivers/message/fusion/mptbase.c:		CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, load_addr);
+drivers/message/fusion/mptbase.c:			CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, *ptrFw++);
+drivers/message/fusion/mptbase.c:	CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, pFwHeader->IopResetRegAddr);
+drivers/message/fusion/mptbase.c:	CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, pFwHeader->IopResetVectorValue);
+drivers/message/fusion/mptbase.c:		CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, 0x3F000000);
+drivers/message/fusion/mptbase.c:		diagRwData = CHIPREG_PIO_READ32(&ioc->pio_chip->DiagRwData);
+drivers/message/fusion/mptbase.c:		CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, 0x3F000000);
+drivers/message/fusion/mptbase.c:		CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, diagRwData);
+drivers/message/fusion/mptbase.c:		diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
+drivers/message/fusion/mptbase.c:		CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val |
+drivers/message/fusion/mptbase.c:	diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val);
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
+drivers/message/fusion/mptbase.c:			&ioc->chip->Doorbell, &ioc->chip->Reset_1078));
+drivers/message/fusion/mptbase.c:		CHIPREG_WRITE32(&ioc->chip->Reset_1078, 0x07);
+drivers/message/fusion/mptbase.c:			doorbell = CHIPREG_READ32(&ioc->chip->Doorbell);
+drivers/message/fusion/mptbase.c:	diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
+drivers/message/fusion/mptbase.c:			diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic);
+drivers/message/fusion/mptbase.c:			CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
+drivers/message/fusion/mptbase.c:			CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
+drivers/message/fusion/mptbase.c:			CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
+drivers/message/fusion/mptbase.c:			CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);
+drivers/message/fusion/mptbase.c:			CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);
+drivers/message/fusion/mptbase.c:			CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);
+drivers/message/fusion/mptbase.c:			diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
+drivers/message/fusion/mptbase.c:				diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic);
+drivers/message/fusion/mptbase.c:		CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_DISABLE_ARM);
+drivers/message/fusion/mptbase.c:		CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_RESET_ADAPTER);
+drivers/message/fusion/mptbase.c:				diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
+drivers/message/fusion/mptbase.c:				doorbell = CHIPREG_READ32(&ioc->chip->Doorbell);
+drivers/message/fusion/mptbase.c:	diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
+drivers/message/fusion/mptbase.c:			diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic);
+drivers/message/fusion/mptbase.c:	diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
+drivers/message/fusion/mptbase.c:		CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
+drivers/message/fusion/mptbase.c:		CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
+drivers/message/fusion/mptbase.c:		CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
+drivers/message/fusion/mptbase.c:		CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);
+drivers/message/fusion/mptbase.c:		CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);
+drivers/message/fusion/mptbase.c:		CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);
+drivers/message/fusion/mptbase.c:		diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val);
+drivers/message/fusion/mptbase.c:	diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFFFFFFFF);
+drivers/message/fusion/mptbase.c:	diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
+drivers/message/fusion/mptbase.c:			diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic);
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->Doorbell, reset_type<<MPI_DOORBELL_FUNCTION_SHIFT);
+drivers/message/fusion/mptbase.c:		CHIPREG_WRITE32(&ioc->chip->ReplyFifo, alloc_dma);
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->Doorbell,
+drivers/message/fusion/mptbase.c:	if (!(CHIPREG_READ32(&ioc->chip->Doorbell) & MPI_DOORBELL_ACTIVE))
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
+drivers/message/fusion/mptbase.c:			CHIPREG_WRITE32(&ioc->chip->Doorbell, word);
+drivers/message/fusion/mptbase.c:			intstat = CHIPREG_READ32(&ioc->chip->IntStatus);
+drivers/message/fusion/mptbase.c:			intstat = CHIPREG_READ32(&ioc->chip->IntStatus);
+drivers/message/fusion/mptbase.c:			intstat = CHIPREG_READ32(&ioc->chip->IntStatus);
+drivers/message/fusion/mptbase.c:			intstat = CHIPREG_READ32(&ioc->chip->IntStatus);
+drivers/message/fusion/mptbase.c:		hs_reply[u16cnt++] = le16_to_cpu(CHIPREG_READ32(&ioc->chip->Doorbell) & 0x0000FFFF);
+drivers/message/fusion/mptbase.c:		CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
+drivers/message/fusion/mptbase.c:			hs_reply[u16cnt++] = le16_to_cpu(CHIPREG_READ32(&ioc->chip->Doorbell) & 0x0000FFFF);
+drivers/message/fusion/mptbase.c:			CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
+drivers/message/fusion/mptbase.c:		hword = le16_to_cpu(CHIPREG_READ32(&ioc->chip->Doorbell) & 0x0000FFFF);
+drivers/message/fusion/mptbase.c:		CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
+drivers/message/fusion/mptbase.c:		CHIPREG_WRITE32(&ioc->chip->Doorbell, 0xC0FFEE00);
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
+drivers/message/fusion/mptbase.c:	CHIPREG_WRITE32(&ioc->chip->IntMask, MPI_HIM_DIM);
+drivers/mfd/88pm800.c:	struct pm80x_subchip *subchip = chip->subchip;
+drivers/mfd/88pm800.c:	struct regmap *map = subchip->regmap_gpadc;
+drivers/mfd/88pm800.c:		dev_warn(chip->dev,
+drivers/mfd/88pm800.c:	dev_info(chip->dev, "pm800 device_gpadc_init: Done\n");
+drivers/mfd/88pm800.c:	dev_info(chip->dev, "pm800 device_gpadc_init: Failed!\n");
+drivers/mfd/88pm800.c:	ret = mfd_add_devices(chip->dev, 0, &onkey_devs[0],
+drivers/mfd/88pm800.c:		dev_err(chip->dev, "Failed to add onkey subdev\n");
+drivers/mfd/88pm800.c:	ret = mfd_add_devices(chip->dev, 0, &rtc_devs[0],
+drivers/mfd/88pm800.c:		dev_err(chip->dev, "Failed to add rtc subdev\n");
+drivers/mfd/88pm800.c:	ret = mfd_add_devices(chip->dev, 0, &regulator_devs[0],
+drivers/mfd/88pm800.c:		dev_err(chip->dev, "Failed to add regulator subdev\n");
+drivers/mfd/88pm800.c:	struct regmap *map = chip->regmap;
+drivers/mfd/88pm800.c:	if (!map || !chip->irq) {
+drivers/mfd/88pm800.c:		dev_err(chip->dev, "incorrect parameters\n");
+drivers/mfd/88pm800.c:	    regmap_add_irq_chip(chip->regmap, chip->irq, flags, -1,
+drivers/mfd/88pm800.c:				chip->regmap_irq_chip, &chip->irq_data);
+drivers/mfd/88pm800.c:	regmap_del_irq_chip(chip->irq, chip->irq_data);
+drivers/mfd/88pm800.c:	struct i2c_client *client = chip->client;
+drivers/mfd/88pm800.c:	subchip = chip->subchip;
+drivers/mfd/88pm800.c:	if (!subchip || !subchip->power_page_addr || !subchip->gpadc_page_addr)
+drivers/mfd/88pm800.c:	subchip->power_page = i2c_new_dummy_device(client->adapter,
+drivers/mfd/88pm800.c:					    subchip->power_page_addr);
+drivers/mfd/88pm800.c:	if (IS_ERR(subchip->power_page)) {
+drivers/mfd/88pm800.c:		ret = PTR_ERR(subchip->power_page);
+drivers/mfd/88pm800.c:	subchip->regmap_power = devm_regmap_init_i2c(subchip->power_page,
+drivers/mfd/88pm800.c:	if (IS_ERR(subchip->regmap_power)) {
+drivers/mfd/88pm800.c:		ret = PTR_ERR(subchip->regmap_power);
+drivers/mfd/88pm800.c:		dev_err(chip->dev,
+drivers/mfd/88pm800.c:	i2c_set_clientdata(subchip->power_page, chip);
+drivers/mfd/88pm800.c:	subchip->gpadc_page = i2c_new_dummy_device(client->adapter,
+drivers/mfd/88pm800.c:					    subchip->gpadc_page_addr);
+drivers/mfd/88pm800.c:	if (IS_ERR(subchip->gpadc_page)) {
+drivers/mfd/88pm800.c:		ret = PTR_ERR(subchip->gpadc_page);
+drivers/mfd/88pm800.c:	subchip->regmap_gpadc = devm_regmap_init_i2c(subchip->gpadc_page,
+drivers/mfd/88pm800.c:	if (IS_ERR(subchip->regmap_gpadc)) {
+drivers/mfd/88pm800.c:		ret = PTR_ERR(subchip->regmap_gpadc);
+drivers/mfd/88pm800.c:		dev_err(chip->dev,
+drivers/mfd/88pm800.c:	i2c_set_clientdata(subchip->gpadc_page, chip);
+drivers/mfd/88pm800.c:	subchip = chip->subchip;
+drivers/mfd/88pm800.c:	if (subchip && subchip->power_page)
+drivers/mfd/88pm800.c:		i2c_unregister_device(subchip->power_page);
+drivers/mfd/88pm800.c:	if (subchip && subchip->gpadc_page)
+drivers/mfd/88pm800.c:		i2c_unregister_device(subchip->gpadc_page);
+drivers/mfd/88pm800.c:	ret = regmap_read(chip->regmap, PM800_RTC_CONTROL, &val);
+drivers/mfd/88pm800.c:		dev_err(chip->dev, "Failed to read RTC register: %d\n", ret);
+drivers/mfd/88pm800.c:		dev_err(chip->dev, "[%s]Failed to init gpadc\n", __func__);
+drivers/mfd/88pm800.c:	chip->regmap_irq_chip = &pm800_irq_chip;
+drivers/mfd/88pm800.c:		dev_err(chip->dev, "[%s]Failed to init pm800 irq\n", __func__);
+drivers/mfd/88pm800.c:		dev_err(chip->dev, "Failed to add onkey subdev\n");
+drivers/mfd/88pm800.c:		dev_err(chip->dev, "Failed to add rtc subdev\n");
+drivers/mfd/88pm800.c:		dev_err(chip->dev, "Failed to add regulators subdev\n");
+drivers/mfd/88pm800.c:	mfd_remove_devices(chip->dev);
+drivers/mfd/88pm800.c:	subchip->power_page_addr = client->addr + 1;
+drivers/mfd/88pm800.c:	subchip->gpadc_page_addr = client->addr + 2;
+drivers/mfd/88pm800.c:	chip->subchip = subchip;
+drivers/mfd/88pm800.c:		dev_err(chip->dev, "Failed to initialize 88pm800 devices\n");
+drivers/mfd/88pm800.c:	mfd_remove_devices(chip->dev);
+drivers/mfd/88pm805.c:	struct regmap *map = chip->regmap;
+drivers/mfd/88pm805.c:	if (!map || !chip->irq) {
+drivers/mfd/88pm805.c:		dev_err(chip->dev, "incorrect parameters\n");
+drivers/mfd/88pm805.c:	    regmap_add_irq_chip(chip->regmap, chip->irq, flags, -1,
+drivers/mfd/88pm805.c:				chip->regmap_irq_chip, &chip->irq_data);
+drivers/mfd/88pm805.c:	regmap_del_irq_chip(chip->irq, chip->irq_data);
+drivers/mfd/88pm805.c:	struct regmap *map = chip->regmap;
+drivers/mfd/88pm805.c:		dev_err(chip->dev, "regmap is invalid\n");
+drivers/mfd/88pm805.c:	chip->regmap_irq_chip = &pm805_irq_chip;
+drivers/mfd/88pm805.c:		dev_err(chip->dev, "Failed to init pm805 irq!\n");
+drivers/mfd/88pm805.c:	ret = mfd_add_devices(chip->dev, 0, &codec_devs[0],
+drivers/mfd/88pm805.c:		dev_err(chip->dev, "Failed to add codec subdev\n");
+drivers/mfd/88pm805.c:		dev_info(chip->dev, "[%s]:Added mfd codec_devs\n", __func__);
+drivers/mfd/88pm805.c:		dev_err(chip->dev, "Failed to initialize 88pm805 devices\n");
+drivers/mfd/88pm805.c:	mfd_remove_devices(chip->dev);
+drivers/mfd/88pm80x.c:	chip->client = client;
+drivers/mfd/88pm80x.c:	chip->regmap = map;
+drivers/mfd/88pm80x.c:	chip->irq = client->irq;
+drivers/mfd/88pm80x.c:	chip->dev = &client->dev;
+drivers/mfd/88pm80x.c:	dev_set_drvdata(chip->dev, chip);
+drivers/mfd/88pm80x.c:	i2c_set_clientdata(chip->client, chip);
+drivers/mfd/88pm80x.c:	ret = regmap_read(chip->regmap, PM80X_CHIP_ID, &val);
+drivers/mfd/88pm80x.c:		dev_err(chip->dev, "Failed to read CHIP ID: %d\n", ret);
+drivers/mfd/88pm80x.c:			chip->type = chip_mapping[i].type;
+drivers/mfd/88pm80x.c:		dev_err(chip->dev,
+drivers/mfd/88pm80x.c:		chip->companion = g_pm80x_chip->client;
+drivers/mfd/88pm80x.c:		g_pm80x_chip->companion = chip->client;
+drivers/mfd/88pm80x.c:	if (g_pm80x_chip->companion)
+drivers/mfd/88pm80x.c:		g_pm80x_chip->companion = NULL;
+drivers/mfd/88pm80x.c:	if (chip && chip->wu_flag)
+drivers/mfd/88pm80x.c:		if (device_may_wakeup(chip->dev))
+drivers/mfd/88pm80x.c:			enable_irq_wake(chip->irq);
+drivers/mfd/88pm80x.c:	if (chip && chip->wu_flag)
+drivers/mfd/88pm80x.c:		if (device_may_wakeup(chip->dev))
+drivers/mfd/88pm80x.c:			disable_irq_wake(chip->irq);
+drivers/mfd/88pm860x-core.c:	i2c = (chip->id == CHIP_PM8607) ? chip->client : chip->companion;
+drivers/mfd/88pm860x-core.c:			handle_nested_irq(chip->irq_base + i);
+drivers/mfd/88pm860x-core.c:	mutex_lock(&chip->irq_lock);
+drivers/mfd/88pm860x-core.c:	i2c = (chip->id == CHIP_PM8607) ? chip->client : chip->companion;
+drivers/mfd/88pm860x-core.c:			dev_err(chip->dev, "wrong IRQ\n");
+drivers/mfd/88pm860x-core.c:	mutex_unlock(&chip->irq_lock);
+drivers/mfd/88pm860x-core.c:	struct i2c_client *i2c = (chip->id == CHIP_PM8607) ?
+drivers/mfd/88pm860x-core.c:		chip->client : chip->companion;
+drivers/mfd/88pm860x-core.c:	chip->irq_mode = 0;
+drivers/mfd/88pm860x-core.c:		chip->irq_mode = 1;
+drivers/mfd/88pm860x-core.c:	if (chip->irq_mode) {
+drivers/mfd/88pm860x-core.c:	mutex_init(&chip->irq_lock);
+drivers/mfd/88pm860x-core.c:	chip->irq_base = irq_alloc_descs(irq_base, 0, nr_irqs, 0);
+drivers/mfd/88pm860x-core.c:	if (chip->irq_base < 0) {
+drivers/mfd/88pm860x-core.c:			chip->irq_base);
+drivers/mfd/88pm860x-core.c:	irq_domain_add_legacy(node, nr_irqs, chip->irq_base, 0,
+drivers/mfd/88pm860x-core.c:	chip->core_irq = i2c->irq;
+drivers/mfd/88pm860x-core.c:	if (!chip->core_irq)
+drivers/mfd/88pm860x-core.c:	ret = request_threaded_irq(chip->core_irq, NULL, pm860x_irq,
+drivers/mfd/88pm860x-core.c:		dev_err(chip->dev, "Failed to request IRQ: %d\n", ret);
+drivers/mfd/88pm860x-core.c:		chip->core_irq = 0;
+drivers/mfd/88pm860x-core.c:	chip->core_irq = 0;
+drivers/mfd/88pm860x-core.c:	if (chip->core_irq)
+drivers/mfd/88pm860x-core.c:		free_irq(chip->core_irq, chip);
+drivers/mfd/88pm860x-core.c:	struct i2c_client *i2c = (chip->id == CHIP_PM8606) ?
+drivers/mfd/88pm860x-core.c:		chip->client : chip->companion;
+drivers/mfd/88pm860x-core.c:	dev_dbg(chip->dev, "%s(B): client=0x%x\n", __func__, client);
+drivers/mfd/88pm860x-core.c:	dev_dbg(chip->dev, "%s(B): vote=0x%x status=%d\n",
+drivers/mfd/88pm860x-core.c:			__func__, chip->osc_vote,
+drivers/mfd/88pm860x-core.c:			chip->osc_status);
+drivers/mfd/88pm860x-core.c:	mutex_lock(&chip->osc_lock);
+drivers/mfd/88pm860x-core.c:	chip->osc_vote |= client;
+drivers/mfd/88pm860x-core.c:	if (chip->osc_status != PM8606_REF_GP_OSC_ON) {
+drivers/mfd/88pm860x-core.c:		chip->osc_status = PM8606_REF_GP_OSC_UNKNOWN;
+drivers/mfd/88pm860x-core.c:		chip->osc_status = PM8606_REF_GP_OSC_ON;
+drivers/mfd/88pm860x-core.c:	mutex_unlock(&chip->osc_lock);
+drivers/mfd/88pm860x-core.c:	dev_dbg(chip->dev, "%s(A): vote=0x%x status=%d ret=%d\n",
+drivers/mfd/88pm860x-core.c:			__func__, chip->osc_vote,
+drivers/mfd/88pm860x-core.c:			chip->osc_status, ret);
+drivers/mfd/88pm860x-core.c:	mutex_unlock(&chip->osc_lock);
+drivers/mfd/88pm860x-core.c:	struct i2c_client *i2c = (chip->id == CHIP_PM8606) ?
+drivers/mfd/88pm860x-core.c:		chip->client : chip->companion;
+drivers/mfd/88pm860x-core.c:	dev_dbg(chip->dev, "%s(B): client=0x%x\n", __func__, client);
+drivers/mfd/88pm860x-core.c:	dev_dbg(chip->dev, "%s(B): vote=0x%x status=%d\n",
+drivers/mfd/88pm860x-core.c:			__func__, chip->osc_vote,
+drivers/mfd/88pm860x-core.c:			chip->osc_status);
+drivers/mfd/88pm860x-core.c:	mutex_lock(&chip->osc_lock);
+drivers/mfd/88pm860x-core.c:	chip->osc_vote &= ~(client);
+drivers/mfd/88pm860x-core.c:	if ((chip->osc_status != PM8606_REF_GP_OSC_OFF) &&
+drivers/mfd/88pm860x-core.c:			(chip->osc_vote == REF_GP_NO_CLIENTS)) {
+drivers/mfd/88pm860x-core.c:		chip->osc_status = PM8606_REF_GP_OSC_UNKNOWN;
+drivers/mfd/88pm860x-core.c:		chip->osc_status = PM8606_REF_GP_OSC_OFF;
+drivers/mfd/88pm860x-core.c:	mutex_unlock(&chip->osc_lock);
+drivers/mfd/88pm860x-core.c:	dev_dbg(chip->dev, "%s(A): vote=0x%x status=%d ret=%d\n",
+drivers/mfd/88pm860x-core.c:			__func__, chip->osc_vote,
+drivers/mfd/88pm860x-core.c:			chip->osc_status, ret);
+drivers/mfd/88pm860x-core.c:	mutex_unlock(&chip->osc_lock);
+drivers/mfd/88pm860x-core.c:	mutex_init(&chip->osc_lock);
+drivers/mfd/88pm860x-core.c:	chip->osc_vote = REF_GP_NO_CLIENTS;
+drivers/mfd/88pm860x-core.c:	chip->osc_status = PM8606_REF_GP_OSC_OFF;
+drivers/mfd/88pm860x-core.c:	ret = mfd_add_devices(chip->dev, 0, bk_devs,
+drivers/mfd/88pm860x-core.c:		dev_err(chip->dev, "Failed to add backlight subdev\n");
+drivers/mfd/88pm860x-core.c:	ret = mfd_add_devices(chip->dev, 0, led_devs,
+drivers/mfd/88pm860x-core.c:		dev_err(chip->dev, "Failed to add led subdev\n");
+drivers/mfd/88pm860x-core.c:	ret = mfd_add_devices(chip->dev, 0, reg_devs,
+drivers/mfd/88pm860x-core.c:		dev_err(chip->dev, "Failed to add regulator subdev\n");
+drivers/mfd/88pm860x-core.c:	ret = mfd_add_devices(chip->dev, 0, &rtc_devs[0],
+drivers/mfd/88pm860x-core.c:			      chip->irq_base, NULL);
+drivers/mfd/88pm860x-core.c:		dev_err(chip->dev, "Failed to add rtc subdev\n");
+drivers/mfd/88pm860x-core.c:	ret = mfd_add_devices(chip->dev, 0, &touch_devs[0],
+drivers/mfd/88pm860x-core.c:			      chip->irq_base, NULL);
+drivers/mfd/88pm860x-core.c:		dev_err(chip->dev, "Failed to add touch subdev\n");
+drivers/mfd/88pm860x-core.c:	ret = mfd_add_devices(chip->dev, 0, &power_devs[0], 1,
+drivers/mfd/88pm860x-core.c:			      &battery_resources[0], chip->irq_base, NULL);
+drivers/mfd/88pm860x-core.c:		dev_err(chip->dev, "Failed to add battery subdev\n");
+drivers/mfd/88pm860x-core.c:	ret = mfd_add_devices(chip->dev, 0, &power_devs[1], 1,
+drivers/mfd/88pm860x-core.c:			      &charger_resources[0], chip->irq_base, NULL);
+drivers/mfd/88pm860x-core.c:		dev_err(chip->dev, "Failed to add charger subdev\n");
+drivers/mfd/88pm860x-core.c:	ret = mfd_add_devices(chip->dev, 0, &power_devs[2], 1,
+drivers/mfd/88pm860x-core.c:			      NULL, chip->irq_base, NULL);
+drivers/mfd/88pm860x-core.c:		dev_err(chip->dev, "Failed to add preg subdev\n");
+drivers/mfd/88pm860x-core.c:		ret = mfd_add_devices(chip->dev, 0, &power_devs[3], 1,
+drivers/mfd/88pm860x-core.c:				      NULL, chip->irq_base, NULL);
+drivers/mfd/88pm860x-core.c:			dev_err(chip->dev, "Failed to add chg-manager subdev\n");
+drivers/mfd/88pm860x-core.c:	ret = mfd_add_devices(chip->dev, 0, &onkey_devs[0],
+drivers/mfd/88pm860x-core.c:			      chip->irq_base, NULL);
+drivers/mfd/88pm860x-core.c:		dev_err(chip->dev, "Failed to add onkey subdev\n");
+drivers/mfd/88pm860x-core.c:	ret = mfd_add_devices(chip->dev, 0, &codec_devs[0],
+drivers/mfd/88pm860x-core.c:		dev_err(chip->dev, "Failed to add codec subdev\n");
+drivers/mfd/88pm860x-core.c:		dev_err(chip->dev, "Failed to read CHIP ID: %d\n", ret);
+drivers/mfd/88pm860x-core.c:		dev_info(chip->dev, "Marvell 88PM8607 (ID: %02x) detected\n",
+drivers/mfd/88pm860x-core.c:		dev_err(chip->dev,
+drivers/mfd/88pm860x-core.c:		dev_err(chip->dev, "Failed to read BUCK3 register: %d\n", ret);
+drivers/mfd/88pm860x-core.c:		chip->buck3_double = 1;
+drivers/mfd/88pm860x-core.c:		dev_err(chip->dev, "Failed to read MISC1 register: %d\n", ret);
+drivers/mfd/88pm860x-core.c:		dev_err(chip->dev, "Failed to access MISC1:%d\n", ret);
+drivers/mfd/88pm860x-core.c:	chip->core_irq = 0;
+drivers/mfd/88pm860x-core.c:	switch (chip->id) {
+drivers/mfd/88pm860x-core.c:		device_8606_init(chip, chip->client, pdata);
+drivers/mfd/88pm860x-core.c:		device_8607_init(chip, chip->client, pdata);
+drivers/mfd/88pm860x-core.c:	if (chip->companion) {
+drivers/mfd/88pm860x-core.c:		switch (chip->id) {
+drivers/mfd/88pm860x-core.c:			device_8606_init(chip, chip->companion, pdata);
+drivers/mfd/88pm860x-core.c:			device_8607_init(chip, chip->companion, pdata);
+drivers/mfd/88pm860x-core.c:	mfd_remove_devices(chip->dev);
+drivers/mfd/88pm860x-core.c:	chip->id = verify_addr(client);
+drivers/mfd/88pm860x-core.c:	chip->regmap = devm_regmap_init_i2c(client, &pm860x_regmap_config);
+drivers/mfd/88pm860x-core.c:	if (IS_ERR(chip->regmap)) {
+drivers/mfd/88pm860x-core.c:		ret = PTR_ERR(chip->regmap);
+drivers/mfd/88pm860x-core.c:	chip->client = client;
+drivers/mfd/88pm860x-core.c:	chip->dev = &client->dev;
+drivers/mfd/88pm860x-core.c:	dev_set_drvdata(chip->dev, chip);
+drivers/mfd/88pm860x-core.c:		chip->companion_addr = pdata->companion_addr;
+drivers/mfd/88pm860x-core.c:		chip->companion = i2c_new_dummy_device(chip->client->adapter,
+drivers/mfd/88pm860x-core.c:						chip->companion_addr);
+drivers/mfd/88pm860x-core.c:		if (IS_ERR(chip->companion)) {
+drivers/mfd/88pm860x-core.c:			return PTR_ERR(chip->companion);
+drivers/mfd/88pm860x-core.c:		chip->regmap_companion = regmap_init_i2c(chip->companion,
+drivers/mfd/88pm860x-core.c:		if (IS_ERR(chip->regmap_companion)) {
+drivers/mfd/88pm860x-core.c:			ret = PTR_ERR(chip->regmap_companion);
+drivers/mfd/88pm860x-core.c:			dev_err(&chip->companion->dev,
+drivers/mfd/88pm860x-core.c:			i2c_unregister_device(chip->companion);
+drivers/mfd/88pm860x-core.c:		i2c_set_clientdata(chip->companion, chip);
+drivers/mfd/88pm860x-core.c:	if (chip->companion) {
+drivers/mfd/88pm860x-core.c:		regmap_exit(chip->regmap_companion);
+drivers/mfd/88pm860x-core.c:		i2c_unregister_device(chip->companion);
+drivers/mfd/88pm860x-core.c:	if (device_may_wakeup(dev) && chip->wakeup_flag)
+drivers/mfd/88pm860x-core.c:		enable_irq_wake(chip->core_irq);
+drivers/mfd/88pm860x-core.c:	if (device_may_wakeup(dev) && chip->wakeup_flag)
+drivers/mfd/88pm860x-core.c:		disable_irq_wake(chip->core_irq);
+drivers/mfd/88pm860x-i2c.c:	struct regmap *map = (i2c == chip->client) ? chip->regmap
+drivers/mfd/88pm860x-i2c.c:				: chip->regmap_companion;
+drivers/mfd/88pm860x-i2c.c:	struct regmap *map = (i2c == chip->client) ? chip->regmap
+drivers/mfd/88pm860x-i2c.c:				: chip->regmap_companion;
+drivers/mfd/88pm860x-i2c.c:	struct regmap *map = (i2c == chip->client) ? chip->regmap
+drivers/mfd/88pm860x-i2c.c:				: chip->regmap_companion;
+drivers/mfd/88pm860x-i2c.c:	struct regmap *map = (i2c == chip->client) ? chip->regmap
+drivers/mfd/88pm860x-i2c.c:				: chip->regmap_companion;
+drivers/mfd/88pm860x-i2c.c:	struct regmap *map = (i2c == chip->client) ? chip->regmap
+drivers/mfd/88pm860x-i2c.c:				: chip->regmap_companion;
+drivers/mfd/ab3100-core.c: * and some basic chip-configuration.
+drivers/mfd/adp5520.c:	mutex_lock(&chip->lock);
+drivers/mfd/adp5520.c:	mutex_unlock(&chip->lock);
+drivers/mfd/adp5520.c:	mutex_lock(&chip->lock);
+drivers/mfd/adp5520.c:	ret = __adp5520_read(chip->client, reg, &reg_val);
+drivers/mfd/adp5520.c:		ret = __adp5520_write(chip->client, reg, reg_val);
+drivers/mfd/adp5520.c:	mutex_unlock(&chip->lock);
+drivers/mfd/adp5520.c:	mutex_lock(&chip->lock);
+drivers/mfd/adp5520.c:	ret = __adp5520_read(chip->client, reg, &reg_val);
+drivers/mfd/adp5520.c:		ret = __adp5520_write(chip->client, reg, reg_val);
+drivers/mfd/adp5520.c:	mutex_unlock(&chip->lock);
+drivers/mfd/adp5520.c:	if (chip->irq) {
+drivers/mfd/adp5520.c:		adp5520_set_bits(chip->dev, ADP5520_INTERRUPT_ENABLE,
+drivers/mfd/adp5520.c:		return blocking_notifier_chain_register(&chip->notifier_list,
+drivers/mfd/adp5520.c:	adp5520_clr_bits(chip->dev, ADP5520_INTERRUPT_ENABLE,
+drivers/mfd/adp5520.c:	return blocking_notifier_chain_unregister(&chip->notifier_list, nb);
+drivers/mfd/adp5520.c:	ret = __adp5520_read(chip->client, ADP5520_MODE_STATUS, &reg_val);
+drivers/mfd/adp5520.c:	blocking_notifier_call_chain(&chip->notifier_list, events, NULL);
+drivers/mfd/adp5520.c:	__adp5520_ack_bits(chip->client, ADP5520_MODE_STATUS, events);
+drivers/mfd/adp5520.c:	return device_for_each_child(chip->dev, NULL, __remove_subdev);
+drivers/mfd/adp5520.c:	chip->client = client;
+drivers/mfd/adp5520.c:	chip->dev = &client->dev;
+drivers/mfd/adp5520.c:	chip->irq = client->irq;
+drivers/mfd/adp5520.c:	chip->id = id->driver_data;
+drivers/mfd/adp5520.c:	mutex_init(&chip->lock);
+drivers/mfd/adp5520.c:	if (chip->irq) {
+drivers/mfd/adp5520.c:		BLOCKING_INIT_NOTIFIER_HEAD(&chip->notifier_list);
+drivers/mfd/adp5520.c:		ret = request_threaded_irq(chip->irq, NULL, adp5520_irq_thread,
+drivers/mfd/adp5520.c:					chip->irq);
+drivers/mfd/adp5520.c:	ret = adp5520_write(chip->dev, ADP5520_MODE_STATUS, ADP5520_nSTNBY);
+drivers/mfd/adp5520.c:		pdev = platform_device_register_data(chip->dev, "adp5520-keys",
+drivers/mfd/adp5520.c:				chip->id, pdata->keys, sizeof(*pdata->keys));
+drivers/mfd/adp5520.c:		pdev = platform_device_register_data(chip->dev, "adp5520-gpio",
+drivers/mfd/adp5520.c:				chip->id, pdata->gpio, sizeof(*pdata->gpio));
+drivers/mfd/adp5520.c:		pdev = platform_device_register_data(chip->dev, "adp5520-led",
+drivers/mfd/adp5520.c:				chip->id, pdata->leds, sizeof(*pdata->leds));
+drivers/mfd/adp5520.c:		pdev = platform_device_register_data(chip->dev,
+drivers/mfd/adp5520.c:						chip->id,
+drivers/mfd/adp5520.c:	if (chip->irq)
+drivers/mfd/adp5520.c:		free_irq(chip->irq, chip);
+drivers/mfd/adp5520.c:	adp5520_read(chip->dev, ADP5520_MODE_STATUS, &chip->mode);
+drivers/mfd/adp5520.c:	chip->mode &= ADP5520_BL_EN | ADP5520_DIM_EN | ADP5520_nSTNBY;
+drivers/mfd/adp5520.c:	adp5520_write(chip->dev, ADP5520_MODE_STATUS, 0);
+drivers/mfd/adp5520.c:	adp5520_write(chip->dev, ADP5520_MODE_STATUS, chip->mode);
+drivers/mfd/asic3.c:	data->chip->irq_ack(data);
+drivers/mfd/da903x.c:	chip->ops->unmask_events(chip, events);
+drivers/mfd/da903x.c:	return blocking_notifier_chain_register(&chip->notifier_list, nb);
+drivers/mfd/da903x.c:	chip->ops->mask_events(chip, events);
+drivers/mfd/da903x.c:	return blocking_notifier_chain_unregister(&chip->notifier_list, nb);
+drivers/mfd/da903x.c:	mutex_lock(&chip->lock);
+drivers/mfd/da903x.c:	ret = __da903x_read(chip->client, reg, &reg_val);
+drivers/mfd/da903x.c:		ret = __da903x_write(chip->client, reg, reg_val);
+drivers/mfd/da903x.c:	mutex_unlock(&chip->lock);
+drivers/mfd/da903x.c:	mutex_lock(&chip->lock);
+drivers/mfd/da903x.c:	ret = __da903x_read(chip->client, reg, &reg_val);
+drivers/mfd/da903x.c:		ret = __da903x_write(chip->client, reg, reg_val);
+drivers/mfd/da903x.c:	mutex_unlock(&chip->lock);
+drivers/mfd/da903x.c:	mutex_lock(&chip->lock);
+drivers/mfd/da903x.c:	ret = __da903x_read(chip->client, reg, &reg_val);
+drivers/mfd/da903x.c:		ret = __da903x_write(chip->client, reg, reg_val);
+drivers/mfd/da903x.c:	mutex_unlock(&chip->lock);
+drivers/mfd/da903x.c:	chip->ops->read_status(chip, &status);
+drivers/mfd/da903x.c:	err = __da903x_read(chip->client, DA9030_CHIP_ID, &chip_id);
+drivers/mfd/da903x.c:	err = __da903x_write(chip->client, DA9030_SYS_CTRL_A, 0xE8);
+drivers/mfd/da903x.c:	dev_info(chip->dev, "DA9030 (CHIP ID: 0x%02x) detected\n", chip_id);
+drivers/mfd/da903x.c:	chip->events_mask &= ~events;
+drivers/mfd/da903x.c:	v[0] = (chip->events_mask & 0xff);
+drivers/mfd/da903x.c:	v[1] = (chip->events_mask >> 8) & 0xff;
+drivers/mfd/da903x.c:	v[2] = (chip->events_mask >> 16) & 0xff;
+drivers/mfd/da903x.c:	return __da903x_writes(chip->client, DA9030_IRQ_MASK_A, 3, v);
+drivers/mfd/da903x.c:	chip->events_mask |= events;
+drivers/mfd/da903x.c:	v[0] = (chip->events_mask & 0xff);
+drivers/mfd/da903x.c:	v[1] = (chip->events_mask >> 8) & 0xff;
+drivers/mfd/da903x.c:	v[2] = (chip->events_mask >> 16) & 0xff;
+drivers/mfd/da903x.c:	return __da903x_writes(chip->client, DA9030_IRQ_MASK_A, 3, v);
+drivers/mfd/da903x.c:	ret = __da903x_reads(chip->client, DA9030_EVENT_A, 3, v);
+drivers/mfd/da903x.c:	return __da903x_read(chip->client, DA9030_STATUS, (uint8_t *)status);
+drivers/mfd/da903x.c:	err = __da903x_read(chip->client, DA9034_CHIP_ID, &chip_id);
+drivers/mfd/da903x.c:	err = __da903x_write(chip->client, DA9034_SYS_CTRL_A, 0xE8);
+drivers/mfd/da903x.c:	__da903x_write(chip->client, 0x10, 0x07);
+drivers/mfd/da903x.c:	__da903x_write(chip->client, 0x11, 0xff);
+drivers/mfd/da903x.c:	__da903x_write(chip->client, 0x12, 0xff);
+drivers/mfd/da903x.c:	__da903x_write(chip->client, DA9034_SYS_CTRL_B, 0x20);
+drivers/mfd/da903x.c:	__da903x_write(chip->client, DA9034_SYS_CTRL_A, 0x60);
+drivers/mfd/da903x.c:	__da903x_write(chip->client, 0x90, 0x01);
+drivers/mfd/da903x.c:	__da903x_write(chip->client, 0xB0, 0x08);
+drivers/mfd/da903x.c:	__da903x_write(chip->client, 0x20, 0x00);
+drivers/mfd/da903x.c:	dev_info(chip->dev, "DA9034 (CHIP ID: 0x%02x) detected\n", chip_id);
+drivers/mfd/da903x.c:	chip->events_mask &= ~events;
+drivers/mfd/da903x.c:	v[0] = (chip->events_mask & 0xff);
+drivers/mfd/da903x.c:	v[1] = (chip->events_mask >> 8) & 0xff;
+drivers/mfd/da903x.c:	v[2] = (chip->events_mask >> 16) & 0xff;
+drivers/mfd/da903x.c:	v[3] = (chip->events_mask >> 24) & 0xff;
+drivers/mfd/da903x.c:	return __da903x_writes(chip->client, DA9034_IRQ_MASK_A, 4, v);
+drivers/mfd/da903x.c:	chip->events_mask |= events;
+drivers/mfd/da903x.c:	v[0] = (chip->events_mask & 0xff);
+drivers/mfd/da903x.c:	v[1] = (chip->events_mask >> 8) & 0xff;
+drivers/mfd/da903x.c:	v[2] = (chip->events_mask >> 16) & 0xff;
+drivers/mfd/da903x.c:	v[3] = (chip->events_mask >> 24) & 0xff;
+drivers/mfd/da903x.c:	return __da903x_writes(chip->client, DA9034_IRQ_MASK_A, 4, v);
+drivers/mfd/da903x.c:	ret = __da903x_reads(chip->client, DA9034_EVENT_A, 4, v);
+drivers/mfd/da903x.c:	ret = __da903x_reads(chip->client, DA9034_STATUS_A, 2, v);
+drivers/mfd/da903x.c:		if (chip->ops->read_events(chip, &events))
+drivers/mfd/da903x.c:		events &= ~chip->events_mask;
+drivers/mfd/da903x.c:				&chip->notifier_list, events, NULL);
+drivers/mfd/da903x.c:	enable_irq(chip->client->irq);
+drivers/mfd/da903x.c:	(void)schedule_work(&chip->irq_work);
+drivers/mfd/da903x.c:	return device_for_each_child(chip->dev, NULL, __remove_subdev);
+drivers/mfd/da903x.c:		pdev->dev.parent = chip->dev;
+drivers/mfd/da903x.c:	chip->client = client;
+drivers/mfd/da903x.c:	chip->dev = &client->dev;
+drivers/mfd/da903x.c:	chip->ops = &da903x_ops[id->driver_data];
+drivers/mfd/da903x.c:	mutex_init(&chip->lock);
+drivers/mfd/da903x.c:	INIT_WORK(&chip->irq_work, da903x_irq_work);
+drivers/mfd/da903x.c:	BLOCKING_INIT_NOTIFIER_HEAD(&chip->notifier_list);
+drivers/mfd/da903x.c:	ret = chip->ops->init_chip(chip);
+drivers/mfd/da903x.c:	chip->events_mask = 0xffffffff;
+drivers/mfd/da903x.c:	chip->ops->mask_events(chip, chip->events_mask);
+drivers/mfd/da903x.c:	chip->ops->read_events(chip, &tmp);
+drivers/mfd/da9062-core.c:	ret = regmap_read(chip->regmap, DA9062AA_FAULT_LOG, &fault_log);
+drivers/mfd/da9062-core.c:			dev_dbg(chip->dev, "Fault log entry detected: TWD_ERROR\n");
+drivers/mfd/da9062-core.c:			dev_dbg(chip->dev, "Fault log entry detected: POR\n");
+drivers/mfd/da9062-core.c:			dev_dbg(chip->dev, "Fault log entry detected: VDD_FAULT\n");
+drivers/mfd/da9062-core.c:			dev_dbg(chip->dev, "Fault log entry detected: VDD_START\n");
+drivers/mfd/da9062-core.c:			dev_dbg(chip->dev, "Fault log entry detected: TEMP_CRIT\n");
+drivers/mfd/da9062-core.c:			dev_dbg(chip->dev, "Fault log entry detected: KEY_RESET\n");
+drivers/mfd/da9062-core.c:			dev_dbg(chip->dev, "Fault log entry detected: NSHUTDOWN\n");
+drivers/mfd/da9062-core.c:			dev_dbg(chip->dev, "Fault log entry detected: WAIT_SHUT\n");
+drivers/mfd/da9062-core.c:		ret = regmap_write(chip->regmap, DA9062AA_FAULT_LOG,
+drivers/mfd/da9062-core.c:	ret = regmap_read(chip->regmap, DA9062AA_DEVICE_ID, &device_id);
+drivers/mfd/da9062-core.c:		dev_err(chip->dev, "Cannot read chip ID.\n");
+drivers/mfd/da9062-core.c:		dev_err(chip->dev, "Invalid device ID: 0x%02x\n", device_id);
+drivers/mfd/da9062-core.c:	ret = regmap_read(chip->regmap, DA9062AA_VARIANT_ID, &variant_id);
+drivers/mfd/da9062-core.c:		dev_err(chip->dev, "Cannot read chip variant id.\n");
+drivers/mfd/da9062-core.c:	dev_info(chip->dev,
+drivers/mfd/da9062-core.c:		dev_err(chip->dev,
+drivers/mfd/da9062-core.c:		chip->chip_type = (uintptr_t)match->data;
+drivers/mfd/da9062-core.c:		chip->chip_type = id->driver_data;
+drivers/mfd/da9062-core.c:	chip->dev = &i2c->dev;
+drivers/mfd/da9062-core.c:		dev_err(chip->dev, "No IRQ configured\n");
+drivers/mfd/da9062-core.c:	switch (chip->chip_type) {
+drivers/mfd/da9062-core.c:		dev_err(chip->dev, "Unrecognised chip type\n");
+drivers/mfd/da9062-core.c:	chip->regmap = devm_regmap_init_i2c(i2c, config);
+drivers/mfd/da9062-core.c:	if (IS_ERR(chip->regmap)) {
+drivers/mfd/da9062-core.c:		ret = PTR_ERR(chip->regmap);
+drivers/mfd/da9062-core.c:		dev_err(chip->dev, "Failed to allocate register map: %d\n",
+drivers/mfd/da9062-core.c:		dev_warn(chip->dev, "Cannot clear fault log\n");
+drivers/mfd/da9062-core.c:	ret = regmap_add_irq_chip(chip->regmap, i2c->irq,
+drivers/mfd/da9062-core.c:			&chip->regmap_irq);
+drivers/mfd/da9062-core.c:		dev_err(chip->dev, "Failed to request IRQ %d: %d\n",
+drivers/mfd/da9062-core.c:	irq_base = regmap_irq_chip_get_base(chip->regmap_irq);
+drivers/mfd/da9062-core.c:	ret = mfd_add_devices(chip->dev, PLATFORM_DEVID_NONE, cell,
+drivers/mfd/da9062-core.c:		dev_err(chip->dev, "Cannot register child devices\n");
+drivers/mfd/da9062-core.c:		regmap_del_irq_chip(i2c->irq, chip->regmap_irq);
+drivers/mfd/da9062-core.c:	mfd_remove_devices(chip->dev);
+drivers/mfd/da9062-core.c:	regmap_del_irq_chip(i2c->irq, chip->regmap_irq);
+drivers/mfd/da9063-core.c:		 "Device detected (chip-ID: 0x%02X, var-ID: 0x%02X)\n",
+drivers/mfd/ezx-pcap.c:	desc->irq_data.chip->irq_ack(&desc->irq_data);
+drivers/mfd/htc-i2cpld.c:	chip->irqs_enabled &= ~(1 << (data->irq - chip->irq_start));
+drivers/mfd/htc-i2cpld.c:	pr_debug("HTCPLD mask %d %04x\n", data->irq, chip->irqs_enabled);
+drivers/mfd/htc-i2cpld.c:	chip->irqs_enabled |= 1 << (data->irq - chip->irq_start);
+drivers/mfd/htc-i2cpld.c:	pr_debug("HTCPLD unmask %d %04x\n", data->irq, chip->irqs_enabled);
+drivers/mfd/htc-i2cpld.c:	chip->flow_type = flags;
+drivers/mfd/htc-i2cpld.c:		if (chip->nirqs == 0)
+drivers/mfd/htc-i2cpld.c:		client = chip->client;
+drivers/mfd/htc-i2cpld.c:		val = i2c_smbus_read_byte_data(client, chip->cache_out);
+drivers/mfd/htc-i2cpld.c:			dev_warn(chip->dev, "Unable to read from chip: %d\n",
+drivers/mfd/htc-i2cpld.c:		spin_lock_irqsave(&chip->lock, flags);
+drivers/mfd/htc-i2cpld.c:		old_val = chip->cache_in;
+drivers/mfd/htc-i2cpld.c:		chip->cache_in = uval;
+drivers/mfd/htc-i2cpld.c:		spin_unlock_irqrestore(&chip->lock, flags);
+drivers/mfd/htc-i2cpld.c:		for (irqpin = 0; irqpin < chip->nirqs; irqpin++) {
+drivers/mfd/htc-i2cpld.c:			unsigned oldb, newb, type = chip->flow_type;
+drivers/mfd/htc-i2cpld.c:			irq = chip->irq_start + irqpin;
+drivers/mfd/htc-i2cpld.c:	if (!strncmp(chip->label, "htcpld-out", 10)) {
+drivers/mfd/htc-i2cpld.c:	} else if (!strncmp(chip->label, "htcpld-in", 9)) {
+drivers/mfd/htc-i2cpld.c:	return (offset < chip->ngpio) ? 0 : -EINVAL;
+drivers/mfd/htc-i2cpld.c:	irq_end = chip->irq_start + chip->nirqs;
+drivers/mfd/htc-i2cpld.c:	for (irq = chip->irq_start; irq < irq_end; irq++) {
+drivers/mfd/htc-i2cpld.c:	chip->client = client;
+drivers/mfd/htc-i2cpld.c:	chip->cache_in = i2c_smbus_read_byte_data(client, chip->cache_out);
+drivers/mfd/htc-i2cpld.c:	i2c_unregister_device(chip->client);
+drivers/mfd/htc-i2cpld.c:	gpio_chip = &(chip->chip_out);
+drivers/mfd/htc-i2cpld.c:	gpio_chip->label           = "htcpld-out";
+drivers/mfd/htc-i2cpld.c:	gpio_chip->parent             = dev;
+drivers/mfd/htc-i2cpld.c:	gpio_chip->owner           = THIS_MODULE;
+drivers/mfd/htc-i2cpld.c:	gpio_chip->get             = htcpld_chip_get;
+drivers/mfd/htc-i2cpld.c:	gpio_chip->set             = htcpld_chip_set;
+drivers/mfd/htc-i2cpld.c:	gpio_chip->direction_input = NULL;
+drivers/mfd/htc-i2cpld.c:	gpio_chip->direction_output = htcpld_direction_output;
+drivers/mfd/htc-i2cpld.c:	gpio_chip->base            = plat_chip_data->gpio_out_base;
+drivers/mfd/htc-i2cpld.c:	gpio_chip->ngpio           = plat_chip_data->num_gpios;
+drivers/mfd/htc-i2cpld.c:	gpio_chip = &(chip->chip_in);
+drivers/mfd/htc-i2cpld.c:	gpio_chip->label           = "htcpld-in";
+drivers/mfd/htc-i2cpld.c:	gpio_chip->parent             = dev;
+drivers/mfd/htc-i2cpld.c:	gpio_chip->owner           = THIS_MODULE;
+drivers/mfd/htc-i2cpld.c:	gpio_chip->get             = htcpld_chip_get;
+drivers/mfd/htc-i2cpld.c:	gpio_chip->set             = NULL;
+drivers/mfd/htc-i2cpld.c:	gpio_chip->direction_input = htcpld_direction_input;
+drivers/mfd/htc-i2cpld.c:	gpio_chip->direction_output = NULL;
+drivers/mfd/htc-i2cpld.c:	gpio_chip->to_irq          = htcpld_chip_to_irq;
+drivers/mfd/htc-i2cpld.c:	gpio_chip->base            = plat_chip_data->gpio_in_base;
+drivers/mfd/htc-i2cpld.c:	gpio_chip->ngpio           = plat_chip_data->num_gpios;
+drivers/mfd/htc-i2cpld.c:	ret = gpiochip_add_data(&(chip->chip_out), chip);
+drivers/mfd/htc-i2cpld.c:	ret = gpiochip_add_data(&(chip->chip_in), chip);
+drivers/mfd/htc-i2cpld.c:		gpiochip_remove(&(chip->chip_out));
+drivers/mfd/intel_soc_pmic_bxtwc.c:			pirq, chip->name, irq);
+drivers/mfd/max77620.c:	ret = regmap_update_bits(chip->rmap, MAX77620_REG_INTENLBT,
+drivers/mfd/max77620.c:		dev_err(chip->dev, "Failed to set GLBLM: %d\n", ret);
+drivers/mfd/max77620.c:	ret = regmap_update_bits(chip->rmap, MAX77620_REG_INTENLBT,
+drivers/mfd/max77620.c:		dev_err(chip->dev, "Failed to reset GLBLM: %d\n", ret);
+drivers/mfd/max77620.c:	switch (chip->chip_id) {
+drivers/mfd/max77620.c:	struct device *dev = chip->dev;
+drivers/mfd/max77620.c:	switch (chip->chip_id) {
+drivers/mfd/max77620.c:		chip->shutdown_fps_period[fps_id] = min(param_val,
+drivers/mfd/max77620.c:				chip->shutdown_fps_period[fps_id]);
+drivers/mfd/max77620.c:		chip->suspend_fps_period[fps_id] = min(param_val,
+drivers/mfd/max77620.c:	if (!chip->sleep_enable && !chip->enable_global_lpm) {
+drivers/mfd/max77620.c:				chip->sleep_enable = true;
+drivers/mfd/max77620.c:				chip->enable_global_lpm = true;
+drivers/mfd/max77620.c:	ret = regmap_update_bits(chip->rmap, MAX77620_REG_FPS_CFG0 + fps_id,
+drivers/mfd/max77620.c:	struct device *dev = chip->dev;
+drivers/mfd/max77620.c:		chip->shutdown_fps_period[fps_id] = -1;
+drivers/mfd/max77620.c:		chip->suspend_fps_period[fps_id] = -1;
+drivers/mfd/max77620.c:	config = chip->enable_global_lpm ? MAX77620_ONOFFCNFG2_SLP_LPM_MSK : 0;
+drivers/mfd/max77620.c:	ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
+drivers/mfd/max77620.c:	if (chip->chip_id == MAX77663)
+drivers/mfd/max77620.c:	ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
+drivers/mfd/max77620.c:	if ((chip->chip_id == MAX20024) && chip->sleep_enable) {
+drivers/mfd/max77620.c:		ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1,
+drivers/mfd/max77620.c:		ret = regmap_read(chip->rmap, i, &val);
+drivers/mfd/max77620.c:			dev_err(chip->dev, "Failed to read CID: %d\n", ret);
+drivers/mfd/max77620.c:		dev_dbg(chip->dev, "CID%d: 0x%02x\n",
+drivers/mfd/max77620.c:	dev_info(chip->dev, "PMIC Version OTP:0x%02X and ES:0x%X\n",
+drivers/mfd/max77620.c:	regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1,
+drivers/mfd/max77620.c:	chip->dev = &client->dev;
+drivers/mfd/max77620.c:	chip->chip_irq = client->irq;
+drivers/mfd/max77620.c:	chip->chip_id = (enum max77620_chip_id)id->driver_data;
+drivers/mfd/max77620.c:	switch (chip->chip_id) {
+drivers/mfd/max77620.c:		dev_err(chip->dev, "ChipID is invalid %d\n", chip->chip_id);
+drivers/mfd/max77620.c:	chip->rmap = devm_regmap_init_i2c(client, rmap_config);
+drivers/mfd/max77620.c:	if (IS_ERR(chip->rmap)) {
+drivers/mfd/max77620.c:		ret = PTR_ERR(chip->rmap);
+drivers/mfd/max77620.c:		dev_err(chip->dev, "Failed to initialise regmap: %d\n", ret);
+drivers/mfd/max77620.c:	ret = devm_regmap_add_irq_chip(chip->dev, chip->rmap, client->irq,
+drivers/mfd/max77620.c:				       &chip->top_irq_data);
+drivers/mfd/max77620.c:		dev_err(chip->dev, "Failed to add regmap irq: %d\n", ret);
+drivers/mfd/max77620.c:	ret =  devm_mfd_add_devices(chip->dev, PLATFORM_DEVID_NONE,
+drivers/mfd/max77620.c:				    regmap_irq_get_domain(chip->top_irq_data));
+drivers/mfd/max77620.c:		dev_err(chip->dev, "Failed to add MFD children: %d\n", ret);
+drivers/mfd/max77620.c:	ret = regmap_update_bits(chip->rmap, MAX77620_REG_FPS_CFG0 + fps_id,
+drivers/mfd/max77620.c:		dev_err(chip->dev, "Failed to update FPS period: %d\n", ret);
+drivers/mfd/max77620.c:		if (chip->suspend_fps_period[fps] < 0)
+drivers/mfd/max77620.c:					      chip->suspend_fps_period[fps]);
+drivers/mfd/max77620.c:	if (chip->chip_id == MAX20024)
+drivers/mfd/max77620.c:	config = (chip->sleep_enable) ? MAX77620_ONOFFCNFG1_SLPEN : 0;
+drivers/mfd/max77620.c:	ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1,
+drivers/mfd/max77620.c:	if (chip->chip_id == MAX77663)
+drivers/mfd/max77620.c:	ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
+drivers/mfd/max77620.c:		if (chip->shutdown_fps_period[fps] < 0)
+drivers/mfd/max77620.c:					      chip->shutdown_fps_period[fps]);
+drivers/mfd/max77620.c:	if (chip->chip_id == MAX20024 || chip->chip_id == MAX77663)
+drivers/mfd/max77620.c:	ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
+drivers/mfd/max8925-core.c:	return &max8925_irqs[irq - chip->irq_base];
+drivers/mfd/max8925-core.c:			i2c = chip->rtc;
+drivers/mfd/max8925-core.c:			i2c = chip->adc;
+drivers/mfd/max8925-core.c:			i2c = chip->i2c;
+drivers/mfd/max8925-core.c:			handle_nested_irq(chip->irq_base + i);
+drivers/mfd/max8925-core.c:			i2c = chip->rtc;
+drivers/mfd/max8925-core.c:			i2c = chip->adc;
+drivers/mfd/max8925-core.c:			i2c = chip->i2c;
+drivers/mfd/max8925-core.c:			handle_nested_irq(chip->irq_base + i);
+drivers/mfd/max8925-core.c:	mutex_lock(&chip->irq_lock);
+drivers/mfd/max8925-core.c:			dev_err(chip->dev, "wrong IRQ\n");
+drivers/mfd/max8925-core.c:		max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ1_MASK,
+drivers/mfd/max8925-core.c:		max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ2_MASK,
+drivers/mfd/max8925-core.c:		max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ1_MASK,
+drivers/mfd/max8925-core.c:		max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ2_MASK,
+drivers/mfd/max8925-core.c:		max8925_reg_write(chip->rtc, MAX8925_RTC_IRQ_MASK, irq_rtc);
+drivers/mfd/max8925-core.c:		max8925_reg_write(chip->adc, MAX8925_TSC_IRQ_MASK, irq_tsc);
+drivers/mfd/max8925-core.c:	mutex_unlock(&chip->irq_lock);
+drivers/mfd/max8925-core.c:	max8925_irqs[data->irq - chip->irq_base].enable
+drivers/mfd/max8925-core.c:		= max8925_irqs[data->irq - chip->irq_base].offs;
+drivers/mfd/max8925-core.c:	max8925_irqs[data->irq - chip->irq_base].enable = 0;
+drivers/mfd/max8925-core.c:	struct device_node *node = chip->dev->of_node;
+drivers/mfd/max8925-core.c:	max8925_reg_read(chip->i2c, MAX8925_CHG_IRQ1);
+drivers/mfd/max8925-core.c:	max8925_reg_read(chip->i2c, MAX8925_CHG_IRQ2);
+drivers/mfd/max8925-core.c:	max8925_reg_read(chip->i2c, MAX8925_ON_OFF_IRQ1);
+drivers/mfd/max8925-core.c:	max8925_reg_read(chip->i2c, MAX8925_ON_OFF_IRQ2);
+drivers/mfd/max8925-core.c:	max8925_reg_read(chip->rtc, MAX8925_RTC_IRQ);
+drivers/mfd/max8925-core.c:	max8925_reg_read(chip->adc, MAX8925_TSC_IRQ);
+drivers/mfd/max8925-core.c:	max8925_reg_write(chip->rtc, MAX8925_ALARM0_CNTL, 0);
+drivers/mfd/max8925-core.c:	max8925_reg_write(chip->rtc, MAX8925_ALARM1_CNTL, 0);
+drivers/mfd/max8925-core.c:	max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ1_MASK, 0xff);
+drivers/mfd/max8925-core.c:	max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ2_MASK, 0xff);
+drivers/mfd/max8925-core.c:	max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ1_MASK, 0xff);
+drivers/mfd/max8925-core.c:	max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ2_MASK, 0xff);
+drivers/mfd/max8925-core.c:	max8925_reg_write(chip->rtc, MAX8925_RTC_IRQ_MASK, 0xff);
+drivers/mfd/max8925-core.c:	mutex_init(&chip->irq_lock);
+drivers/mfd/max8925-core.c:	chip->irq_base = irq_alloc_descs(-1, 0, MAX8925_NR_IRQS, 0);
+drivers/mfd/max8925-core.c:	if (chip->irq_base < 0) {
+drivers/mfd/max8925-core.c:		dev_err(chip->dev, "Failed to allocate interrupts, ret:%d\n",
+drivers/mfd/max8925-core.c:			chip->irq_base);
+drivers/mfd/max8925-core.c:	irq_domain_add_legacy(node, MAX8925_NR_IRQS, chip->irq_base, 0,
+drivers/mfd/max8925-core.c:	chip->core_irq = irq;
+drivers/mfd/max8925-core.c:	if (!chip->core_irq)
+drivers/mfd/max8925-core.c:		dev_err(chip->dev, "Failed to request core IRQ: %d\n", ret);
+drivers/mfd/max8925-core.c:		chip->core_irq = 0;
+drivers/mfd/max8925-core.c:	max8925_reg_write(chip->adc, MAX8925_TSC_IRQ_MASK, 0x0f);
+drivers/mfd/max8925-core.c:		dev_warn(chip->dev, "No interrupt support on TSC IRQ\n");
+drivers/mfd/max8925-core.c:	chip->tsc_irq = pdata->tsc_irq;
+drivers/mfd/max8925-core.c:	ret = request_threaded_irq(chip->tsc_irq, NULL, max8925_tsc_irq,
+drivers/mfd/max8925-core.c:		dev_err(chip->dev, "Failed to request TSC IRQ: %d\n", ret);
+drivers/mfd/max8925-core.c:		chip->tsc_irq = 0;
+drivers/mfd/max8925-core.c:	ret = mfd_add_devices(chip->dev, 0, reg_devs, ARRAY_SIZE(reg_devs),
+drivers/mfd/max8925-core.c:		dev_err(chip->dev, "Failed to add regulator subdev\n");
+drivers/mfd/max8925-core.c:	max8925_irq_init(chip, chip->i2c->irq, pdata);
+drivers/mfd/max8925-core.c:		max8925_set_bits(chip->i2c, MAX8925_RESET_CNFG, 1, 1);
+drivers/mfd/max8925-core.c:		max8925_set_bits(chip->adc, MAX8925_TSC_CNFG1, 3, 2);
+drivers/mfd/max8925-core.c:			ret = max8925_reg_read(chip->adc, MAX8925_TSC_IRQ);
+drivers/mfd/max8925-core.c:		max8925_set_bits(chip->adc, MAX8925_ADC_SCHED, 3, 2);
+drivers/mfd/max8925-core.c:	max8925_set_bits(chip->rtc, MAX8925_MPL_CNTL, 1 << 4, 1 << 4);
+drivers/mfd/max8925-core.c:	ret = mfd_add_devices(chip->dev, 0, &rtc_devs[0],
+drivers/mfd/max8925-core.c:			      NULL, chip->irq_base, NULL);
+drivers/mfd/max8925-core.c:		dev_err(chip->dev, "Failed to add rtc subdev\n");
+drivers/mfd/max8925-core.c:	ret = mfd_add_devices(chip->dev, 0, &onkey_devs[0],
+drivers/mfd/max8925-core.c:			      NULL, chip->irq_base, NULL);
+drivers/mfd/max8925-core.c:		dev_err(chip->dev, "Failed to add onkey subdev\n");
+drivers/mfd/max8925-core.c:	ret = mfd_add_devices(chip->dev, 0, bk_devs, ARRAY_SIZE(bk_devs),
+drivers/mfd/max8925-core.c:		dev_err(chip->dev, "Failed to add backlight subdev\n");
+drivers/mfd/max8925-core.c:	ret = mfd_add_devices(chip->dev, 0, &power_devs[0],
+drivers/mfd/max8925-core.c:		dev_err(chip->dev,
+drivers/mfd/max8925-core.c:		ret = mfd_add_devices(chip->dev, 0, &touch_devs[0],
+drivers/mfd/max8925-core.c:				      NULL, chip->tsc_irq, NULL);
+drivers/mfd/max8925-core.c:			dev_err(chip->dev, "Failed to add touch subdev\n");
+drivers/mfd/max8925-core.c:	mfd_remove_devices(chip->dev);
+drivers/mfd/max8925-core.c:	if (chip->core_irq)
+drivers/mfd/max8925-core.c:		free_irq(chip->core_irq, chip);
+drivers/mfd/max8925-core.c:	if (chip->tsc_irq)
+drivers/mfd/max8925-core.c:		free_irq(chip->tsc_irq, chip);
+drivers/mfd/max8925-core.c:	mfd_remove_devices(chip->dev);
+drivers/mfd/max8925-i2c.c:	mutex_lock(&chip->io_lock);
+drivers/mfd/max8925-i2c.c:	mutex_unlock(&chip->io_lock);
+drivers/mfd/max8925-i2c.c:	mutex_lock(&chip->io_lock);
+drivers/mfd/max8925-i2c.c:	mutex_unlock(&chip->io_lock);
+drivers/mfd/max8925-i2c.c:	mutex_lock(&chip->io_lock);
+drivers/mfd/max8925-i2c.c:	mutex_unlock(&chip->io_lock);
+drivers/mfd/max8925-i2c.c:	mutex_lock(&chip->io_lock);
+drivers/mfd/max8925-i2c.c:	mutex_unlock(&chip->io_lock);
+drivers/mfd/max8925-i2c.c:	mutex_lock(&chip->io_lock);
+drivers/mfd/max8925-i2c.c:	mutex_unlock(&chip->io_lock);
+drivers/mfd/max8925-i2c.c:	chip->i2c = client;
+drivers/mfd/max8925-i2c.c:	chip->dev = &client->dev;
+drivers/mfd/max8925-i2c.c:	dev_set_drvdata(chip->dev, chip);
+drivers/mfd/max8925-i2c.c:	mutex_init(&chip->io_lock);
+drivers/mfd/max8925-i2c.c:	chip->rtc = i2c_new_dummy_device(chip->i2c->adapter, RTC_I2C_ADDR);
+drivers/mfd/max8925-i2c.c:	if (IS_ERR(chip->rtc)) {
+drivers/mfd/max8925-i2c.c:		dev_err(chip->dev, "Failed to allocate I2C device for RTC\n");
+drivers/mfd/max8925-i2c.c:		return PTR_ERR(chip->rtc);
+drivers/mfd/max8925-i2c.c:	i2c_set_clientdata(chip->rtc, chip);
+drivers/mfd/max8925-i2c.c:	chip->adc = i2c_new_dummy_device(chip->i2c->adapter, ADC_I2C_ADDR);
+drivers/mfd/max8925-i2c.c:	if (IS_ERR(chip->adc)) {
+drivers/mfd/max8925-i2c.c:		dev_err(chip->dev, "Failed to allocate I2C device for ADC\n");
+drivers/mfd/max8925-i2c.c:		i2c_unregister_device(chip->rtc);
+drivers/mfd/max8925-i2c.c:		return PTR_ERR(chip->adc);
+drivers/mfd/max8925-i2c.c:	i2c_set_clientdata(chip->adc, chip);
+drivers/mfd/max8925-i2c.c:	i2c_unregister_device(chip->adc);
+drivers/mfd/max8925-i2c.c:	i2c_unregister_device(chip->rtc);
+drivers/mfd/max8925-i2c.c:	if (device_may_wakeup(dev) && chip->wakeup_flag)
+drivers/mfd/max8925-i2c.c:		enable_irq_wake(chip->core_irq);
+drivers/mfd/max8925-i2c.c:	if (device_may_wakeup(dev) && chip->wakeup_flag)
+drivers/mfd/max8925-i2c.c:		disable_irq_wake(chip->core_irq);
+drivers/mfd/motorola-cpcap.c:	chip->irqs = &cpcap->irqs[irq_start];
+drivers/mfd/motorola-cpcap.c:	chip->num_irqs = nr_irqs;
+drivers/mfd/motorola-cpcap.c:	chip->irq_drv_data = cpcap;
+drivers/mfd/mt6397-core.c:	regmap_write(chip->regmap, chip->int_con[0], chip->wake_mask[0]);
+drivers/mfd/mt6397-core.c:	regmap_write(chip->regmap, chip->int_con[1], chip->wake_mask[1]);
+drivers/mfd/mt6397-core.c:	enable_irq_wake(chip->irq);
+drivers/mfd/mt6397-core.c:	regmap_write(chip->regmap, chip->int_con[0], chip->irq_masks_cur[0]);
+drivers/mfd/mt6397-core.c:	regmap_write(chip->regmap, chip->int_con[1], chip->irq_masks_cur[1]);
+drivers/mfd/mt6397-core.c:	disable_irq_wake(chip->irq);
+drivers/mfd/mt6397-irq.c:	mutex_init(&chip->irqlock);
+drivers/mfd/mt6397-irq.c:	switch (chip->chip_id) {
+drivers/mfd/mt6397-irq.c:		chip->int_con[0] = MT6323_INT_CON0;
+drivers/mfd/mt6397-irq.c:		chip->int_con[1] = MT6323_INT_CON1;
+drivers/mfd/mt6397-irq.c:		chip->int_status[0] = MT6323_INT_STATUS0;
+drivers/mfd/mt6397-irq.c:		chip->int_status[1] = MT6323_INT_STATUS1;
+drivers/mfd/mt6397-irq.c:		chip->int_con[0] = MT6397_INT_CON0;
+drivers/mfd/mt6397-irq.c:		chip->int_con[1] = MT6397_INT_CON1;
+drivers/mfd/mt6397-irq.c:		chip->int_status[0] = MT6397_INT_STATUS0;
+drivers/mfd/mt6397-irq.c:		chip->int_status[1] = MT6397_INT_STATUS1;
+drivers/mfd/mt6397-irq.c:		dev_err(chip->dev, "unsupported chip: 0x%x\n", chip->chip_id);
+drivers/mfd/mt6397-irq.c:	regmap_write(chip->regmap, chip->int_con[0], 0x0);
+drivers/mfd/mt6397-irq.c:	regmap_write(chip->regmap, chip->int_con[1], 0x0);
+drivers/mfd/mt6397-irq.c:	chip->irq_domain = irq_domain_add_linear(chip->dev->of_node,
+drivers/mfd/mt6397-irq.c:	if (!chip->irq_domain) {
+drivers/mfd/mt6397-irq.c:		dev_err(chip->dev, "could not create irq domain\n");
+drivers/mfd/mt6397-irq.c:	ret = devm_request_threaded_irq(chip->dev, chip->irq, NULL,
+drivers/mfd/mt6397-irq.c:		dev_err(chip->dev, "failed to register irq=%d; err: %d\n",
+drivers/mfd/mt6397-irq.c:			chip->irq, ret);
+drivers/mfd/qcom-pm8xxx.c:	spin_lock(&chip->pm_irq_lock);
+drivers/mfd/qcom-pm8xxx.c:	rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
+drivers/mfd/qcom-pm8xxx.c:	rc = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_IT_STATUS, ip);
+drivers/mfd/qcom-pm8xxx.c:	spin_unlock(&chip->pm_irq_lock);
+drivers/mfd/qcom-pm8xxx.c:	spin_lock(&chip->pm_irq_lock);
+drivers/mfd/qcom-pm8xxx.c:	rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
+drivers/mfd/qcom-pm8xxx.c:	rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_CONFIG, cp);
+drivers/mfd/qcom-pm8xxx.c:	spin_unlock(&chip->pm_irq_lock);
+drivers/mfd/qcom-pm8xxx.c:			irq = irq_find_mapping(chip->irqdomain, pmirq);
+drivers/mfd/qcom-pm8xxx.c:	ret = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_M_STATUS1 + master,
+drivers/mfd/qcom-pm8xxx.c:	ret = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_ROOT, &root);
+drivers/mfd/qcom-pm8xxx.c:	for (i = 0; i < chip->num_masters; i++)
+drivers/mfd/qcom-pm8xxx.c:	ret = regmap_read(chip->regmap,
+drivers/mfd/qcom-pm8xxx.c:			irq = irq_find_mapping(chip->irqdomain, pmirq);
+drivers/mfd/qcom-pm8xxx.c:	ret = regmap_read(chip->regmap,
+drivers/mfd/qcom-pm8xxx.c:	ret = regmap_read(chip->regmap,
+drivers/mfd/qcom-pm8xxx.c:	config = chip->config[pmirq] | PM_IRQF_MASK_ALL | PM_IRQF_CLR;
+drivers/mfd/qcom-pm8xxx.c:	config = chip->config[pmirq];
+drivers/mfd/qcom-pm8xxx.c:	chip->config[pmirq] = (irq_bit << PM_IRQF_BITS_SHIFT)
+drivers/mfd/qcom-pm8xxx.c:			chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
+drivers/mfd/qcom-pm8xxx.c:			chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
+drivers/mfd/qcom-pm8xxx.c:		chip->config[pmirq] |= PM_IRQF_LVL_SEL;
+drivers/mfd/qcom-pm8xxx.c:			chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
+drivers/mfd/qcom-pm8xxx.c:			chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
+drivers/mfd/qcom-pm8xxx.c:	config = chip->config[pmirq] | PM_IRQF_CLR;
+drivers/mfd/qcom-pm8xxx.c:	spin_lock(&chip->pm_irq_lock);
+drivers/mfd/qcom-pm8xxx.c:	rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, block);
+drivers/mfd/qcom-pm8xxx.c:	rc = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_RT_STATUS, &bits);
+drivers/mfd/qcom-pm8xxx.c:	spin_unlock(&chip->pm_irq_lock);
+drivers/mfd/qcom-pm8xxx.c:	irq_domain_set_info(domain, irq, hwirq, chip->pm_irq_data->irq_chip,
+drivers/mfd/qcom-pm8xxx.c:	rc = regmap_update_bits(chip->regmap,
+drivers/mfd/qcom-pm8xxx.c:	rc = regmap_update_bits(chip->regmap,
+drivers/mfd/qcom-pm8xxx.c:	rc = regmap_update_bits(chip->regmap,
+drivers/mfd/qcom-pm8xxx.c:	rc = regmap_read(chip->regmap,
+drivers/mfd/qcom-pm8xxx.c:	chip->regmap = regmap;
+drivers/mfd/qcom-pm8xxx.c:	chip->num_blocks = DIV_ROUND_UP(data->num_irqs, 8);
+drivers/mfd/qcom-pm8xxx.c:	chip->num_masters = DIV_ROUND_UP(chip->num_blocks, 8);
+drivers/mfd/qcom-pm8xxx.c:	chip->pm_irq_data = data;
+drivers/mfd/qcom-pm8xxx.c:	spin_lock_init(&chip->pm_irq_lock);
+drivers/mfd/qcom-pm8xxx.c:	chip->irqdomain = irq_domain_add_linear(pdev->dev.of_node,
+drivers/mfd/qcom-pm8xxx.c:	if (!chip->irqdomain)
+drivers/mfd/qcom-pm8xxx.c:		irq_domain_remove(chip->irqdomain);
+drivers/mfd/qcom-pm8xxx.c:	irq_domain_remove(chip->irqdomain);
+drivers/mfd/retu-mfd.c:	ret = retu_write(rdev, rdat->irq_chip->mask_base, 0xffff);
+drivers/mfd/sm501.c:	if (smc501_readl(smchip->control) & bit) {
+drivers/mfd/sm501.c:		dev_info(sm501_gpio_to_dev(smchip->ourgpio)->dev,
+drivers/mfd/sm501.c:		ctrl = smc501_readl(smchip->control);
+drivers/mfd/sm501.c:		smc501_writel(ctrl, smchip->control);
+drivers/mfd/sm501.c:		sm501_sync_regs(sm501_gpio_to_dev(smchip->ourgpio));
+drivers/mfd/sm501.c:	struct sm501_gpio *smgpio = smchip->ourgpio;
+drivers/mfd/sm501.c:	void __iomem *regs = smchip->regbase;
+drivers/mfd/sm501.c:	struct sm501_gpio *smgpio = smchip->ourgpio;
+drivers/mfd/sm501.c:	void __iomem *regs = smchip->regbase;
+drivers/mfd/sm501.c:	struct sm501_gpio *smgpio = smchip->ourgpio;
+drivers/mfd/sm501.c:	void __iomem *regs = smchip->regbase;
+drivers/mfd/sm501.c:	struct gpio_chip *gchip = &chip->gpio;
+drivers/mfd/sm501.c:	chip->gpio = gpio_chip_template;
+drivers/mfd/sm501.c:		chip->regbase = gpio->regs + SM501_GPIO_DATA_HIGH;
+drivers/mfd/sm501.c:		chip->control = sm->regs + SM501_GPIO63_32_CONTROL;
+drivers/mfd/sm501.c:		gchip->label  = "SM501-HIGH";
+drivers/mfd/sm501.c:		chip->regbase = gpio->regs + SM501_GPIO_DATA_LOW;
+drivers/mfd/sm501.c:		chip->control = sm->regs + SM501_GPIO31_0_CONTROL;
+drivers/mfd/sm501.c:		gchip->label  = "SM501-LOW";
+drivers/mfd/sm501.c:	gchip->base   = base;
+drivers/mfd/sm501.c:	chip->ourgpio = gpio;
+drivers/mfd/sm501.c:	/* Create a gpiod lookup using gpiochip-local offsets */
+drivers/mfd/vexpress-sysreg.c:	mmc_gpio_chip->ngpio = 2;
+drivers/misc/apds990x.c:	struct i2c_client *client = chip->client;
+drivers/misc/apds990x.c:	struct i2c_client *client = chip->client;
+drivers/misc/apds990x.c:	struct i2c_client *client = chip->client;
+drivers/misc/apds990x.c:	struct i2c_client *client = chip->client;
+drivers/misc/apds990x.c:	if (chip->prox_en)
+drivers/misc/apds990x.c:	lux = lux * (APDS_CALIB_SCALER / 4) / (chip->lux_calib / 4);
+drivers/misc/apds990x.c:	cpl = ((u32)chip->atime * (u32)again[chip->again_next] *
+drivers/misc/apds990x.c:		APDS_PARAM_SCALE * 64) / (chip->cf.ga * chip->cf.df);
+drivers/misc/apds990x.c:	ir = (u32)chip->lux_ir * (u32)again[chip->again_next] /
+drivers/misc/apds990x.c:		(u32)again[chip->again_meas];
+drivers/misc/apds990x.c:	if (chip->lux_clear * APDS_PARAM_SCALE >=
+drivers/misc/apds990x.c:		chip->rcf.afactor * chip->lux_ir)
+drivers/misc/apds990x.c:		thres = (chip->rcf.cf1 * thres + chip->rcf.irf1 * ir) /
+drivers/misc/apds990x.c:		thres = (chip->rcf.cf2 * thres + chip->rcf.irf2 * ir) /
+drivers/misc/apds990x.c:	if (thres >= chip->a_max_result)
+drivers/misc/apds990x.c:		thres = chip->a_max_result - 1;
+drivers/misc/apds990x.c:	chip->atime = time_ms;
+drivers/misc/apds990x.c:	chip->a_max_result = (u16)(256 - reg_value) * APDS990X_TIME_TO_ADC;
+drivers/misc/apds990x.c:	if (pm_runtime_suspended(&chip->client->dev))
+drivers/misc/apds990x.c:	if (data < chip->prox_thres) {
+drivers/misc/apds990x.c:		hi = chip->prox_thres;
+drivers/misc/apds990x.c:		lo = chip->prox_thres - APDS_PROX_HYSTERESIS;
+drivers/misc/apds990x.c:		if (chip->prox_continuous_mode)
+drivers/misc/apds990x.c:			hi = chip->prox_thres;
+drivers/misc/apds990x.c:	if (pm_runtime_suspended(&chip->client->dev))
+drivers/misc/apds990x.c:			apds990x_lux_to_threshold(chip, chip->lux_thres_lo));
+drivers/misc/apds990x.c:			apds990x_lux_to_threshold(chip, chip->lux_thres_hi));
+drivers/misc/apds990x.c:	int curr_again = chip->again_meas;
+drivers/misc/apds990x.c:	int next_again = chip->again_meas;
+drivers/misc/apds990x.c:	if (chip->lux_clear == chip->a_max_result)
+drivers/misc/apds990x.c:	else if (chip->lux_clear > chip->a_max_result / 2)
+drivers/misc/apds990x.c:	else if (chip->lux_clear < APDS_LUX_GAIN_LO_LIMIT_STRICT)
+drivers/misc/apds990x.c:	else if (chip->lux_clear < APDS_LUX_GAIN_LO_LIMIT)
+drivers/misc/apds990x.c:	if (chip->lux_clear == chip->a_max_result)
+drivers/misc/apds990x.c:		chip->lux_clear < APDS_LUX_GAIN_LO_LIMIT_STRICT)
+drivers/misc/apds990x.c:	chip->again_next = next_again;
+drivers/misc/apds990x.c:			(chip->pdrive << 6) |
+drivers/misc/apds990x.c:			(chip->pdiode << 4) |
+drivers/misc/apds990x.c:			(chip->pgain << 2) |
+drivers/misc/apds990x.c:			(chip->again_next << 0));
+drivers/misc/apds990x.c:	iac1 = (chip->cf.cf1 * clear - chip->cf.irf1 * ir) / APDS_PARAM_SCALE;
+drivers/misc/apds990x.c:	iac2 = (chip->cf.cf2 * clear - chip->cf.irf2 * ir) / APDS_PARAM_SCALE;
+drivers/misc/apds990x.c:	lpc = APDS990X_LUX_OUTPUT_SCALE * (chip->cf.df * chip->cf.ga) /
+drivers/misc/apds990x.c:		(u32)(again[chip->again_meas] * (u32)chip->atime);
+drivers/misc/apds990x.c:	struct i2c_client *client = chip->client;
+drivers/misc/apds990x.c:	mutex_lock(&chip->mutex);
+drivers/misc/apds990x.c:	if (!pm_runtime_suspended(&chip->client->dev)) {
+drivers/misc/apds990x.c:					&chip->lux_clear);
+drivers/misc/apds990x.c:					&chip->lux_ir);
+drivers/misc/apds990x.c:			chip->again_meas = chip->again_next;
+drivers/misc/apds990x.c:			chip->lux_raw = apds990x_get_lux(chip,
+drivers/misc/apds990x.c:							chip->lux_clear,
+drivers/misc/apds990x.c:							chip->lux_ir);
+drivers/misc/apds990x.c:				chip->lux = chip->lux_raw;
+drivers/misc/apds990x.c:				chip->lux_wait_fresh_res = false;
+drivers/misc/apds990x.c:				wake_up(&chip->wait);
+drivers/misc/apds990x.c:				sysfs_notify(&chip->client->dev.kobj,
+drivers/misc/apds990x.c:		if ((status & APDS990X_ST_PINT) && chip->prox_en) {
+drivers/misc/apds990x.c:			if (chip->again_meas == 0 &&
+drivers/misc/apds990x.c:				clr_ch == chip->a_max_result)
+drivers/misc/apds990x.c:				chip->prox_data = 0;
+drivers/misc/apds990x.c:						&chip->prox_data);
+drivers/misc/apds990x.c:			apds990x_refresh_pthres(chip, chip->prox_data);
+drivers/misc/apds990x.c:			if (chip->prox_data < chip->prox_thres)
+drivers/misc/apds990x.c:				chip->prox_data = 0;
+drivers/misc/apds990x.c:			else if (!chip->prox_continuous_mode)
+drivers/misc/apds990x.c:				chip->prox_data = APDS_PROX_RANGE;
+drivers/misc/apds990x.c:			sysfs_notify(&chip->client->dev.kobj,
+drivers/misc/apds990x.c:	mutex_unlock(&chip->mutex);
+drivers/misc/apds990x.c:			(chip->lux_persistence << APDS990X_APERS_SHIFT) |
+drivers/misc/apds990x.c:			(chip->prox_persistence << APDS990X_PPERS_SHIFT));
+drivers/misc/apds990x.c:	apds990x_write_byte(chip, APDS990X_PPCOUNT, chip->pdata->ppcount);
+drivers/misc/apds990x.c:	chip->again_meas = 1;
+drivers/misc/apds990x.c:	chip->again_next = 1;
+drivers/misc/apds990x.c:			(chip->pdrive << 6) |
+drivers/misc/apds990x.c:			(chip->pdiode << 4) |
+drivers/misc/apds990x.c:			(chip->pgain << 2) |
+drivers/misc/apds990x.c:			(chip->again_next << 0));
+drivers/misc/apds990x.c:	struct i2c_client *client = chip->client;
+drivers/misc/apds990x.c:	ret = apds990x_read_byte(chip, APDS990X_REV, &chip->revision);
+drivers/misc/apds990x.c:		snprintf(chip->chipname, sizeof(chip->chipname), "APDS-990x");
+drivers/misc/apds990x.c:	int err	 = regulator_bulk_enable(ARRAY_SIZE(chip->regs),
+drivers/misc/apds990x.c:					chip->regs);
+drivers/misc/apds990x.c:	chip->prox_data = 0;
+drivers/misc/apds990x.c:	regulator_bulk_disable(ARRAY_SIZE(chip->regs), chip->regs);
+drivers/misc/apds990x.c:	timeout = wait_event_interruptible_timeout(chip->wait,
+drivers/misc/apds990x.c:						!chip->lux_wait_fresh_res,
+drivers/misc/apds990x.c:	mutex_lock(&chip->mutex);
+drivers/misc/apds990x.c:	result = (chip->lux * chip->lux_calib) / APDS_CALIB_SCALER;
+drivers/misc/apds990x.c:	mutex_unlock(&chip->mutex);
+drivers/misc/apds990x.c:	return sprintf(buf, "%u\n", chip->lux_calib);
+drivers/misc/apds990x.c:	chip->lux_calib = value;
+drivers/misc/apds990x.c:	return sprintf(buf, "%d\n", chip->arate);
+drivers/misc/apds990x.c:	chip->lux_persistence = apersis[i];
+drivers/misc/apds990x.c:	chip->arate = arates_hz[i];
+drivers/misc/apds990x.c:	if (pm_runtime_suspended(&chip->client->dev))
+drivers/misc/apds990x.c:			(chip->lux_persistence << APDS990X_APERS_SHIFT) |
+drivers/misc/apds990x.c:			(chip->prox_persistence << APDS990X_PPERS_SHIFT));
+drivers/misc/apds990x.c:	mutex_lock(&chip->mutex);
+drivers/misc/apds990x.c:	mutex_unlock(&chip->mutex);
+drivers/misc/apds990x.c:	if (pm_runtime_suspended(dev) || !chip->prox_en)
+drivers/misc/apds990x.c:	mutex_lock(&chip->mutex);
+drivers/misc/apds990x.c:	ret = sprintf(buf, "%d\n", chip->prox_data);
+drivers/misc/apds990x.c:	mutex_unlock(&chip->mutex);
+drivers/misc/apds990x.c:	return sprintf(buf, "%d\n", chip->prox_en);
+drivers/misc/apds990x.c:	mutex_lock(&chip->mutex);
+drivers/misc/apds990x.c:	if (!chip->prox_en)
+drivers/misc/apds990x.c:		chip->prox_data = 0;
+drivers/misc/apds990x.c:		chip->prox_en++;
+drivers/misc/apds990x.c:	else if (chip->prox_en > 0)
+drivers/misc/apds990x.c:		chip->prox_en--;
+drivers/misc/apds990x.c:	mutex_unlock(&chip->mutex);
+drivers/misc/apds990x.c:		reporting_modes[!!chip->prox_continuous_mode]);
+drivers/misc/apds990x.c:	chip->prox_continuous_mode = ret;
+drivers/misc/apds990x.c:	return sprintf(buf, "%d\n", chip->lux_thres_hi);
+drivers/misc/apds990x.c:	return sprintf(buf, "%d\n", chip->lux_thres_lo);
+drivers/misc/apds990x.c:	mutex_lock(&chip->mutex);
+drivers/misc/apds990x.c:	if (!chip->lux_wait_fresh_res)
+drivers/misc/apds990x.c:	mutex_unlock(&chip->mutex);
+drivers/misc/apds990x.c:	int ret = apds990x_set_lux_thresh(chip, &chip->lux_thres_hi, buf);
+drivers/misc/apds990x.c:	int ret = apds990x_set_lux_thresh(chip, &chip->lux_thres_lo, buf);
+drivers/misc/apds990x.c:	return sprintf(buf, "%d\n", chip->prox_thres);
+drivers/misc/apds990x.c:	mutex_lock(&chip->mutex);
+drivers/misc/apds990x.c:	chip->prox_thres = value;
+drivers/misc/apds990x.c:	mutex_unlock(&chip->mutex);
+drivers/misc/apds990x.c:		mutex_lock(&chip->mutex);
+drivers/misc/apds990x.c:		chip->lux_wait_fresh_res = true;
+drivers/misc/apds990x.c:		mutex_unlock(&chip->mutex);
+drivers/misc/apds990x.c:	return sprintf(buf, "%s %d\n", chip->chipname, chip->revision);
+drivers/misc/apds990x.c:	chip->client  = client;
+drivers/misc/apds990x.c:	init_waitqueue_head(&chip->wait);
+drivers/misc/apds990x.c:	mutex_init(&chip->mutex);
+drivers/misc/apds990x.c:	chip->pdata	= client->dev.platform_data;
+drivers/misc/apds990x.c:	if (chip->pdata == NULL) {
+drivers/misc/apds990x.c:	if (chip->pdata->cf.ga == 0) {
+drivers/misc/apds990x.c:		chip->cf.ga = 1966; /* 0.48 * APDS_PARAM_SCALE */
+drivers/misc/apds990x.c:		chip->cf.cf1 = 4096; /* 1.00 * APDS_PARAM_SCALE */
+drivers/misc/apds990x.c:		chip->cf.irf1 = 9134; /* 2.23 * APDS_PARAM_SCALE */
+drivers/misc/apds990x.c:		chip->cf.cf2 = 2867; /* 0.70 * APDS_PARAM_SCALE */
+drivers/misc/apds990x.c:		chip->cf.irf2 = 5816; /* 1.42 * APDS_PARAM_SCALE */
+drivers/misc/apds990x.c:		chip->cf.df = 52;
+drivers/misc/apds990x.c:		chip->cf = chip->pdata->cf;
+drivers/misc/apds990x.c:	chip->rcf.afactor =
+drivers/misc/apds990x.c:		(chip->cf.irf1 - chip->cf.irf2) * APDS_PARAM_SCALE /
+drivers/misc/apds990x.c:		(chip->cf.cf1 - chip->cf.cf2);
+drivers/misc/apds990x.c:	chip->rcf.cf1 = APDS_PARAM_SCALE * APDS_PARAM_SCALE /
+drivers/misc/apds990x.c:		chip->cf.cf1;
+drivers/misc/apds990x.c:	chip->rcf.irf1 = chip->cf.irf1 * APDS_PARAM_SCALE /
+drivers/misc/apds990x.c:		chip->cf.cf1;
+drivers/misc/apds990x.c:	chip->rcf.cf2 = APDS_PARAM_SCALE * APDS_PARAM_SCALE /
+drivers/misc/apds990x.c:		chip->cf.cf2;
+drivers/misc/apds990x.c:	chip->rcf.irf2 = chip->cf.irf2 * APDS_PARAM_SCALE /
+drivers/misc/apds990x.c:		chip->cf.cf2;
+drivers/misc/apds990x.c:	chip->lux_thres_hi = APDS_LUX_DEF_THRES_HI;
+drivers/misc/apds990x.c:	chip->lux_thres_lo = APDS_LUX_DEF_THRES_LO;
+drivers/misc/apds990x.c:	chip->lux_calib = APDS_LUX_NEUTRAL_CALIB_VALUE;
+drivers/misc/apds990x.c:	chip->prox_thres = APDS_PROX_DEF_THRES;
+drivers/misc/apds990x.c:	chip->pdrive = chip->pdata->pdrive;
+drivers/misc/apds990x.c:	chip->pdiode = APDS_PDIODE_IR;
+drivers/misc/apds990x.c:	chip->pgain = APDS_PGAIN_1X;
+drivers/misc/apds990x.c:	chip->prox_calib = APDS_PROX_NEUTRAL_CALIB_VALUE;
+drivers/misc/apds990x.c:	chip->prox_persistence = APDS_DEFAULT_PROX_PERS;
+drivers/misc/apds990x.c:	chip->prox_continuous_mode = false;
+drivers/misc/apds990x.c:	chip->regs[0].supply = reg_vcc;
+drivers/misc/apds990x.c:	chip->regs[1].supply = reg_vled;
+drivers/misc/apds990x.c:				 ARRAY_SIZE(chip->regs), chip->regs);
+drivers/misc/apds990x.c:	err = regulator_bulk_enable(ARRAY_SIZE(chip->regs), chip->regs);
+drivers/misc/apds990x.c:	if (chip->pdata->setup_resources) {
+drivers/misc/apds990x.c:		err = chip->pdata->setup_resources();
+drivers/misc/apds990x.c:	err = sysfs_create_group(&chip->client->dev.kobj,
+drivers/misc/apds990x.c:		dev_err(&chip->client->dev, "Sysfs registration failed\n");
+drivers/misc/apds990x.c:	sysfs_remove_group(&chip->client->dev.kobj,
+drivers/misc/apds990x.c:	if (chip->pdata && chip->pdata->release_resources)
+drivers/misc/apds990x.c:		chip->pdata->release_resources();
+drivers/misc/apds990x.c:	regulator_bulk_disable(ARRAY_SIZE(chip->regs), chip->regs);
+drivers/misc/apds990x.c:	regulator_bulk_free(ARRAY_SIZE(chip->regs), chip->regs);
+drivers/misc/apds990x.c:	sysfs_remove_group(&chip->client->dev.kobj,
+drivers/misc/apds990x.c:	if (chip->pdata && chip->pdata->release_resources)
+drivers/misc/apds990x.c:		chip->pdata->release_resources();
+drivers/misc/apds990x.c:	regulator_bulk_free(ARRAY_SIZE(chip->regs), chip->regs);
+drivers/misc/bh1770glc.c: * interrupt control functions are called while keeping chip->mutex
+drivers/misc/bh1770glc.c:	chip->int_mode_lux = lux;
+drivers/misc/bh1770glc.c:	return i2c_smbus_write_byte_data(chip->client,
+drivers/misc/bh1770glc.c:					(lux << 1) | chip->int_mode_prox);
+drivers/misc/bh1770glc.c:	chip->int_mode_prox = ps;
+drivers/misc/bh1770glc.c:	return i2c_smbus_write_byte_data(chip->client,
+drivers/misc/bh1770glc.c:					(chip->int_mode_lux << 1) | (ps << 0));
+drivers/misc/bh1770glc.c:/* chip->mutex is always kept here */
+drivers/misc/bh1770glc.c:	if (pm_runtime_suspended(&chip->client->dev))
+drivers/misc/bh1770glc.c:	if (chip->prox_enable_count)
+drivers/misc/bh1770glc.c:	return i2c_smbus_write_byte_data(chip->client,
+drivers/misc/bh1770glc.c:		chip->prox_rate_threshold : chip->prox_rate;
+drivers/misc/bh1770glc.c:	return i2c_smbus_write_byte_data(chip->client,
+drivers/misc/bh1770glc.c:	return i2c_smbus_write_byte_data(chip->client,
+drivers/misc/bh1770glc.c:					chip->prox_led);
+drivers/misc/bh1770glc.c:	adjusted = (u16)(((u32)(psraw + chip->prox_const) * chip->prox_coef) /
+drivers/misc/bh1770glc.c:	raw = (((u32)ps * BH1770_COEF_SCALER) / chip->prox_coef);
+drivers/misc/bh1770glc.c:	if (raw > chip->prox_const)
+drivers/misc/bh1770glc.c:		raw = raw - chip->prox_const;
+drivers/misc/bh1770glc.c:	if (pm_runtime_suspended(&chip->client->dev))
+drivers/misc/bh1770glc.c:	tmp = bh1770_psadjusted_to_raw(chip, chip->prox_threshold);
+drivers/misc/bh1770glc.c:	chip->prox_threshold_hw = tmp;
+drivers/misc/bh1770glc.c:	return	i2c_smbus_write_byte_data(chip->client, BH1770_PS_TH_LED1,
+drivers/misc/bh1770glc.c:	lux = ((u32)raw * chip->lux_corr) / BH1770_LUX_CORR_SCALE;
+drivers/misc/bh1770glc.c:	return (u32)adjusted * BH1770_LUX_CORR_SCALE / chip->lux_corr;
+drivers/misc/bh1770glc.c:/* chip->mutex is kept when this is called */
+drivers/misc/bh1770glc.c:	if (pm_runtime_suspended(&chip->client->dev))
+drivers/misc/bh1770glc.c:	if (chip->lux_thres_hi_onchip == threshold_hi &&
+drivers/misc/bh1770glc.c:	    chip->lux_thres_lo_onchip == threshold_lo)
+drivers/misc/bh1770glc.c:	chip->lux_thres_hi_onchip = threshold_hi;
+drivers/misc/bh1770glc.c:	chip->lux_thres_lo_onchip = threshold_lo;
+drivers/misc/bh1770glc.c:	ret = i2c_smbus_write_i2c_block_data(chip->client,
+drivers/misc/bh1770glc.c:	ret = i2c_smbus_read_byte_data(chip->client, BH1770_ALS_DATA_0);
+drivers/misc/bh1770glc.c:	ret = i2c_smbus_read_byte_data(chip->client, BH1770_ALS_DATA_1);
+drivers/misc/bh1770glc.c:	chip->lux_data_raw = data | ((ret & 0xff) << 8);
+drivers/misc/bh1770glc.c:	tmp = (BH1770_LUX_CORR_SCALE * chip->lux_ga) / BH1770_LUX_GA_SCALE;
+drivers/misc/bh1770glc.c:	tmp = (tmp * chip->lux_cf) / BH1770_LUX_CF_SCALE;
+drivers/misc/bh1770glc.c:	tmp = (tmp * chip->lux_calib) / BH1770_CALIB_SCALER;
+drivers/misc/bh1770glc.c:	return bh1770_lux_raw_to_adjusted(chip, chip->lux_data_raw);
+drivers/misc/bh1770glc.c:	int ret = regulator_bulk_enable(ARRAY_SIZE(chip->regs),
+drivers/misc/bh1770glc.c:					chip->regs);
+drivers/misc/bh1770glc.c:	i2c_smbus_write_byte_data(chip->client, BH1770_ALS_CONTROL,
+drivers/misc/bh1770glc.c:	chip->lux_data_raw = 0;
+drivers/misc/bh1770glc.c:	chip->prox_data = 0;
+drivers/misc/bh1770glc.c:	ret = i2c_smbus_write_byte_data(chip->client,
+drivers/misc/bh1770glc.c:	chip->lux_thres_hi_onchip = BH1770_LUX_RANGE;
+drivers/misc/bh1770glc.c:	chip->lux_thres_lo_onchip = 0;
+drivers/misc/bh1770glc.c:	i2c_smbus_write_byte_data(chip->client,
+drivers/misc/bh1770glc.c:	i2c_smbus_write_byte_data(chip->client,
+drivers/misc/bh1770glc.c:	i2c_smbus_write_byte_data(chip->client,
+drivers/misc/bh1770glc.c:	regulator_bulk_disable(ARRAY_SIZE(chip->regs), chip->regs);
+drivers/misc/bh1770glc.c:/* chip->mutex is kept when this is called */
+drivers/misc/bh1770glc.c:	if (chip->prox_enable_count) {
+drivers/misc/bh1770glc.c:		chip->prox_force_update = true; /* Force immediate update */
+drivers/misc/bh1770glc.c:		bh1770_lux_rate(chip, chip->lux_rate_index);
+drivers/misc/bh1770glc.c:		i2c_smbus_write_byte_data(chip->client,
+drivers/misc/bh1770glc.c:		chip->prox_data = 0;
+drivers/misc/bh1770glc.c:		bh1770_lux_rate(chip, chip->lux_rate_index);
+drivers/misc/bh1770glc.c:		i2c_smbus_write_byte_data(chip->client,
+drivers/misc/bh1770glc.c:/* chip->mutex is kept when this is called */
+drivers/misc/bh1770glc.c:	ret = i2c_smbus_read_byte_data(chip->client, BH1770_PS_DATA_LED1);
+drivers/misc/bh1770glc.c:	if (ret > chip->prox_threshold_hw)
+drivers/misc/bh1770glc.c:	if (chip->lux_data_raw > PROX_IGNORE_LUX_LIMIT)
+drivers/misc/bh1770glc.c:	chip->prox_data = bh1770_psraw_to_adjusted(chip, ret);
+drivers/misc/bh1770glc.c:	if (chip->prox_data >= chip->prox_abs_thres ||
+drivers/misc/bh1770glc.c:	    chip->prox_force_update)
+drivers/misc/bh1770glc.c:		chip->prox_persistence_counter = chip->prox_persistence;
+drivers/misc/bh1770glc.c:	chip->prox_force_update = false;
+drivers/misc/bh1770glc.c:		if (chip->prox_persistence_counter < chip->prox_persistence) {
+drivers/misc/bh1770glc.c:			chip->prox_persistence_counter++;
+drivers/misc/bh1770glc.c:		chip->prox_persistence_counter = 0;
+drivers/misc/bh1770glc.c:		chip->prox_data = 0;
+drivers/misc/bh1770glc.c:		sysfs_notify(&chip->client->dev.kobj, NULL, "prox0_raw");
+drivers/misc/bh1770glc.c:	struct i2c_client *client = chip->client;
+drivers/misc/bh1770glc.c:	chip->revision = (part & BH1770_REV_MASK) >> BH1770_REV_SHIFT;
+drivers/misc/bh1770glc.c:	chip->prox_coef = BH1770_COEF_SCALER;
+drivers/misc/bh1770glc.c:	chip->prox_const = 0;
+drivers/misc/bh1770glc.c:	chip->lux_cf = BH1770_NEUTRAL_CF;
+drivers/misc/bh1770glc.c:		snprintf(chip->chipname, sizeof(chip->chipname), "BH1770GLC");
+drivers/misc/bh1770glc.c:		snprintf(chip->chipname, sizeof(chip->chipname), "SFH7770");
+drivers/misc/bh1770glc.c:		chip->prox_coef = 819; /* 0.8 * BH1770_COEF_SCALER */
+drivers/misc/bh1770glc.c:		chip->prox_const = 40;
+drivers/misc/bh1770glc.c:	mutex_lock(&chip->mutex);
+drivers/misc/bh1770glc.c:	mutex_unlock(&chip->mutex);
+drivers/misc/bh1770glc.c:	mutex_lock(&chip->mutex);
+drivers/misc/bh1770glc.c:	status = i2c_smbus_read_byte_data(chip->client, BH1770_ALS_PS_STATUS);
+drivers/misc/bh1770glc.c:	i2c_smbus_read_byte_data(chip->client, BH1770_INTERRUPT);
+drivers/misc/bh1770glc.c:		if (unlikely(chip->lux_wait_result)) {
+drivers/misc/bh1770glc.c:			chip->lux_wait_result = false;
+drivers/misc/bh1770glc.c:			wake_up(&chip->wait);
+drivers/misc/bh1770glc.c:						chip->lux_threshold_hi,
+drivers/misc/bh1770glc.c:						chip->lux_threshold_lo);
+drivers/misc/bh1770glc.c:	i2c_smbus_write_byte_data(chip->client, BH1770_INTERRUPT,
+drivers/misc/bh1770glc.c:		sysfs_notify(&chip->client->dev.kobj, NULL, "lux0_input");
+drivers/misc/bh1770glc.c:	if (chip->int_mode_prox && (status & BH1770_INT_LEDS_INT)) {
+drivers/misc/bh1770glc.c:		rate = prox_rates_ms[chip->prox_rate_threshold];
+drivers/misc/bh1770glc.c:	i2c_smbus_write_byte_data(chip->client, BH1770_INTERRUPT,
+drivers/misc/bh1770glc.c:				  (chip->int_mode_lux << 1) |
+drivers/misc/bh1770glc.c:				  (chip->int_mode_prox << 0));
+drivers/misc/bh1770glc.c:	mutex_unlock(&chip->mutex);
+drivers/misc/bh1770glc.c:		cancel_delayed_work_sync(&chip->prox_work);
+drivers/misc/bh1770glc.c:		schedule_delayed_work(&chip->prox_work,
+drivers/misc/bh1770glc.c:	mutex_lock(&chip->mutex);
+drivers/misc/bh1770glc.c:		ret = bh1770_lux_rate(chip, chip->lux_rate_index);
+drivers/misc/bh1770glc.c:		chip->lux_wait_result = true;
+drivers/misc/bh1770glc.c:	mutex_unlock(&chip->mutex);
+drivers/misc/bh1770glc.c:	timeout = wait_event_interruptible_timeout(chip->wait,
+drivers/misc/bh1770glc.c:					!chip->lux_wait_result,
+drivers/misc/bh1770glc.c:	mutex_lock(&chip->mutex);
+drivers/misc/bh1770glc.c:	mutex_unlock(&chip->mutex);
+drivers/misc/bh1770glc.c:	mutex_lock(&chip->mutex);
+drivers/misc/bh1770glc.c:	if (!chip->prox_enable_count)
+drivers/misc/bh1770glc.c:		chip->prox_data = 0;
+drivers/misc/bh1770glc.c:		chip->prox_enable_count++;
+drivers/misc/bh1770glc.c:	else if (chip->prox_enable_count > 0)
+drivers/misc/bh1770glc.c:		chip->prox_enable_count--;
+drivers/misc/bh1770glc.c:	mutex_unlock(&chip->mutex);
+drivers/misc/bh1770glc.c:	mutex_lock(&chip->mutex);
+drivers/misc/bh1770glc.c:	len = sprintf(buf, "%d\n", chip->prox_enable_count);
+drivers/misc/bh1770glc.c:	mutex_unlock(&chip->mutex);
+drivers/misc/bh1770glc.c:	mutex_lock(&chip->mutex);
+drivers/misc/bh1770glc.c:	if (chip->prox_enable_count && !pm_runtime_suspended(dev))
+drivers/misc/bh1770glc.c:		ret = sprintf(buf, "%d\n", chip->prox_data);
+drivers/misc/bh1770glc.c:	mutex_unlock(&chip->mutex);
+drivers/misc/bh1770glc.c:	return sprintf(buf, "%d\n", prox_rates_hz[chip->prox_rate_threshold]);
+drivers/misc/bh1770glc.c:	return sprintf(buf, "%d\n", prox_rates_hz[chip->prox_rate]);
+drivers/misc/bh1770glc.c:	mutex_lock(&chip->mutex);
+drivers/misc/bh1770glc.c:	chip->prox_rate_threshold = bh1770_prox_rate_validate(value);
+drivers/misc/bh1770glc.c:	mutex_unlock(&chip->mutex);
+drivers/misc/bh1770glc.c:	mutex_lock(&chip->mutex);
+drivers/misc/bh1770glc.c:	chip->prox_rate = bh1770_prox_rate_validate(value);
+drivers/misc/bh1770glc.c:	mutex_unlock(&chip->mutex);
+drivers/misc/bh1770glc.c:	return sprintf(buf, "%d\n", chip->prox_threshold);
+drivers/misc/bh1770glc.c:	mutex_lock(&chip->mutex);
+drivers/misc/bh1770glc.c:	chip->prox_threshold = value;
+drivers/misc/bh1770glc.c:	mutex_unlock(&chip->mutex);
+drivers/misc/bh1770glc.c:	return sprintf(buf, "%u\n", chip->prox_persistence);
+drivers/misc/bh1770glc.c:	chip->prox_persistence = value;
+drivers/misc/bh1770glc.c:	return sprintf(buf, "%u\n", chip->prox_abs_thres);
+drivers/misc/bh1770glc.c:	chip->prox_abs_thres = value;
+drivers/misc/bh1770glc.c:	return sprintf(buf, "%s rev %d\n", chip->chipname, chip->revision);
+drivers/misc/bh1770glc.c:	mutex_lock(&chip->mutex);
+drivers/misc/bh1770glc.c:	len = sprintf(buf, "%u\n", chip->lux_calib);
+drivers/misc/bh1770glc.c:	mutex_unlock(&chip->mutex);
+drivers/misc/bh1770glc.c:	mutex_lock(&chip->mutex);
+drivers/misc/bh1770glc.c:	old_calib = chip->lux_calib;
+drivers/misc/bh1770glc.c:	chip->lux_calib = value;
+drivers/misc/bh1770glc.c:		chip->lux_calib = old_calib;
+drivers/misc/bh1770glc.c:		mutex_unlock(&chip->mutex);
+drivers/misc/bh1770glc.c:	chip->lux_corr = new_corr;
+drivers/misc/bh1770glc.c:	bh1770_lux_update_thresholds(chip, chip->lux_threshold_hi,
+drivers/misc/bh1770glc.c:				chip->lux_threshold_lo);
+drivers/misc/bh1770glc.c:	mutex_unlock(&chip->mutex);
+drivers/misc/bh1770glc.c:	return sprintf(buf, "%d\n", lux_rates_hz[chip->lux_rate_index]);
+drivers/misc/bh1770glc.c:	mutex_lock(&chip->mutex);
+drivers/misc/bh1770glc.c:	chip->lux_rate_index = i;
+drivers/misc/bh1770glc.c:	mutex_unlock(&chip->mutex);
+drivers/misc/bh1770glc.c:	return sprintf(buf, "%d\n", chip->lux_threshold_hi);
+drivers/misc/bh1770glc.c:	return sprintf(buf, "%d\n", chip->lux_threshold_lo);
+drivers/misc/bh1770glc.c:	mutex_lock(&chip->mutex);
+drivers/misc/bh1770glc.c:	if (!chip->lux_wait_result)
+drivers/misc/bh1770glc.c:						chip->lux_threshold_hi,
+drivers/misc/bh1770glc.c:						chip->lux_threshold_lo);
+drivers/misc/bh1770glc.c:	mutex_unlock(&chip->mutex);
+drivers/misc/bh1770glc.c:	int ret = bh1770_set_lux_thresh(chip, &chip->lux_threshold_hi, buf);
+drivers/misc/bh1770glc.c:	int ret = bh1770_set_lux_thresh(chip, &chip->lux_threshold_lo, buf);
+drivers/misc/bh1770glc.c:	chip->client  = client;
+drivers/misc/bh1770glc.c:	mutex_init(&chip->mutex);
+drivers/misc/bh1770glc.c:	init_waitqueue_head(&chip->wait);
+drivers/misc/bh1770glc.c:	INIT_DELAYED_WORK(&chip->prox_work, bh1770_prox_work);
+drivers/misc/bh1770glc.c:	chip->pdata		= client->dev.platform_data;
+drivers/misc/bh1770glc.c:	chip->lux_calib		= BH1770_LUX_NEUTRAL_CALIB_VALUE;
+drivers/misc/bh1770glc.c:	chip->lux_rate_index	= BH1770_LUX_DEFAULT_RATE;
+drivers/misc/bh1770glc.c:	chip->lux_threshold_lo	= BH1770_LUX_DEF_THRES;
+drivers/misc/bh1770glc.c:	chip->lux_threshold_hi	= BH1770_LUX_DEF_THRES;
+drivers/misc/bh1770glc.c:	if (chip->pdata->glass_attenuation == 0)
+drivers/misc/bh1770glc.c:		chip->lux_ga = BH1770_NEUTRAL_GA;
+drivers/misc/bh1770glc.c:		chip->lux_ga = chip->pdata->glass_attenuation;
+drivers/misc/bh1770glc.c:	chip->prox_threshold	= BH1770_PROX_DEF_THRES;
+drivers/misc/bh1770glc.c:	chip->prox_led		= chip->pdata->led_def_curr;
+drivers/misc/bh1770glc.c:	chip->prox_abs_thres	= BH1770_PROX_DEF_ABS_THRES;
+drivers/misc/bh1770glc.c:	chip->prox_persistence	= BH1770_DEFAULT_PERSISTENCE;
+drivers/misc/bh1770glc.c:	chip->prox_rate_threshold = BH1770_PROX_DEF_RATE_THRESH;
+drivers/misc/bh1770glc.c:	chip->prox_rate		= BH1770_PROX_DEFAULT_RATE;
+drivers/misc/bh1770glc.c:	chip->prox_data		= 0;
+drivers/misc/bh1770glc.c:	chip->regs[0].supply = reg_vcc;
+drivers/misc/bh1770glc.c:	chip->regs[1].supply = reg_vleds;
+drivers/misc/bh1770glc.c:				      ARRAY_SIZE(chip->regs), chip->regs);
+drivers/misc/bh1770glc.c:	err = regulator_bulk_enable(ARRAY_SIZE(chip->regs),
+drivers/misc/bh1770glc.c:				chip->regs);
+drivers/misc/bh1770glc.c:	chip->lux_corr = bh1770_get_corr_value(chip);
+drivers/misc/bh1770glc.c:	if (chip->lux_corr == 0) {
+drivers/misc/bh1770glc.c:	if (chip->pdata->setup_resources) {
+drivers/misc/bh1770glc.c:		err = chip->pdata->setup_resources();
+drivers/misc/bh1770glc.c:	err = sysfs_create_group(&chip->client->dev.kobj,
+drivers/misc/bh1770glc.c:		dev_err(&chip->client->dev, "Sysfs registration failed\n");
+drivers/misc/bh1770glc.c:	regulator_bulk_disable(ARRAY_SIZE(chip->regs), chip->regs);
+drivers/misc/bh1770glc.c:	sysfs_remove_group(&chip->client->dev.kobj,
+drivers/misc/bh1770glc.c:	if (chip->pdata->release_resources)
+drivers/misc/bh1770glc.c:		chip->pdata->release_resources();
+drivers/misc/bh1770glc.c:	regulator_bulk_disable(ARRAY_SIZE(chip->regs), chip->regs);
+drivers/misc/bh1770glc.c:	sysfs_remove_group(&chip->client->dev.kobj,
+drivers/misc/bh1770glc.c:	if (chip->pdata->release_resources)
+drivers/misc/bh1770glc.c:		chip->pdata->release_resources();
+drivers/misc/bh1770glc.c:	cancel_delayed_work_sync(&chip->prox_work);
+drivers/misc/bh1770glc.c:		ret = bh1770_lux_rate(chip, chip->lux_rate_index);
+drivers/misc/bh1770glc.c:		chip->lux_wait_result = true;
+drivers/misc/cb710/core.c:	struct cb710_slot *slot = &chip->slot[0];
+drivers/misc/cb710/core.c:	spin_lock(&chip->irq_lock); /* incl. smp_rmb() */
+drivers/misc/cb710/core.c:	for (nr = chip->slots; nr; ++slot, --nr) {
+drivers/misc/cb710/core.c:	spin_unlock(&chip->irq_lock);
+drivers/misc/cb710/core.c:	atomic_dec(&chip->slot_refs_count);
+drivers/misc/cb710/core.c:	int nr = chip->slots;
+drivers/misc/cb710/core.c:	struct cb710_slot *slot = &chip->slot[nr];
+drivers/misc/cb710/core.c:		name, chip->platform_id, nr, slot_mask, io_offset);
+drivers/misc/cb710/core.c:	++chip->slots;
+drivers/misc/cb710/core.c:	slot->iobase = chip->iobase + io_offset;
+drivers/misc/cb710/core.c:	slot->pdev.id = chip->platform_id;
+drivers/misc/cb710/core.c:	slot->pdev.dev.parent = &chip->pdev->dev;
+drivers/misc/cb710/core.c:	atomic_inc(&chip->slot_refs_count);
+drivers/misc/cb710/core.c:		--chip->slots;
+drivers/misc/cb710/core.c:	chip->slot_mask |= slot_mask;
+drivers/misc/cb710/core.c:	int nr = chip->slots - 1;
+drivers/misc/cb710/core.c:	if (!(chip->slot_mask & slot_mask))
+drivers/misc/cb710/core.c:	platform_device_unregister(&chip->slot[nr].pdev);
+drivers/misc/cb710/core.c:	BUG_ON(chip->slot[nr].irq_handler != NULL);
+drivers/misc/cb710/core.c:	--chip->slots;
+drivers/misc/cb710/core.c:	chip->slot_mask &= ~slot_mask;
+drivers/misc/cb710/core.c:	spin_lock_irqsave(&chip->irq_lock, flags);
+drivers/misc/cb710/core.c:	spin_unlock_irqrestore(&chip->irq_lock, flags);
+drivers/misc/cb710/core.c:	spin_lock_init(&chip->irq_lock);
+drivers/misc/cb710/core.c:	chip->pdev = pdev;
+drivers/misc/cb710/core.c:	chip->iobase = pcim_iomap_table(pdev)[0];
+drivers/misc/cb710/core.c:	chip->platform_id = err;
+drivers/misc/cb710/core.c:		chip->platform_id, chip->iobase, pdev->irq);
+drivers/misc/cb710/core.c:	BUG_ON(atomic_read(&chip->slot_refs_count) != 0);
+drivers/misc/cb710/core.c:	BUG_ON(atomic_read(&chip->slot_refs_count) != 0);
+drivers/misc/cb710/core.c:	ida_free(&cb710_ida, chip->platform_id);
+drivers/misc/cb710/debug.c:	cb710_read_regs_##t(chip->iobase, regs, select);		\
+drivers/misc/cs5535-mfgpt.c:		spin_lock_irqsave(&timer->chip->lock, flags);
+drivers/misc/cs5535-mfgpt.c:		__set_bit(timer->nr, timer->chip->avail);
+drivers/misc/cs5535-mfgpt.c:		spin_unlock_irqrestore(&timer->chip->lock, flags);
+drivers/misc/cs5535-mfgpt.c:	return inw(timer->chip->base + reg + (timer->nr * 8));
+drivers/misc/cs5535-mfgpt.c:	outw(value, timer->chip->base + reg + (timer->nr * 8));
+drivers/misc/cxl/pci.c:	while (np && !(prop = of_get_property(np, "ibm,chip-id", NULL)))
+drivers/misc/eeprom/at25.c:	strncpy(chip->name, "at25", sizeof(chip->name));
+drivers/misc/eeprom/at25.c:		chip->byte_len = val;
+drivers/misc/eeprom/at25.c:		chip->page_size = (u16)val;
+drivers/misc/eeprom/at25.c:		chip->flags = (u16)val;
+drivers/misc/eeprom/at25.c:			chip->flags |= EE_INSTR_BIT3_IS_ADDR;
+drivers/misc/eeprom/at25.c:			chip->flags |= EE_ADDR1;
+drivers/misc/eeprom/at25.c:			chip->flags |= EE_ADDR2;
+drivers/misc/eeprom/at25.c:			chip->flags |= EE_ADDR3;
+drivers/misc/eeprom/at25.c:			chip->flags |= EE_READONLY;
+drivers/misc/pch_phub.c:	void __iomem *reg_addr = chip->pch_phub_base_address + reg_addr_offset;
+drivers/misc/pch_phub.c:	void __iomem *p = chip->pch_phub_base_address;
+drivers/misc/pch_phub.c:	chip->phub_id_reg = ioread32(p + PCH_PHUB_ID_REG);
+drivers/misc/pch_phub.c:	chip->q_pri_val_reg = ioread32(p + PCH_PHUB_QUEUE_PRI_VAL_REG);
+drivers/misc/pch_phub.c:	chip->rc_q_maxsize_reg = ioread32(p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG);
+drivers/misc/pch_phub.c:	chip->bri_q_maxsize_reg = ioread32(p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG);
+drivers/misc/pch_phub.c:	chip->comp_resp_timeout_reg =
+drivers/misc/pch_phub.c:	chip->bus_slave_control_reg =
+drivers/misc/pch_phub.c:	chip->deadlock_avoid_type_reg =
+drivers/misc/pch_phub.c:	chip->intpin_reg_wpermit_reg0 =
+drivers/misc/pch_phub.c:	chip->intpin_reg_wpermit_reg1 =
+drivers/misc/pch_phub.c:	chip->intpin_reg_wpermit_reg2 =
+drivers/misc/pch_phub.c:	chip->intpin_reg_wpermit_reg3 =
+drivers/misc/pch_phub.c:		"chip->phub_id_reg=%x, "
+drivers/misc/pch_phub.c:		"chip->q_pri_val_reg=%x, "
+drivers/misc/pch_phub.c:		"chip->rc_q_maxsize_reg=%x, "
+drivers/misc/pch_phub.c:		"chip->bri_q_maxsize_reg=%x, "
+drivers/misc/pch_phub.c:		"chip->comp_resp_timeout_reg=%x, "
+drivers/misc/pch_phub.c:		"chip->bus_slave_control_reg=%x, "
+drivers/misc/pch_phub.c:		"chip->deadlock_avoid_type_reg=%x, "
+drivers/misc/pch_phub.c:		"chip->intpin_reg_wpermit_reg0=%x, "
+drivers/misc/pch_phub.c:		"chip->intpin_reg_wpermit_reg1=%x, "
+drivers/misc/pch_phub.c:		"chip->intpin_reg_wpermit_reg2=%x, "
+drivers/misc/pch_phub.c:		"chip->intpin_reg_wpermit_reg3=%x\n", __func__,
+drivers/misc/pch_phub.c:		chip->phub_id_reg,
+drivers/misc/pch_phub.c:		chip->q_pri_val_reg,
+drivers/misc/pch_phub.c:		chip->rc_q_maxsize_reg,
+drivers/misc/pch_phub.c:		chip->bri_q_maxsize_reg,
+drivers/misc/pch_phub.c:		chip->comp_resp_timeout_reg,
+drivers/misc/pch_phub.c:		chip->bus_slave_control_reg,
+drivers/misc/pch_phub.c:		chip->deadlock_avoid_type_reg,
+drivers/misc/pch_phub.c:		chip->intpin_reg_wpermit_reg0,
+drivers/misc/pch_phub.c:		chip->intpin_reg_wpermit_reg1,
+drivers/misc/pch_phub.c:		chip->intpin_reg_wpermit_reg2,
+drivers/misc/pch_phub.c:		chip->intpin_reg_wpermit_reg3);
+drivers/misc/pch_phub.c:		chip->int_reduce_control_reg[i] =
+drivers/misc/pch_phub.c:			"chip->int_reduce_control_reg[%d]=%x\n",
+drivers/misc/pch_phub.c:			__func__, i, chip->int_reduce_control_reg[i]);
+drivers/misc/pch_phub.c:	chip->clkcfg_reg = ioread32(p + CLKCFG_REG_OFFSET);
+drivers/misc/pch_phub.c:	if ((chip->ioh_type == 2) || (chip->ioh_type == 4))
+drivers/misc/pch_phub.c:		chip->funcsel_reg = ioread32(p + FUNCSEL_REG_OFFSET);
+drivers/misc/pch_phub.c:	p = chip->pch_phub_base_address;
+drivers/misc/pch_phub.c:	iowrite32(chip->phub_id_reg, p + PCH_PHUB_ID_REG);
+drivers/misc/pch_phub.c:	iowrite32(chip->q_pri_val_reg, p + PCH_PHUB_QUEUE_PRI_VAL_REG);
+drivers/misc/pch_phub.c:	iowrite32(chip->rc_q_maxsize_reg, p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG);
+drivers/misc/pch_phub.c:	iowrite32(chip->bri_q_maxsize_reg, p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG);
+drivers/misc/pch_phub.c:	iowrite32(chip->comp_resp_timeout_reg,
+drivers/misc/pch_phub.c:	iowrite32(chip->bus_slave_control_reg,
+drivers/misc/pch_phub.c:	iowrite32(chip->deadlock_avoid_type_reg,
+drivers/misc/pch_phub.c:	iowrite32(chip->intpin_reg_wpermit_reg0,
+drivers/misc/pch_phub.c:	iowrite32(chip->intpin_reg_wpermit_reg1,
+drivers/misc/pch_phub.c:	iowrite32(chip->intpin_reg_wpermit_reg2,
+drivers/misc/pch_phub.c:	iowrite32(chip->intpin_reg_wpermit_reg3,
+drivers/misc/pch_phub.c:		"chip->phub_id_reg=%x, "
+drivers/misc/pch_phub.c:		"chip->q_pri_val_reg=%x, "
+drivers/misc/pch_phub.c:		"chip->rc_q_maxsize_reg=%x, "
+drivers/misc/pch_phub.c:		"chip->bri_q_maxsize_reg=%x, "
+drivers/misc/pch_phub.c:		"chip->comp_resp_timeout_reg=%x, "
+drivers/misc/pch_phub.c:		"chip->bus_slave_control_reg=%x, "
+drivers/misc/pch_phub.c:		"chip->deadlock_avoid_type_reg=%x, "
+drivers/misc/pch_phub.c:		"chip->intpin_reg_wpermit_reg0=%x, "
+drivers/misc/pch_phub.c:		"chip->intpin_reg_wpermit_reg1=%x, "
+drivers/misc/pch_phub.c:		"chip->intpin_reg_wpermit_reg2=%x, "
+drivers/misc/pch_phub.c:		"chip->intpin_reg_wpermit_reg3=%x\n", __func__,
+drivers/misc/pch_phub.c:		chip->phub_id_reg,
+drivers/misc/pch_phub.c:		chip->q_pri_val_reg,
+drivers/misc/pch_phub.c:		chip->rc_q_maxsize_reg,
+drivers/misc/pch_phub.c:		chip->bri_q_maxsize_reg,
+drivers/misc/pch_phub.c:		chip->comp_resp_timeout_reg,
+drivers/misc/pch_phub.c:		chip->bus_slave_control_reg,
+drivers/misc/pch_phub.c:		chip->deadlock_avoid_type_reg,
+drivers/misc/pch_phub.c:		chip->intpin_reg_wpermit_reg0,
+drivers/misc/pch_phub.c:		chip->intpin_reg_wpermit_reg1,
+drivers/misc/pch_phub.c:		chip->intpin_reg_wpermit_reg2,
+drivers/misc/pch_phub.c:		chip->intpin_reg_wpermit_reg3);
+drivers/misc/pch_phub.c:		iowrite32(chip->int_reduce_control_reg[i],
+drivers/misc/pch_phub.c:			"chip->int_reduce_control_reg[%d]=%x\n",
+drivers/misc/pch_phub.c:			__func__, i, chip->int_reduce_control_reg[i]);
+drivers/misc/pch_phub.c:	iowrite32(chip->clkcfg_reg, p + CLKCFG_REG_OFFSET);
+drivers/misc/pch_phub.c:	if ((chip->ioh_type == 2) || (chip->ioh_type == 4))
+drivers/misc/pch_phub.c:		iowrite32(chip->funcsel_reg, p + FUNCSEL_REG_OFFSET);
+drivers/misc/pch_phub.c:	void __iomem *mem_addr = chip->pch_phub_extrom_base_address +
+drivers/misc/pch_phub.c:	void __iomem *mem_addr = chip->pch_phub_extrom_base_address +
+drivers/misc/pch_phub.c:			chip->pch_phub_extrom_base_address + PHUB_CONTROL);
+drivers/misc/pch_phub.c:	while (ioread8(chip->pch_phub_extrom_base_address +
+drivers/misc/pch_phub.c:			chip->pch_phub_extrom_base_address + PHUB_CONTROL);
+drivers/misc/pch_phub.c:	mem_addr = chip->pch_mac_start_address +
+drivers/misc/pch_phub.c:	mem_addr = chip->pch_mac_start_address +
+drivers/misc/pch_phub.c:	if ((chip->ioh_type == 1) || (chip->ioh_type == 5)) /* EG20T or ML7831*/
+drivers/misc/pch_phub.c:	chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
+drivers/misc/pch_phub.c:	if (!chip->pch_phub_extrom_base_address) {
+drivers/misc/pch_phub.c:	pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address,
+drivers/misc/pch_phub.c:	pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address + 1,
+drivers/misc/pch_phub.c:					 chip->pch_opt_rom_start_address + 2,
+drivers/misc/pch_phub.c:			    chip->pch_opt_rom_start_address + addr_offset + off,
+drivers/misc/pch_phub.c:	pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
+drivers/misc/pch_phub.c:	pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
+drivers/misc/pch_phub.c:	chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
+drivers/misc/pch_phub.c:	if (!chip->pch_phub_extrom_base_address) {
+drivers/misc/pch_phub.c:			    chip->pch_opt_rom_start_address + addr_offset + off,
+drivers/misc/pch_phub.c:	pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
+drivers/misc/pch_phub.c:	pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
+drivers/misc/pch_phub.c:	chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
+drivers/misc/pch_phub.c:	if (!chip->pch_phub_extrom_base_address)
+drivers/misc/pch_phub.c:	pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
+drivers/misc/pch_phub.c:	chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size);
+drivers/misc/pch_phub.c:	if (!chip->pch_phub_extrom_base_address)
+drivers/misc/pch_phub.c:	pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address);
+drivers/misc/pch_phub.c:	chip->pch_phub_base_address = pci_iomap(pdev, 1, 0);
+drivers/misc/pch_phub.c:	if (chip->pch_phub_base_address == NULL) {
+drivers/misc/pch_phub.c:		chip->pch_phub_base_address);
+drivers/misc/pch_phub.c:	chip->pdev = pdev; /* Save pci device struct */
+drivers/misc/pch_phub.c:		iowrite32(prefetch, chip->pch_phub_base_address + 0x14);
+drivers/misc/pch_phub.c:		iowrite32(0x25, chip->pch_phub_base_address + 0x44);
+drivers/misc/pch_phub.c:		chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T;
+drivers/misc/pch_phub.c:		chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_EG20T;
+drivers/misc/pch_phub.c:		iowrite32(0x000affa0, chip->pch_phub_base_address + 0x14);
+drivers/misc/pch_phub.c:		chip->pch_opt_rom_start_address =\
+drivers/misc/pch_phub.c:		iowrite32(0x000a0000, chip->pch_phub_base_address + 0x14);
+drivers/misc/pch_phub.c:		iowrite32(0x25, chip->pch_phub_base_address + 0x140);
+drivers/misc/pch_phub.c:		chip->pch_opt_rom_start_address =\
+drivers/misc/pch_phub.c:		chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223;
+drivers/misc/pch_phub.c:		iowrite32(0x0000ffa0, chip->pch_phub_base_address + 0x14);
+drivers/misc/pch_phub.c:		chip->pch_opt_rom_start_address =\
+drivers/misc/pch_phub.c:		chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223;
+drivers/misc/pch_phub.c:		iowrite32(0x000affaa, chip->pch_phub_base_address + 0x14);
+drivers/misc/pch_phub.c:		iowrite32(0x25, chip->pch_phub_base_address + 0x44);
+drivers/misc/pch_phub.c:		chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T;
+drivers/misc/pch_phub.c:		chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_EG20T;
+drivers/misc/pch_phub.c:	chip->ioh_type = id->driver_data;
+drivers/misc/pch_phub.c:	pci_iounmap(pdev, chip->pch_phub_base_address);
+drivers/misc/pch_phub.c:	pci_iounmap(pdev, chip->pch_phub_base_address);
+drivers/mmc/host/cb710-mmc.c:	pci_read_config_dword(chip->pdev, 0x48, &val);
+drivers/mmc/host/mmc_spi.c:				"can't change chip-select polarity\n");
+drivers/mmc/host/mmc_spi.c:					"can't restore chip-select polarity\n");
+drivers/mmc/host/sdhci-acpi.c:			host->ops            = c->slot->chip->ops;
+drivers/mmc/host/sdhci-acpi.c:			host->quirks        |= c->slot->chip->quirks;
+drivers/mmc/host/sdhci-acpi.c:			host->quirks2       |= c->slot->chip->quirks2;
+drivers/mmc/host/sdhci-acpi.c:			host->mmc->caps     |= c->slot->chip->caps;
+drivers/mmc/host/sdhci-acpi.c:			host->mmc->caps2    |= c->slot->chip->caps2;
+drivers/mmc/host/sdhci-acpi.c:			host->mmc->pm_caps  |= c->slot->chip->pm_caps;
+drivers/mmc/host/sdhci-pci-core.c:	for (i = 0; i < chip->num_slots; i++) {
+drivers/mmc/host/sdhci-pci-core.c:		struct sdhci_pci_slot *slot = chip->slots[i];
+drivers/mmc/host/sdhci-pci-core.c:		return device_wakeup_enable(&chip->pdev->dev);
+drivers/mmc/host/sdhci-pci-core.c:		return device_wakeup_disable(&chip->pdev->dev);
+drivers/mmc/host/sdhci-pci-core.c:	for (i = 0; i < chip->num_slots; i++) {
+drivers/mmc/host/sdhci-pci-core.c:		struct sdhci_pci_slot *slot = chip->slots[i];
+drivers/mmc/host/sdhci-pci-core.c:		if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3)
+drivers/mmc/host/sdhci-pci-core.c:		if (device_may_wakeup(&chip->pdev->dev))
+drivers/mmc/host/sdhci-pci-core.c:		sdhci_resume_host(chip->slots[i]->host);
+drivers/mmc/host/sdhci-pci-core.c:	for (i = 0; i < chip->num_slots; i++) {
+drivers/mmc/host/sdhci-pci-core.c:		slot = chip->slots[i];
+drivers/mmc/host/sdhci-pci-core.c:	ret = cqhci_suspend(chip->slots[0]->host->mmc);
+drivers/mmc/host/sdhci-pci-core.c:	return cqhci_resume(chip->slots[0]->host->mmc);
+drivers/mmc/host/sdhci-pci-core.c:	for (i = 0; i < chip->num_slots; i++) {
+drivers/mmc/host/sdhci-pci-core.c:		slot = chip->slots[i];
+drivers/mmc/host/sdhci-pci-core.c:		if (chip->rpm_retune &&
+drivers/mmc/host/sdhci-pci-core.c:		sdhci_runtime_resume_host(chip->slots[i]->host, 0);
+drivers/mmc/host/sdhci-pci-core.c:	for (i = 0; i < chip->num_slots; i++) {
+drivers/mmc/host/sdhci-pci-core.c:		slot = chip->slots[i];
+drivers/mmc/host/sdhci-pci-core.c:	ret = cqhci_suspend(chip->slots[0]->host->mmc);
+drivers/mmc/host/sdhci-pci-core.c:	return cqhci_resume(chip->slots[0]->host->mmc);
+drivers/mmc/host/sdhci-pci-core.c:	if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
+drivers/mmc/host/sdhci-pci-core.c:	    chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
+drivers/mmc/host/sdhci-pci-core.c:		chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
+drivers/mmc/host/sdhci-pci-core.c:	chip->num_slots = 1;
+drivers/mmc/host/sdhci-pci-core.c:	err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd");
+drivers/mmc/host/sdhci-pci-core.c:	devm_gpio_free(&slot->chip->pdev->dev, gpio);
+drivers/mmc/host/sdhci-pci-core.c:	dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
+drivers/mmc/host/sdhci-pci-core.c:	struct device *dev = &slot->chip->pdev->dev;
+drivers/mmc/host/sdhci-pci-core.c:	slot->chip->rpm_retune = intel_host->d3_retune;
+drivers/mmc/host/sdhci-pci-core.c:	struct device *dev = &slot->chip->pdev->dev;
+drivers/mmc/host/sdhci-pci-core.c:	byt_ocp_setting(slot->chip->pdev);
+drivers/mmc/host/sdhci-pci-core.c:	if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
+drivers/mmc/host/sdhci-pci-core.c:	return slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC &&
+drivers/mmc/host/sdhci-pci-core.c:	if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) {
+drivers/mmc/host/sdhci-pci-core.c:	struct device *dev = &slot->chip->pdev->dev;
+drivers/mmc/host/sdhci-pci-core.c:	struct sdhci_pci_slot *slot = chip->slots[0];
+drivers/mmc/host/sdhci-pci-core.c:	chip->rpm_retune = true;
+drivers/mmc/host/sdhci-pci-core.c:	if (chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC &&
+drivers/mmc/host/sdhci-pci-core.c:	    !chip->rpm_retune)
+drivers/mmc/host/sdhci-pci-core.c:	status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev),
+drivers/mmc/host/sdhci-pci-core.c:		dev_err(&slot->chip->pdev->dev,
+drivers/mmc/host/sdhci-pci-core.c:	if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD ||
+drivers/mmc/host/sdhci-pci-core.c:	    slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD ||
+drivers/mmc/host/sdhci-pci-core.c:	    slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD ||
+drivers/mmc/host/sdhci-pci-core.c:	    slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD)
+drivers/mmc/host/sdhci-pci-core.c:	if (slot->chip->pdev->subsystem_vendor == PCI_VENDOR_ID_NI &&
+drivers/mmc/host/sdhci-pci-core.c:	    slot->chip->pdev->subsystem_device == PCI_SUBDEVICE_ID_NI_78E3)
+drivers/mmc/host/sdhci-pci-core.c:	byt_ocp_setting(chip->pdev);
+drivers/mmc/host/sdhci-pci-core.c:	byt_ocp_setting(chip->pdev);
+drivers/mmc/host/sdhci-pci-core.c:	device = ACPI_COMPANION(&slot->chip->pdev->dev);
+drivers/mmc/host/sdhci-pci-core.c:	unsigned int func = PCI_FUNC(slot->chip->pdev->devfn);
+drivers/mmc/host/sdhci-pci-core.c:	ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
+drivers/mmc/host/sdhci-pci-core.c:	return pci_write_config_byte(chip->pdev, 0xAE, scratch);
+drivers/mmc/host/sdhci-pci-core.c:	if (chip->pdev->revision == 0) {
+drivers/mmc/host/sdhci-pci-core.c:		chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
+drivers/mmc/host/sdhci-pci-core.c:	if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
+drivers/mmc/host/sdhci-pci-core.c:	else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
+drivers/mmc/host/sdhci-pci-core.c:			if ((PCI_SLOT(chip->pdev->devfn) ==
+drivers/mmc/host/sdhci-pci-core.c:				(chip->pdev->bus == sd_dev->bus))
+drivers/mmc/host/sdhci-pci-core.c:			dev_info(&chip->pdev->dev, "Refusing to bind to "
+drivers/mmc/host/sdhci-pci-core.c:		dev_err(&chip->pdev->dev, "Failure enabling card power\n");
+drivers/mmc/host/sdhci-pci-core.c:	if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
+drivers/mmc/host/sdhci-pci-core.c:	    chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
+drivers/mmc/host/sdhci-pci-core.c:		chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
+drivers/mmc/host/sdhci-pci-core.c:	if (slot->chip->pdev->revision == 0) {
+drivers/mmc/host/sdhci-pci-core.c:	if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
+drivers/mmc/host/sdhci-pci-core.c:	if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
+drivers/mmc/host/sdhci-pci-core.c:	    slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
+drivers/mmc/host/sdhci-pci-core.c:	if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
+drivers/mmc/host/sdhci-pci-core.c:	    slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
+drivers/mmc/host/sdhci-pci-core.c:	if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
+drivers/mmc/host/sdhci-pci-core.c:	    chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
+drivers/mmc/host/sdhci-pci-core.c:		for (i = 0; i < chip->num_slots; i++)
+drivers/mmc/host/sdhci-pci-core.c:			jmicron_enable_mmc(chip->slots[i]->host, 0);
+drivers/mmc/host/sdhci-pci-core.c:	if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
+drivers/mmc/host/sdhci-pci-core.c:	    chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
+drivers/mmc/host/sdhci-pci-core.c:		for (i = 0; i < chip->num_slots; i++)
+drivers/mmc/host/sdhci-pci-core.c:			jmicron_enable_mmc(chip->slots[i]->host, 1);
+drivers/mmc/host/sdhci-pci-core.c:		dev_err(&chip->pdev->dev, "Failure enabling card power\n");
+drivers/mmc/host/sdhci-pci-core.c:	if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
+drivers/mmc/host/sdhci-pci-core.c:		chip->pdev->class &= ~0x0000FF;
+drivers/mmc/host/sdhci-pci-core.c:		chip->pdev->class |= PCI_SDHCI_IFDMA;
+drivers/mmc/host/sdhci-pci-core.c:	dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
+drivers/mmc/host/sdhci-pci-core.c:		dev_err(&slot->chip->pdev->dev,
+drivers/mmc/host/sdhci-pci-core.c:	if (chip->pdev->revision == 0x10)
+drivers/mmc/host/sdhci-pci-core.c:		chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
+drivers/mmc/host/sdhci-pci-core.c:	struct pci_dev *pdev = slot->chip->pdev;
+drivers/mmc/host/sdhci-pci-core.c:		chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
+drivers/mmc/host/sdhci-pci-core.c:	struct pci_dev *pdev = slot->chip->pdev;
+drivers/mmc/host/sdhci-pci-core.c:	pdev = slot->chip->pdev;
+drivers/mmc/host/sdhci-pci-core.c:	if (chip->fixes && chip->fixes->suspend)
+drivers/mmc/host/sdhci-pci-core.c:		return chip->fixes->suspend(chip);
+drivers/mmc/host/sdhci-pci-core.c:	if (chip->fixes && chip->fixes->resume)
+drivers/mmc/host/sdhci-pci-core.c:		return chip->fixes->resume(chip);
+drivers/mmc/host/sdhci-pci-core.c:	if (chip->fixes && chip->fixes->runtime_suspend)
+drivers/mmc/host/sdhci-pci-core.c:		return chip->fixes->runtime_suspend(chip);
+drivers/mmc/host/sdhci-pci-core.c:	if (chip->fixes && chip->fixes->runtime_resume)
+drivers/mmc/host/sdhci-pci-core.c:		return chip->fixes->runtime_resume(chip);
+drivers/mmc/host/sdhci-pci-core.c:	size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0;
+drivers/mmc/host/sdhci-pci-core.c:	host->ops = chip->fixes && chip->fixes->ops ?
+drivers/mmc/host/sdhci-pci-core.c:		    chip->fixes->ops :
+drivers/mmc/host/sdhci-pci-core.c:	host->quirks = chip->quirks;
+drivers/mmc/host/sdhci-pci-core.c:	host->quirks2 = chip->quirks2;
+drivers/mmc/host/sdhci-pci-core.c:	if (chip->fixes && chip->fixes->probe_slot) {
+drivers/mmc/host/sdhci-pci-core.c:		ret = chip->fixes->probe_slot(slot);
+drivers/mmc/host/sdhci-pci-core.c:	if (chip->fixes && chip->fixes->add_host)
+drivers/mmc/host/sdhci-pci-core.c:		ret = chip->fixes->add_host(slot);
+drivers/mmc/host/sdhci-pci-core.c:	if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
+drivers/mmc/host/sdhci-pci-core.c:		chip->allow_runtime_pm = false;
+drivers/mmc/host/sdhci-pci-core.c:	if (chip->fixes && chip->fixes->remove_slot)
+drivers/mmc/host/sdhci-pci-core.c:		chip->fixes->remove_slot(slot, 0);
+drivers/mmc/host/sdhci-pci-core.c:	if (slot->chip->fixes && slot->chip->fixes->remove_slot)
+drivers/mmc/host/sdhci-pci-core.c:		slot->chip->fixes->remove_slot(slot, dead);
+drivers/mmc/host/sdhci-pci-core.c:	chip->pdev = pdev;
+drivers/mmc/host/sdhci-pci-core.c:	chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
+drivers/mmc/host/sdhci-pci-core.c:	if (chip->fixes) {
+drivers/mmc/host/sdhci-pci-core.c:		chip->quirks = chip->fixes->quirks;
+drivers/mmc/host/sdhci-pci-core.c:		chip->quirks2 = chip->fixes->quirks2;
+drivers/mmc/host/sdhci-pci-core.c:		chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
+drivers/mmc/host/sdhci-pci-core.c:	chip->num_slots = slots;
+drivers/mmc/host/sdhci-pci-core.c:	chip->pm_retune = true;
+drivers/mmc/host/sdhci-pci-core.c:	chip->rpm_retune = true;
+drivers/mmc/host/sdhci-pci-core.c:	if (chip->fixes && chip->fixes->probe) {
+drivers/mmc/host/sdhci-pci-core.c:		ret = chip->fixes->probe(chip);
+drivers/mmc/host/sdhci-pci-core.c:	slots = chip->num_slots;	/* Quirk may have changed this */
+drivers/mmc/host/sdhci-pci-core.c:				sdhci_pci_remove_slot(chip->slots[i]);
+drivers/mmc/host/sdhci-pci-core.c:		chip->slots[i] = slot;
+drivers/mmc/host/sdhci-pci-core.c:	if (chip->allow_runtime_pm)
+drivers/mmc/host/sdhci-pci-core.c:	if (chip->allow_runtime_pm)
+drivers/mmc/host/sdhci-pci-core.c:	for (i = 0; i < chip->num_slots; i++)
+drivers/mmc/host/sdhci-pci-core.c:		sdhci_pci_remove_slot(chip->slots[i]);
+drivers/mmc/host/sdhci-pci-o2micro.c:	pci_read_config_dword(chip->pdev,
+drivers/mmc/host/sdhci-pci-o2micro.c:	pci_write_config_dword(chip->pdev,
+drivers/mmc/host/sdhci-pci-o2micro.c:	pci_read_config_byte(chip->pdev,
+drivers/mmc/host/sdhci-pci-o2micro.c:	pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
+drivers/mmc/host/sdhci-pci-o2micro.c:		pci_read_config_dword(chip->pdev,
+drivers/mmc/host/sdhci-pci-o2micro.c:		pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG4, scratch_32);
+drivers/mmc/host/sdhci-pci-o2micro.c:	pci_read_config_byte(chip->pdev,
+drivers/mmc/host/sdhci-pci-o2micro.c:	pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
+drivers/mmc/host/sdhci-pci-o2micro.c:	ret = pci_read_config_dword(chip->pdev,
+drivers/mmc/host/sdhci-pci-o2micro.c:	pci_write_config_dword(chip->pdev,
+drivers/mmc/host/sdhci-pci-o2micro.c:	ret = pci_read_config_dword(chip->pdev,
+drivers/mmc/host/sdhci-pci-o2micro.c:	pci_write_config_dword(chip->pdev,
+drivers/mmc/host/sdhci-pci-o2micro.c:	ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32);
+drivers/mmc/host/sdhci-pci-o2micro.c:	pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32);
+drivers/mmc/host/sdhci-pci-o2micro.c:	ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32);
+drivers/mmc/host/sdhci-pci-o2micro.c:	pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32);
+drivers/mmc/host/sdhci-pci-o2micro.c:	ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32);
+drivers/mmc/host/sdhci-pci-o2micro.c:	pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32);
+drivers/mmc/host/sdhci-pci-o2micro.c:	pci_write_config_dword(chip->pdev, O2_SD_DELAY_CTRL, 0x00002492);
+drivers/mmc/host/sdhci-pci-o2micro.c:	ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32);
+drivers/mmc/host/sdhci-pci-o2micro.c:	pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32);
+drivers/mmc/host/sdhci-pci-o2micro.c:	ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32);
+drivers/mmc/host/sdhci-pci-o2micro.c:	pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32);
+drivers/mmc/host/sdhci-pci-o2micro.c:	ret = pci_read_config_dword(chip->pdev,
+drivers/mmc/host/sdhci-pci-o2micro.c:	pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32);
+drivers/mmc/host/sdhci-pci-o2micro.c:	ret = pci_read_config_dword(chip->pdev,
+drivers/mmc/host/sdhci-pci-o2micro.c:	pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32);
+drivers/mmc/host/sdhci-pci-o2micro.c:	ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32);
+drivers/mmc/host/sdhci-pci-o2micro.c:	pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32);
+drivers/mmc/host/sdhci-pci-o2micro.c:	ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32);
+drivers/mmc/host/sdhci-pci-o2micro.c:	pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32);
+drivers/mmc/host/sdhci-pci-o2micro.c:	ret = pci_read_config_dword(chip->pdev,
+drivers/mmc/host/sdhci-pci-o2micro.c:	pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32);
+drivers/mmc/host/sdhci-pci-o2micro.c:	ret = pci_find_capability(chip->pdev, PCI_CAP_ID_MSI);
+drivers/mmc/host/sdhci-pci-o2micro.c:	ret = pci_alloc_irq_vectors(chip->pdev, 1, 1,
+drivers/mmc/host/sdhci-pci-o2micro.c:	host->irq = pci_irq_vector(chip->pdev, 0);
+drivers/mmc/host/sdhci-pci-o2micro.c:	switch (chip->pdev->device) {
+drivers/mmc/host/sdhci-pci-o2micro.c:		if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD0) {
+drivers/mmc/host/sdhci-pci-o2micro.c:			ret = pci_read_config_dword(chip->pdev,
+drivers/mmc/host/sdhci-pci-o2micro.c:				pci_write_config_dword(chip->pdev,
+drivers/mmc/host/sdhci-pci-o2micro.c:		if (chip->pdev->device != PCI_DEVICE_ID_O2_FUJIN2)
+drivers/mmc/host/sdhci-pci-o2micro.c:	switch (chip->pdev->device) {
+drivers/mmc/host/sdhci-pci-o2micro.c:		ret = pci_read_config_byte(chip->pdev,
+drivers/mmc/host/sdhci-pci-o2micro.c:		pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
+drivers/mmc/host/sdhci-pci-o2micro.c:		pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
+drivers/mmc/host/sdhci-pci-o2micro.c:		ret = pci_read_config_byte(chip->pdev,
+drivers/mmc/host/sdhci-pci-o2micro.c:		pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
+drivers/mmc/host/sdhci-pci-o2micro.c:		ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
+drivers/mmc/host/sdhci-pci-o2micro.c:		pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
+drivers/mmc/host/sdhci-pci-o2micro.c:		pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
+drivers/mmc/host/sdhci-pci-o2micro.c:		pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
+drivers/mmc/host/sdhci-pci-o2micro.c:		pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
+drivers/mmc/host/sdhci-pci-o2micro.c:		ret = pci_read_config_byte(chip->pdev,
+drivers/mmc/host/sdhci-pci-o2micro.c:		pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
+drivers/mmc/host/sdhci-pci-o2micro.c:		ret = pci_read_config_byte(chip->pdev,
+drivers/mmc/host/sdhci-pci-o2micro.c:		pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
+drivers/mmc/host/sdhci-pci-o2micro.c:		ret = pci_read_config_byte(chip->pdev,
+drivers/mmc/host/sdhci-pci-o2micro.c:		pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
+drivers/mmc/host/sdhci-pci-o2micro.c:		if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) {
+drivers/mmc/host/sdhci-pci-o2micro.c:			ret = pci_read_config_dword(chip->pdev,
+drivers/mmc/host/sdhci-pci-o2micro.c:				ret = pci_read_config_dword(chip->pdev,
+drivers/mmc/host/sdhci-pci-o2micro.c:				pci_write_config_dword(chip->pdev,
+drivers/mmc/host/sdhci-pci-o2micro.c:				pci_write_config_byte(chip->pdev,
+drivers/mmc/host/sdhci-pci-o2micro.c:		ret = pci_read_config_dword(chip->pdev,
+drivers/mmc/host/sdhci-pci-o2micro.c:		pci_write_config_dword(chip->pdev,
+drivers/mmc/host/sdhci-pci-o2micro.c:		ret = pci_read_config_dword(chip->pdev,
+drivers/mmc/host/sdhci-pci-o2micro.c:		pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32);
+drivers/mmc/host/sdhci-pci-o2micro.c:		ret = pci_read_config_dword(chip->pdev,
+drivers/mmc/host/sdhci-pci-o2micro.c:		pci_write_config_dword(chip->pdev,
+drivers/mmc/host/sdhci-pci-o2micro.c:		ret = pci_read_config_dword(chip->pdev,
+drivers/mmc/host/sdhci-pci-o2micro.c:		pci_write_config_dword(chip->pdev,
+drivers/mmc/host/sdhci-pci-o2micro.c:		if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2)
+drivers/mmc/host/sdhci-pci-o2micro.c:		ret = pci_read_config_byte(chip->pdev,
+drivers/mmc/host/sdhci-pci-o2micro.c:		pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
+drivers/mmc/host/sdhci-pci-o2micro.c:		ret = pci_read_config_byte(chip->pdev,
+drivers/mmc/host/sdhci-pci-o2micro.c:		pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
+drivers/mmc/host/sdhci-pci-o2micro.c:		ret = pci_read_config_dword(chip->pdev,
+drivers/mmc/host/sdhci-pci-o2micro.c:			pci_write_config_dword(chip->pdev,
+drivers/mmc/host/sdhci-pci-o2micro.c:			pci_write_config_dword(chip->pdev,
+drivers/mmc/host/sdhci-pci-o2micro.c:			ret = pci_read_config_dword(chip->pdev,
+drivers/mmc/host/sdhci-pci-o2micro.c:			pci_write_config_dword(chip->pdev,
+drivers/mmc/host/sdhci-pci-o2micro.c:		pci_write_config_byte(chip->pdev,
+drivers/mmc/host/sdhci-pci-o2micro.c:		ret = pci_read_config_byte(chip->pdev,
+drivers/mmc/host/sdhci-pci-o2micro.c:		pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
+drivers/mtd/chips/cfi_cmdset_0001.c:				chip->start += j << partshift;
+drivers/mtd/chips/cfi_cmdset_0001.c:				chip->priv = &shared[i];
+drivers/mtd/chips/cfi_cmdset_0001.c:				init_waitqueue_head(&chip->wq);
+drivers/mtd/chips/cfi_cmdset_0001.c:				mutex_init(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:	if (mode == FL_SYNCING && chip->oldstate != FL_READY)
+drivers/mtd/chips/cfi_cmdset_0001.c:	switch (chip->state) {
+drivers/mtd/chips/cfi_cmdset_0001.c:			if (chip->priv && map_word_andequal(map, status, status_PWS, status_PWS))
+drivers/mtd/chips/cfi_cmdset_0001.c:			mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:			mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:		if ((adr & chip->in_progress_block_mask) ==
+drivers/mtd/chips/cfi_cmdset_0001.c:		    chip->in_progress_block_addr)
+drivers/mtd/chips/cfi_cmdset_0001.c:		    (chip->in_progress_block_mask == ~(0x8000-1)))
+drivers/mtd/chips/cfi_cmdset_0001.c:		map_write(map, CMD(0xB0), chip->in_progress_block_addr);
+drivers/mtd/chips/cfi_cmdset_0001.c:		map_write(map, CMD(0x70), chip->in_progress_block_addr);
+drivers/mtd/chips/cfi_cmdset_0001.c:		chip->oldstate = FL_ERASING;
+drivers/mtd/chips/cfi_cmdset_0001.c:		chip->state = FL_ERASE_SUSPENDING;
+drivers/mtd/chips/cfi_cmdset_0001.c:		chip->erase_suspended = 1;
+drivers/mtd/chips/cfi_cmdset_0001.c:			status = map_read(map, chip->in_progress_block_addr);
+drivers/mtd/chips/cfi_cmdset_0001.c:			mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:			mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:		chip->state = FL_STATUS;
+drivers/mtd/chips/cfi_cmdset_0001.c:		chip->oldstate = chip->state;
+drivers/mtd/chips/cfi_cmdset_0001.c:		chip->state = FL_READY;
+drivers/mtd/chips/cfi_cmdset_0001.c:		if (mode == FL_READY && chip->oldstate == FL_READY)
+drivers/mtd/chips/cfi_cmdset_0001.c:		add_wait_queue(&chip->wq, &wait);
+drivers/mtd/chips/cfi_cmdset_0001.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:		remove_wait_queue(&chip->wq, &wait);
+drivers/mtd/chips/cfi_cmdset_0001.c:		mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:	if (chip->priv &&
+drivers/mtd/chips/cfi_cmdset_0001.c:	    || mode == FL_SHUTDOWN) && chip->state != FL_SYNCING) {
+drivers/mtd/chips/cfi_cmdset_0001.c:		struct flchip_shared *shared = chip->priv;
+drivers/mtd/chips/cfi_cmdset_0001.c:			mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:			mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:			if (chip->state == FL_SYNCING) {
+drivers/mtd/chips/cfi_cmdset_0001.c:			add_wait_queue(&chip->wq, &wait);
+drivers/mtd/chips/cfi_cmdset_0001.c:			mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:			remove_wait_queue(&chip->wq, &wait);
+drivers/mtd/chips/cfi_cmdset_0001.c:			mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:	if (chip->priv) {
+drivers/mtd/chips/cfi_cmdset_0001.c:		struct flchip_shared *shared = chip->priv;
+drivers/mtd/chips/cfi_cmdset_0001.c:		if (shared->writing == chip && chip->oldstate == FL_READY) {
+drivers/mtd/chips/cfi_cmdset_0001.c:				mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:				mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:				wake_up(&chip->wq);
+drivers/mtd/chips/cfi_cmdset_0001.c:			wake_up(&chip->wq);
+drivers/mtd/chips/cfi_cmdset_0001.c:	switch(chip->oldstate) {
+drivers/mtd/chips/cfi_cmdset_0001.c:		map_write(map, CMD(0xd0), chip->in_progress_block_addr);
+drivers/mtd/chips/cfi_cmdset_0001.c:		map_write(map, CMD(0x70), chip->in_progress_block_addr);
+drivers/mtd/chips/cfi_cmdset_0001.c:		chip->oldstate = FL_READY;
+drivers/mtd/chips/cfi_cmdset_0001.c:		chip->state = FL_ERASING;
+drivers/mtd/chips/cfi_cmdset_0001.c:		chip->state = chip->oldstate;
+drivers/mtd/chips/cfi_cmdset_0001.c:		chip->oldstate = FL_READY;
+drivers/mtd/chips/cfi_cmdset_0001.c:		printk(KERN_ERR "%s: put_chip() called with oldstate %d!!\n", map->name, chip->oldstate);
+drivers/mtd/chips/cfi_cmdset_0001.c:	wake_up(&chip->wq);
+drivers/mtd/chips/cfi_cmdset_0001.c:	if (chip->state != FL_POINT && chip->state != FL_READY) {
+drivers/mtd/chips/cfi_cmdset_0001.c:		chip->state = FL_READY;
+drivers/mtd/chips/cfi_cmdset_0001.c:		    ((chip->state == FL_ERASING && (cfip->FeatureSupport&2)) ||
+drivers/mtd/chips/cfi_cmdset_0001.c:		     (chip->state == FL_WRITING && (cfip->FeatureSupport&4))) &&
+drivers/mtd/chips/cfi_cmdset_0001.c:		    (cfi_interleave_is_1(cfi) || chip->oldstate == FL_READY)) {
+drivers/mtd/chips/cfi_cmdset_0001.c:			oldstate = chip->state;
+drivers/mtd/chips/cfi_cmdset_0001.c:				chip->erase_suspended = 1;
+drivers/mtd/chips/cfi_cmdset_0001.c:				chip->write_suspended = 1;
+drivers/mtd/chips/cfi_cmdset_0001.c:			chip->state = newstate;
+drivers/mtd/chips/cfi_cmdset_0001.c:			mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:			mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:			while (chip->state != newstate) {
+drivers/mtd/chips/cfi_cmdset_0001.c:				add_wait_queue(&chip->wq, &wait);
+drivers/mtd/chips/cfi_cmdset_0001.c:				mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:				remove_wait_queue(&chip->wq, &wait);
+drivers/mtd/chips/cfi_cmdset_0001.c:				mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:			chip->state = oldstate;
+drivers/mtd/chips/cfi_cmdset_0001.c:	int chip_state = chip->state;
+drivers/mtd/chips/cfi_cmdset_0001.c:	mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:	mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:		if (chip->state != chip_state) {
+drivers/mtd/chips/cfi_cmdset_0001.c:			add_wait_queue(&chip->wq, &wait);
+drivers/mtd/chips/cfi_cmdset_0001.c:			mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:			remove_wait_queue(&chip->wq, &wait);
+drivers/mtd/chips/cfi_cmdset_0001.c:			mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:		if (chip->erase_suspended && chip_state == FL_ERASING)  {
+drivers/mtd/chips/cfi_cmdset_0001.c:			chip->erase_suspended = 0;
+drivers/mtd/chips/cfi_cmdset_0001.c:		if (chip->write_suspended && chip_state == FL_WRITING)  {
+drivers/mtd/chips/cfi_cmdset_0001.c:			chip->write_suspended = 0;
+drivers/mtd/chips/cfi_cmdset_0001.c:			chip->state = FL_STATUS;
+drivers/mtd/chips/cfi_cmdset_0001.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:		mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c: 	chip->state = FL_STATUS;
+drivers/mtd/chips/cfi_cmdset_0001.c:	adr += chip->start;
+drivers/mtd/chips/cfi_cmdset_0001.c:	mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:		if (chip->state != FL_POINT && chip->state != FL_READY)
+drivers/mtd/chips/cfi_cmdset_0001.c:		chip->state = FL_POINT;
+drivers/mtd/chips/cfi_cmdset_0001.c:		chip->ref_point_counter++;
+drivers/mtd/chips/cfi_cmdset_0001.c:	mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:		mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:		if (chip->state == FL_POINT) {
+drivers/mtd/chips/cfi_cmdset_0001.c:			chip->ref_point_counter--;
+drivers/mtd/chips/cfi_cmdset_0001.c:			if(chip->ref_point_counter == 0)
+drivers/mtd/chips/cfi_cmdset_0001.c:				chip->state = FL_READY;
+drivers/mtd/chips/cfi_cmdset_0001.c:		put_chip(map, chip, chip->start);
+drivers/mtd/chips/cfi_cmdset_0001.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:	adr += chip->start;
+drivers/mtd/chips/cfi_cmdset_0001.c:	mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:	if (chip->state != FL_POINT && chip->state != FL_READY) {
+drivers/mtd/chips/cfi_cmdset_0001.c:		chip->state = FL_READY;
+drivers/mtd/chips/cfi_cmdset_0001.c:	mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:	adr += chip->start;
+drivers/mtd/chips/cfi_cmdset_0001.c:	mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:	chip->state = mode;
+drivers/mtd/chips/cfi_cmdset_0001.c:				   chip->word_write_time,
+drivers/mtd/chips/cfi_cmdset_0001.c:				   chip->word_write_time_max);
+drivers/mtd/chips/cfi_cmdset_0001.c:	mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:	adr += chip->start;
+drivers/mtd/chips/cfi_cmdset_0001.c:	mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:	if (chip->state != FL_STATUS) {
+drivers/mtd/chips/cfi_cmdset_0001.c:		chip->state = FL_STATUS;
+drivers/mtd/chips/cfi_cmdset_0001.c:	chip->state = FL_WRITING_TO_BUFFER;
+drivers/mtd/chips/cfi_cmdset_0001.c:		chip->state = FL_STATUS;
+drivers/mtd/chips/cfi_cmdset_0001.c:	chip->state = FL_WRITING;
+drivers/mtd/chips/cfi_cmdset_0001.c:				   chip->buffer_write_time,
+drivers/mtd/chips/cfi_cmdset_0001.c:				   chip->buffer_write_time_max);
+drivers/mtd/chips/cfi_cmdset_0001.c:		chip->state = FL_STATUS;
+drivers/mtd/chips/cfi_cmdset_0001.c:	mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:	adr += chip->start;
+drivers/mtd/chips/cfi_cmdset_0001.c:	mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:	chip->state = FL_ERASING;
+drivers/mtd/chips/cfi_cmdset_0001.c:	chip->erase_suspended = 0;
+drivers/mtd/chips/cfi_cmdset_0001.c:	chip->in_progress_block_addr = adr;
+drivers/mtd/chips/cfi_cmdset_0001.c:	chip->in_progress_block_mask = ~(len - 1);
+drivers/mtd/chips/cfi_cmdset_0001.c:				   chip->erase_time,
+drivers/mtd/chips/cfi_cmdset_0001.c:				   chip->erase_time_max);
+drivers/mtd/chips/cfi_cmdset_0001.c:		chip->state = FL_STATUS;
+drivers/mtd/chips/cfi_cmdset_0001.c:	chip->state = FL_STATUS;
+drivers/mtd/chips/cfi_cmdset_0001.c:			mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:	mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:		mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:		ret = get_chip(map, chip, chip->start, FL_SYNCING);
+drivers/mtd/chips/cfi_cmdset_0001.c:			chip->oldstate = chip->state;
+drivers/mtd/chips/cfi_cmdset_0001.c:			chip->state = FL_SYNCING;
+drivers/mtd/chips/cfi_cmdset_0001.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:		mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:		if (chip->state == FL_SYNCING) {
+drivers/mtd/chips/cfi_cmdset_0001.c:			chip->state = chip->oldstate;
+drivers/mtd/chips/cfi_cmdset_0001.c:			chip->oldstate = FL_READY;
+drivers/mtd/chips/cfi_cmdset_0001.c:			wake_up(&chip->wq);
+drivers/mtd/chips/cfi_cmdset_0001.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:	adr += chip->start;
+drivers/mtd/chips/cfi_cmdset_0001.c:	chip->state = FL_JEDEC_QUERY;
+drivers/mtd/chips/cfi_cmdset_0001.c:	adr += chip->start;
+drivers/mtd/chips/cfi_cmdset_0001.c:	mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:		chip->state = FL_LOCKING;
+drivers/mtd/chips/cfi_cmdset_0001.c:		chip->state = FL_UNLOCKING;
+drivers/mtd/chips/cfi_cmdset_0001.c:		chip->state = FL_STATUS;
+drivers/mtd/chips/cfi_cmdset_0001.c:	mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:	mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:	ret = get_chip(map, chip, chip->start, FL_JEDEC_QUERY);
+drivers/mtd/chips/cfi_cmdset_0001.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:	INVALIDATE_CACHED_RANGE(map, chip->start + offset, size);
+drivers/mtd/chips/cfi_cmdset_0001.c:	xip_disable(map, chip, chip->start);
+drivers/mtd/chips/cfi_cmdset_0001.c:	if (chip->state != FL_JEDEC_QUERY) {
+drivers/mtd/chips/cfi_cmdset_0001.c:		map_write(map, CMD(0x90), chip->start);
+drivers/mtd/chips/cfi_cmdset_0001.c:		chip->state = FL_JEDEC_QUERY;
+drivers/mtd/chips/cfi_cmdset_0001.c:	map_copy_from(map, buf, chip->start + offset, size);
+drivers/mtd/chips/cfi_cmdset_0001.c:	xip_enable(map, chip, chip->start);
+drivers/mtd/chips/cfi_cmdset_0001.c:	INVALIDATE_CACHED_RANGE(map, chip->start + offset, size);
+drivers/mtd/chips/cfi_cmdset_0001.c:	put_chip(map, chip, chip->start);
+drivers/mtd/chips/cfi_cmdset_0001.c:	mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:		mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:		switch (chip->state) {
+drivers/mtd/chips/cfi_cmdset_0001.c:			if (chip->oldstate == FL_READY) {
+drivers/mtd/chips/cfi_cmdset_0001.c:				chip->oldstate = chip->state;
+drivers/mtd/chips/cfi_cmdset_0001.c:				chip->state = FL_PM_SUSPENDED;
+drivers/mtd/chips/cfi_cmdset_0001.c:				printk(KERN_NOTICE "Flash device refused suspend due to pending operation (oldstate %d)\n", chip->oldstate);
+drivers/mtd/chips/cfi_cmdset_0001.c:			printk(KERN_NOTICE "Flash device refused suspend due to active operation (state %d)\n", chip->state);
+drivers/mtd/chips/cfi_cmdset_0001.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:			mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:			if (chip->state == FL_PM_SUSPENDED) {
+drivers/mtd/chips/cfi_cmdset_0001.c:				chip->state = chip->oldstate;
+drivers/mtd/chips/cfi_cmdset_0001.c:				chip->oldstate = FL_READY;
+drivers/mtd/chips/cfi_cmdset_0001.c:				wake_up(&chip->wq);
+drivers/mtd/chips/cfi_cmdset_0001.c:			mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:		mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:		if (chip->state == FL_PM_SUSPENDED) {
+drivers/mtd/chips/cfi_cmdset_0001.c:			chip->oldstate = chip->state = FL_READY;
+drivers/mtd/chips/cfi_cmdset_0001.c:			wake_up(&chip->wq);
+drivers/mtd/chips/cfi_cmdset_0001.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:		mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0001.c:		ret = get_chip(map, chip, chip->start, FL_SHUTDOWN);
+drivers/mtd/chips/cfi_cmdset_0001.c:			map_write(map, CMD(0xff), chip->start);
+drivers/mtd/chips/cfi_cmdset_0001.c:			chip->state = FL_SHUTDOWN;
+drivers/mtd/chips/cfi_cmdset_0001.c:			put_chip(map, chip, chip->start);
+drivers/mtd/chips/cfi_cmdset_0001.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:	cfi_send_gen_cmd(0x70, cfi->addr_unlock1, chip->start, map, cfi,
+drivers/mtd/chips/cfi_cmdset_0002.c:		cfi_send_gen_cmd(0x70, cfi->addr_unlock1, chip->start, map, cfi,
+drivers/mtd/chips/cfi_cmdset_0002.c:		cfi_send_gen_cmd(0x70, cfi->addr_unlock1, chip->start, map, cfi,
+drivers/mtd/chips/cfi_cmdset_0002.c:	switch (chip->state) {
+drivers/mtd/chips/cfi_cmdset_0002.c:			mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:			mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:		if ((adr & chip->in_progress_block_mask) ==
+drivers/mtd/chips/cfi_cmdset_0002.c:		    chip->in_progress_block_addr)
+drivers/mtd/chips/cfi_cmdset_0002.c:		map_write(map, CMD(0xB0), chip->in_progress_block_addr);
+drivers/mtd/chips/cfi_cmdset_0002.c:		chip->oldstate = FL_ERASING;
+drivers/mtd/chips/cfi_cmdset_0002.c:		chip->state = FL_ERASE_SUSPENDING;
+drivers/mtd/chips/cfi_cmdset_0002.c:		chip->erase_suspended = 1;
+drivers/mtd/chips/cfi_cmdset_0002.c:			mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:			mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:		chip->state = FL_READY;
+drivers/mtd/chips/cfi_cmdset_0002.c:		chip->oldstate = chip->state;
+drivers/mtd/chips/cfi_cmdset_0002.c:		chip->state = FL_READY;
+drivers/mtd/chips/cfi_cmdset_0002.c:		if (mode == FL_READY && chip->oldstate == FL_READY)
+drivers/mtd/chips/cfi_cmdset_0002.c:		add_wait_queue(&chip->wq, &wait);
+drivers/mtd/chips/cfi_cmdset_0002.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:		remove_wait_queue(&chip->wq, &wait);
+drivers/mtd/chips/cfi_cmdset_0002.c:		mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:	switch(chip->oldstate) {
+drivers/mtd/chips/cfi_cmdset_0002.c:			chip->in_progress_block_addr);
+drivers/mtd/chips/cfi_cmdset_0002.c:		map_write(map, cfi->sector_erase_cmd, chip->in_progress_block_addr);
+drivers/mtd/chips/cfi_cmdset_0002.c:		chip->oldstate = FL_READY;
+drivers/mtd/chips/cfi_cmdset_0002.c:		chip->state = FL_ERASING;
+drivers/mtd/chips/cfi_cmdset_0002.c:		chip->state = chip->oldstate;
+drivers/mtd/chips/cfi_cmdset_0002.c:		chip->oldstate = FL_READY;
+drivers/mtd/chips/cfi_cmdset_0002.c:		printk(KERN_ERR "MTD: put_chip() called with oldstate %d!!\n", chip->oldstate);
+drivers/mtd/chips/cfi_cmdset_0002.c:	wake_up(&chip->wq);
+drivers/mtd/chips/cfi_cmdset_0002.c:	if (chip->state != FL_POINT && chip->state != FL_READY) {
+drivers/mtd/chips/cfi_cmdset_0002.c:		chip->state = FL_READY;
+drivers/mtd/chips/cfi_cmdset_0002.c:		    ((chip->state == FL_ERASING && (extp->EraseSuspend & 2))) &&
+drivers/mtd/chips/cfi_cmdset_0002.c:		    (cfi_interleave_is_1(cfi) || chip->oldstate == FL_READY)) {
+drivers/mtd/chips/cfi_cmdset_0002.c:			oldstate = chip->state;
+drivers/mtd/chips/cfi_cmdset_0002.c:			chip->state = FL_XIP_WHILE_ERASING;
+drivers/mtd/chips/cfi_cmdset_0002.c:			chip->erase_suspended = 1;
+drivers/mtd/chips/cfi_cmdset_0002.c:			mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:			mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:			while (chip->state != FL_XIP_WHILE_ERASING) {
+drivers/mtd/chips/cfi_cmdset_0002.c:				add_wait_queue(&chip->wq, &wait);
+drivers/mtd/chips/cfi_cmdset_0002.c:				mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:				remove_wait_queue(&chip->wq, &wait);
+drivers/mtd/chips/cfi_cmdset_0002.c:				mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:			chip->state = oldstate;
+drivers/mtd/chips/cfi_cmdset_0002.c: * with chip->state set to FL_READY (or FL_XIP_WHILE_*) where flash state
+drivers/mtd/chips/cfi_cmdset_0002.c:	mutex_unlock(&chip->mutex);  \
+drivers/mtd/chips/cfi_cmdset_0002.c:	mutex_lock(&chip->mutex);  \
+drivers/mtd/chips/cfi_cmdset_0002.c:	mutex_unlock(&chip->mutex);  \
+drivers/mtd/chips/cfi_cmdset_0002.c:	mutex_lock(&chip->mutex);  \
+drivers/mtd/chips/cfi_cmdset_0002.c:	adr += chip->start;
+drivers/mtd/chips/cfi_cmdset_0002.c:	mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:	if (chip->state != FL_POINT && chip->state != FL_READY) {
+drivers/mtd/chips/cfi_cmdset_0002.c:		chip->state = FL_READY;
+drivers/mtd/chips/cfi_cmdset_0002.c:	mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:	cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
+drivers/mtd/chips/cfi_cmdset_0002.c:	cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
+drivers/mtd/chips/cfi_cmdset_0002.c:	cfi_send_gen_cmd(0x88, cfi->addr_unlock1, chip->start, map, cfi,
+drivers/mtd/chips/cfi_cmdset_0002.c:	INVALIDATE_CACHED_RANGE(map, chip->start + adr, len);
+drivers/mtd/chips/cfi_cmdset_0002.c:	cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
+drivers/mtd/chips/cfi_cmdset_0002.c:	cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
+drivers/mtd/chips/cfi_cmdset_0002.c:	cfi_send_gen_cmd(0x90, cfi->addr_unlock1, chip->start, map, cfi,
+drivers/mtd/chips/cfi_cmdset_0002.c:	cfi_send_gen_cmd(0x00, cfi->addr_unlock1, chip->start, map, cfi,
+drivers/mtd/chips/cfi_cmdset_0002.c:	INVALIDATE_CACHED_RANGE(map, chip->start + adr, len);
+drivers/mtd/chips/cfi_cmdset_0002.c:	mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:	if (chip->state != FL_READY){
+drivers/mtd/chips/cfi_cmdset_0002.c:		add_wait_queue(&chip->wq, &wait);
+drivers/mtd/chips/cfi_cmdset_0002.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:		remove_wait_queue(&chip->wq, &wait);
+drivers/mtd/chips/cfi_cmdset_0002.c:	adr += chip->start;
+drivers/mtd/chips/cfi_cmdset_0002.c:	chip->state = FL_READY;
+drivers/mtd/chips/cfi_cmdset_0002.c:	wake_up(&chip->wq);
+drivers/mtd/chips/cfi_cmdset_0002.c:	mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:	mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:	ret = get_chip(map, chip, chip->start, FL_LOCKING);
+drivers/mtd/chips/cfi_cmdset_0002.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:	chip->state = FL_LOCKING;
+drivers/mtd/chips/cfi_cmdset_0002.c:	cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
+drivers/mtd/chips/cfi_cmdset_0002.c:	cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
+drivers/mtd/chips/cfi_cmdset_0002.c:	cfi_send_gen_cmd(0x40, cfi->addr_unlock1, chip->start, map, cfi,
+drivers/mtd/chips/cfi_cmdset_0002.c:	map_write(map, CMD(0xA0), chip->start);
+drivers/mtd/chips/cfi_cmdset_0002.c:	map_write(map, CMD(lockreg), chip->start);
+drivers/mtd/chips/cfi_cmdset_0002.c:	map_write(map, CMD(0x90), chip->start);
+drivers/mtd/chips/cfi_cmdset_0002.c:	map_write(map, CMD(0x00), chip->start);
+drivers/mtd/chips/cfi_cmdset_0002.c:	chip->state = FL_READY;
+drivers/mtd/chips/cfi_cmdset_0002.c:	put_chip(map, chip, chip->start);
+drivers/mtd/chips/cfi_cmdset_0002.c:	mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:			base = chip->start;
+drivers/mtd/chips/cfi_cmdset_0002.c:			mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:				mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:			mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:				mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:					mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:						 chip->start, map, cfi,
+drivers/mtd/chips/cfi_cmdset_0002.c:						 chip->start, map, cfi,
+drivers/mtd/chips/cfi_cmdset_0002.c:						 chip->start, map, cfi,
+drivers/mtd/chips/cfi_cmdset_0002.c:				map_write(map, CMD(0x90), chip->start);
+drivers/mtd/chips/cfi_cmdset_0002.c:				map_write(map, CMD(0x00), chip->start);
+drivers/mtd/chips/cfi_cmdset_0002.c:				put_chip(map, chip, chip->start);
+drivers/mtd/chips/cfi_cmdset_0002.c:				mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:	cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
+drivers/mtd/chips/cfi_cmdset_0002.c:	cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
+drivers/mtd/chips/cfi_cmdset_0002.c:	cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
+drivers/mtd/chips/cfi_cmdset_0002.c:	chip->state = mode;
+drivers/mtd/chips/cfi_cmdset_0002.c:				chip->word_write_time);
+drivers/mtd/chips/cfi_cmdset_0002.c:		if (chip->state != mode) {
+drivers/mtd/chips/cfi_cmdset_0002.c:			add_wait_queue(&chip->wq, &wait);
+drivers/mtd/chips/cfi_cmdset_0002.c:			mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:			remove_wait_queue(&chip->wq, &wait);
+drivers/mtd/chips/cfi_cmdset_0002.c:			mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:	mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:	chip->state = FL_READY;
+drivers/mtd/chips/cfi_cmdset_0002.c:	mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:		map_write(map, CMD(0xF0), chip->start);
+drivers/mtd/chips/cfi_cmdset_0002.c:	adr += chip->start;
+drivers/mtd/chips/cfi_cmdset_0002.c:	u_write_timeout = usecs_to_jiffies(chip->buffer_write_time_max);
+drivers/mtd/chips/cfi_cmdset_0002.c:		if (chip->state != FL_WRITING) {
+drivers/mtd/chips/cfi_cmdset_0002.c:			add_wait_queue(&chip->wq, &wait);
+drivers/mtd/chips/cfi_cmdset_0002.c:			mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:			remove_wait_queue(&chip->wq, &wait);
+drivers/mtd/chips/cfi_cmdset_0002.c:			mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:	cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
+drivers/mtd/chips/cfi_cmdset_0002.c:	cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
+drivers/mtd/chips/cfi_cmdset_0002.c:	cfi_send_gen_cmd(0xF0, cfi->addr_unlock1, chip->start, map, cfi,
+drivers/mtd/chips/cfi_cmdset_0002.c:	adr += chip->start;
+drivers/mtd/chips/cfi_cmdset_0002.c:	mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:	cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
+drivers/mtd/chips/cfi_cmdset_0002.c:	cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
+drivers/mtd/chips/cfi_cmdset_0002.c:	chip->state = FL_WRITING_TO_BUFFER;
+drivers/mtd/chips/cfi_cmdset_0002.c:	chip->state = FL_WRITING;
+drivers/mtd/chips/cfi_cmdset_0002.c:				chip->word_write_time);
+drivers/mtd/chips/cfi_cmdset_0002.c:	chip->state = FL_READY;
+drivers/mtd/chips/cfi_cmdset_0002.c:	mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:	if (chip->state == FL_READY && chip_ready(map, chip, adr))
+drivers/mtd/chips/cfi_cmdset_0002.c:		map_write(map, CMD(0xF0), chip->start);
+drivers/mtd/chips/cfi_cmdset_0002.c:	adr += chip->start;
+drivers/mtd/chips/cfi_cmdset_0002.c:	cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
+drivers/mtd/chips/cfi_cmdset_0002.c:	cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
+drivers/mtd/chips/cfi_cmdset_0002.c:	cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
+drivers/mtd/chips/cfi_cmdset_0002.c:		map_write(map, CMD(0xF0), chip->start);
+drivers/mtd/chips/cfi_cmdset_0002.c:	mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:	       __func__, chip->start);
+drivers/mtd/chips/cfi_cmdset_0002.c:	cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
+drivers/mtd/chips/cfi_cmdset_0002.c:	cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
+drivers/mtd/chips/cfi_cmdset_0002.c:	cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
+drivers/mtd/chips/cfi_cmdset_0002.c:	cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
+drivers/mtd/chips/cfi_cmdset_0002.c:	cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
+drivers/mtd/chips/cfi_cmdset_0002.c:	cfi_send_gen_cmd(0x10, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
+drivers/mtd/chips/cfi_cmdset_0002.c:	chip->state = FL_ERASING;
+drivers/mtd/chips/cfi_cmdset_0002.c:	chip->erase_suspended = 0;
+drivers/mtd/chips/cfi_cmdset_0002.c:	chip->in_progress_block_addr = adr;
+drivers/mtd/chips/cfi_cmdset_0002.c:	chip->in_progress_block_mask = ~(map->size - 1);
+drivers/mtd/chips/cfi_cmdset_0002.c:				chip->erase_time*500);
+drivers/mtd/chips/cfi_cmdset_0002.c:		if (chip->state != FL_ERASING) {
+drivers/mtd/chips/cfi_cmdset_0002.c:			add_wait_queue(&chip->wq, &wait);
+drivers/mtd/chips/cfi_cmdset_0002.c:			mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:			remove_wait_queue(&chip->wq, &wait);
+drivers/mtd/chips/cfi_cmdset_0002.c:			mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:		if (chip->erase_suspended) {
+drivers/mtd/chips/cfi_cmdset_0002.c:			chip->erase_suspended = 0;
+drivers/mtd/chips/cfi_cmdset_0002.c:		map_write(map, CMD(0xF0), chip->start);
+drivers/mtd/chips/cfi_cmdset_0002.c:	chip->state = FL_READY;
+drivers/mtd/chips/cfi_cmdset_0002.c:	mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:	adr += chip->start;
+drivers/mtd/chips/cfi_cmdset_0002.c:	mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:	cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
+drivers/mtd/chips/cfi_cmdset_0002.c:	cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
+drivers/mtd/chips/cfi_cmdset_0002.c:	cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
+drivers/mtd/chips/cfi_cmdset_0002.c:	cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
+drivers/mtd/chips/cfi_cmdset_0002.c:	cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
+drivers/mtd/chips/cfi_cmdset_0002.c:	chip->state = FL_ERASING;
+drivers/mtd/chips/cfi_cmdset_0002.c:	chip->erase_suspended = 0;
+drivers/mtd/chips/cfi_cmdset_0002.c:	chip->in_progress_block_addr = adr;
+drivers/mtd/chips/cfi_cmdset_0002.c:	chip->in_progress_block_mask = ~(len - 1);
+drivers/mtd/chips/cfi_cmdset_0002.c:				chip->erase_time*500);
+drivers/mtd/chips/cfi_cmdset_0002.c:		if (chip->state != FL_ERASING) {
+drivers/mtd/chips/cfi_cmdset_0002.c:			add_wait_queue(&chip->wq, &wait);
+drivers/mtd/chips/cfi_cmdset_0002.c:			mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:			remove_wait_queue(&chip->wq, &wait);
+drivers/mtd/chips/cfi_cmdset_0002.c:			mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:		if (chip->erase_suspended) {
+drivers/mtd/chips/cfi_cmdset_0002.c:			chip->erase_suspended = 0;
+drivers/mtd/chips/cfi_cmdset_0002.c:		map_write(map, CMD(0xF0), chip->start);
+drivers/mtd/chips/cfi_cmdset_0002.c:	chip->state = FL_READY;
+drivers/mtd/chips/cfi_cmdset_0002.c:	mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:	mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:	ret = get_chip(map, chip, adr + chip->start, FL_LOCKING);
+drivers/mtd/chips/cfi_cmdset_0002.c:	chip->state = FL_LOCKING;
+drivers/mtd/chips/cfi_cmdset_0002.c:	cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
+drivers/mtd/chips/cfi_cmdset_0002.c:	cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
+drivers/mtd/chips/cfi_cmdset_0002.c:	cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi,
+drivers/mtd/chips/cfi_cmdset_0002.c:	cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
+drivers/mtd/chips/cfi_cmdset_0002.c:	cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
+drivers/mtd/chips/cfi_cmdset_0002.c:	map_write(map, CMD(0x40), chip->start + adr);
+drivers/mtd/chips/cfi_cmdset_0002.c:	chip->state = FL_READY;
+drivers/mtd/chips/cfi_cmdset_0002.c:	put_chip(map, chip, adr + chip->start);
+drivers/mtd/chips/cfi_cmdset_0002.c:	mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:	mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:	ret = get_chip(map, chip, adr + chip->start, FL_UNLOCKING);
+drivers/mtd/chips/cfi_cmdset_0002.c:	chip->state = FL_UNLOCKING;
+drivers/mtd/chips/cfi_cmdset_0002.c:	cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
+drivers/mtd/chips/cfi_cmdset_0002.c:	chip->state = FL_READY;
+drivers/mtd/chips/cfi_cmdset_0002.c:	put_chip(map, chip, adr + chip->start);
+drivers/mtd/chips/cfi_cmdset_0002.c:	mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:	adr += chip->start;
+drivers/mtd/chips/cfi_cmdset_0002.c:	mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:	cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
+drivers/mtd/chips/cfi_cmdset_0002.c:	cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
+drivers/mtd/chips/cfi_cmdset_0002.c:	cfi_send_gen_cmd(0xC0, cfi->addr_unlock1, chip->start, map, cfi,
+drivers/mtd/chips/cfi_cmdset_0002.c:		chip->state = FL_LOCKING;
+drivers/mtd/chips/cfi_cmdset_0002.c:		chip->state = FL_UNLOCKING;
+drivers/mtd/chips/cfi_cmdset_0002.c:		map_write(map, CMD(0x80), chip->start);
+drivers/mtd/chips/cfi_cmdset_0002.c:		map_write(map, CMD(0x30), chip->start);
+drivers/mtd/chips/cfi_cmdset_0002.c:		chip->state = FL_JEDEC_QUERY;
+drivers/mtd/chips/cfi_cmdset_0002.c:	map_write(map, CMD(0x90), chip->start);
+drivers/mtd/chips/cfi_cmdset_0002.c:	map_write(map, CMD(0x00), chip->start);
+drivers/mtd/chips/cfi_cmdset_0002.c:	chip->state = FL_READY;
+drivers/mtd/chips/cfi_cmdset_0002.c:	mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:		mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:		switch(chip->state) {
+drivers/mtd/chips/cfi_cmdset_0002.c:			chip->oldstate = chip->state;
+drivers/mtd/chips/cfi_cmdset_0002.c:			chip->state = FL_SYNCING;
+drivers/mtd/chips/cfi_cmdset_0002.c:			mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:			add_wait_queue(&chip->wq, &wait);
+drivers/mtd/chips/cfi_cmdset_0002.c:			mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:			remove_wait_queue(&chip->wq, &wait);
+drivers/mtd/chips/cfi_cmdset_0002.c:		mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:		if (chip->state == FL_SYNCING) {
+drivers/mtd/chips/cfi_cmdset_0002.c:			chip->state = chip->oldstate;
+drivers/mtd/chips/cfi_cmdset_0002.c:			wake_up(&chip->wq);
+drivers/mtd/chips/cfi_cmdset_0002.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:		mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:		switch(chip->state) {
+drivers/mtd/chips/cfi_cmdset_0002.c:			chip->oldstate = chip->state;
+drivers/mtd/chips/cfi_cmdset_0002.c:			chip->state = FL_PM_SUSPENDED;
+drivers/mtd/chips/cfi_cmdset_0002.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:			mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:			if (chip->state == FL_PM_SUSPENDED) {
+drivers/mtd/chips/cfi_cmdset_0002.c:				chip->state = chip->oldstate;
+drivers/mtd/chips/cfi_cmdset_0002.c:				wake_up(&chip->wq);
+drivers/mtd/chips/cfi_cmdset_0002.c:			mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:		mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:		if (chip->state == FL_PM_SUSPENDED) {
+drivers/mtd/chips/cfi_cmdset_0002.c:			chip->state = FL_READY;
+drivers/mtd/chips/cfi_cmdset_0002.c:			map_write(map, CMD(0xF0), chip->start);
+drivers/mtd/chips/cfi_cmdset_0002.c:			wake_up(&chip->wq);
+drivers/mtd/chips/cfi_cmdset_0002.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:		mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0002.c:		ret = get_chip(map, chip, chip->start, FL_SHUTDOWN);
+drivers/mtd/chips/cfi_cmdset_0002.c:			map_write(map, CMD(0xF0), chip->start);
+drivers/mtd/chips/cfi_cmdset_0002.c:			chip->state = FL_SHUTDOWN;
+drivers/mtd/chips/cfi_cmdset_0002.c:			put_chip(map, chip, chip->start);
+drivers/mtd/chips/cfi_cmdset_0002.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:	adr += chip->start;
+drivers/mtd/chips/cfi_cmdset_0020.c:	mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:	switch (chip->state) {
+drivers/mtd/chips/cfi_cmdset_0020.c:		chip->oldstate = FL_ERASING;
+drivers/mtd/chips/cfi_cmdset_0020.c:		chip->state = FL_ERASE_SUSPENDING;
+drivers/mtd/chips/cfi_cmdset_0020.c:				chip->state = FL_ERASING;
+drivers/mtd/chips/cfi_cmdset_0020.c:				wake_up(&chip->wq);
+drivers/mtd/chips/cfi_cmdset_0020.c:				mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:			mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:			mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:		chip->state = FL_READY;
+drivers/mtd/chips/cfi_cmdset_0020.c:		chip->state = FL_STATUS;
+drivers/mtd/chips/cfi_cmdset_0020.c:			chip->state = FL_READY;
+drivers/mtd/chips/cfi_cmdset_0020.c:			mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:		add_wait_queue(&chip->wq, &wait);
+drivers/mtd/chips/cfi_cmdset_0020.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:		remove_wait_queue(&chip->wq, &wait);
+drivers/mtd/chips/cfi_cmdset_0020.c:		chip->state = chip->oldstate;
+drivers/mtd/chips/cfi_cmdset_0020.c:	wake_up(&chip->wq);
+drivers/mtd/chips/cfi_cmdset_0020.c:	mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:        adr += chip->start;
+drivers/mtd/chips/cfi_cmdset_0020.c:       printk("%s: chip->state[%d]\n", __func__, chip->state);
+drivers/mtd/chips/cfi_cmdset_0020.c:	mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:	switch (chip->state) {
+drivers/mtd/chips/cfi_cmdset_0020.c:                chip->state = FL_STATUS;
+drivers/mtd/chips/cfi_cmdset_0020.c:			mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:		add_wait_queue(&chip->wq, &wait);
+drivers/mtd/chips/cfi_cmdset_0020.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:		remove_wait_queue(&chip->wq, &wait);
+drivers/mtd/chips/cfi_cmdset_0020.c:	chip->state = FL_WRITING_TO_BUFFER;
+drivers/mtd/chips/cfi_cmdset_0020.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:		mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:			chip->state = FL_STATUS;
+drivers/mtd/chips/cfi_cmdset_0020.c:			mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:	chip->state = FL_WRITING;
+drivers/mtd/chips/cfi_cmdset_0020.c:	mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:	cfi_udelay(chip->buffer_write_time);
+drivers/mtd/chips/cfi_cmdset_0020.c:	mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:		if (chip->state != FL_WRITING) {
+drivers/mtd/chips/cfi_cmdset_0020.c:			add_wait_queue(&chip->wq, &wait);
+drivers/mtd/chips/cfi_cmdset_0020.c:			mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:			remove_wait_queue(&chip->wq, &wait);
+drivers/mtd/chips/cfi_cmdset_0020.c:			mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:			chip->state = FL_STATUS;
+drivers/mtd/chips/cfi_cmdset_0020.c:			mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:		mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:		chip->buffer_write_time--;
+drivers/mtd/chips/cfi_cmdset_0020.c:		if (!chip->buffer_write_time)
+drivers/mtd/chips/cfi_cmdset_0020.c:			chip->buffer_write_time++;
+drivers/mtd/chips/cfi_cmdset_0020.c:		chip->buffer_write_time++;
+drivers/mtd/chips/cfi_cmdset_0020.c:	chip->state = FL_STATUS;
+drivers/mtd/chips/cfi_cmdset_0020.c:		wake_up(&chip->wq);
+drivers/mtd/chips/cfi_cmdset_0020.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:	wake_up(&chip->wq);
+drivers/mtd/chips/cfi_cmdset_0020.c:	mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:	adr += chip->start;
+drivers/mtd/chips/cfi_cmdset_0020.c:	mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:	switch (chip->state) {
+drivers/mtd/chips/cfi_cmdset_0020.c:		chip->state = FL_STATUS;
+drivers/mtd/chips/cfi_cmdset_0020.c:			mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:		add_wait_queue(&chip->wq, &wait);
+drivers/mtd/chips/cfi_cmdset_0020.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:		remove_wait_queue(&chip->wq, &wait);
+drivers/mtd/chips/cfi_cmdset_0020.c:	chip->state = FL_ERASING;
+drivers/mtd/chips/cfi_cmdset_0020.c:	mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:	mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:		if (chip->state != FL_ERASING) {
+drivers/mtd/chips/cfi_cmdset_0020.c:			add_wait_queue(&chip->wq, &wait);
+drivers/mtd/chips/cfi_cmdset_0020.c:			mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:			remove_wait_queue(&chip->wq, &wait);
+drivers/mtd/chips/cfi_cmdset_0020.c:			mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:			chip->state = FL_STATUS;
+drivers/mtd/chips/cfi_cmdset_0020.c:			mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:		mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:	chip->state = FL_STATUS;
+drivers/mtd/chips/cfi_cmdset_0020.c:				chip->state = FL_STATUS;
+drivers/mtd/chips/cfi_cmdset_0020.c:				mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:	wake_up(&chip->wq);
+drivers/mtd/chips/cfi_cmdset_0020.c:	mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:		mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:		switch(chip->state) {
+drivers/mtd/chips/cfi_cmdset_0020.c:			chip->oldstate = chip->state;
+drivers/mtd/chips/cfi_cmdset_0020.c:			chip->state = FL_SYNCING;
+drivers/mtd/chips/cfi_cmdset_0020.c:			mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:			add_wait_queue(&chip->wq, &wait);
+drivers/mtd/chips/cfi_cmdset_0020.c:			mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:		        remove_wait_queue(&chip->wq, &wait);
+drivers/mtd/chips/cfi_cmdset_0020.c:		mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:		if (chip->state == FL_SYNCING) {
+drivers/mtd/chips/cfi_cmdset_0020.c:			chip->state = chip->oldstate;
+drivers/mtd/chips/cfi_cmdset_0020.c:			wake_up(&chip->wq);
+drivers/mtd/chips/cfi_cmdset_0020.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:	adr += chip->start;
+drivers/mtd/chips/cfi_cmdset_0020.c:	mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:	switch (chip->state) {
+drivers/mtd/chips/cfi_cmdset_0020.c:		chip->state = FL_STATUS;
+drivers/mtd/chips/cfi_cmdset_0020.c:			mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:		add_wait_queue(&chip->wq, &wait);
+drivers/mtd/chips/cfi_cmdset_0020.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:		remove_wait_queue(&chip->wq, &wait);
+drivers/mtd/chips/cfi_cmdset_0020.c:	chip->state = FL_LOCKING;
+drivers/mtd/chips/cfi_cmdset_0020.c:	mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:	mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:			chip->state = FL_STATUS;
+drivers/mtd/chips/cfi_cmdset_0020.c:			mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:		mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:	chip->state = FL_STATUS;
+drivers/mtd/chips/cfi_cmdset_0020.c:	wake_up(&chip->wq);
+drivers/mtd/chips/cfi_cmdset_0020.c:	mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:	adr += chip->start;
+drivers/mtd/chips/cfi_cmdset_0020.c:	mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:	switch (chip->state) {
+drivers/mtd/chips/cfi_cmdset_0020.c:		chip->state = FL_STATUS;
+drivers/mtd/chips/cfi_cmdset_0020.c:			mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:		add_wait_queue(&chip->wq, &wait);
+drivers/mtd/chips/cfi_cmdset_0020.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:		remove_wait_queue(&chip->wq, &wait);
+drivers/mtd/chips/cfi_cmdset_0020.c:	chip->state = FL_UNLOCKING;
+drivers/mtd/chips/cfi_cmdset_0020.c:	mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:	mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:			chip->state = FL_STATUS;
+drivers/mtd/chips/cfi_cmdset_0020.c:			mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:		mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:	chip->state = FL_STATUS;
+drivers/mtd/chips/cfi_cmdset_0020.c:	wake_up(&chip->wq);
+drivers/mtd/chips/cfi_cmdset_0020.c:	mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:		mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:		switch(chip->state) {
+drivers/mtd/chips/cfi_cmdset_0020.c:			chip->oldstate = chip->state;
+drivers/mtd/chips/cfi_cmdset_0020.c:			chip->state = FL_PM_SUSPENDED;
+drivers/mtd/chips/cfi_cmdset_0020.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:			mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:			if (chip->state == FL_PM_SUSPENDED) {
+drivers/mtd/chips/cfi_cmdset_0020.c:				chip->state = chip->oldstate;
+drivers/mtd/chips/cfi_cmdset_0020.c:				wake_up(&chip->wq);
+drivers/mtd/chips/cfi_cmdset_0020.c:			mutex_unlock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:		mutex_lock(&chip->mutex);
+drivers/mtd/chips/cfi_cmdset_0020.c:		if (chip->state == FL_PM_SUSPENDED) {
+drivers/mtd/chips/cfi_cmdset_0020.c:			chip->state = FL_READY;
+drivers/mtd/chips/cfi_cmdset_0020.c:			wake_up(&chip->wq);
+drivers/mtd/chips/cfi_cmdset_0020.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/fwh_lock.h:	if (chip->start < 0x400000) {
+drivers/mtd/chips/fwh_lock.h:		pr_debug( "MTD %s(): chip->start: %lx wanted >= 0x400000\n",
+drivers/mtd/chips/fwh_lock.h:			__func__, chip->start );
+drivers/mtd/chips/fwh_lock.h:	adr += chip->start - 0x400000;
+drivers/mtd/chips/fwh_lock.h:	mutex_lock(&chip->mutex);
+drivers/mtd/chips/fwh_lock.h:		mutex_unlock(&chip->mutex);
+drivers/mtd/chips/fwh_lock.h:	chip->oldstate = chip->state;
+drivers/mtd/chips/fwh_lock.h:	chip->state = xxlt->state;
+drivers/mtd/chips/fwh_lock.h:	chip->state = chip->oldstate;
+drivers/mtd/chips/fwh_lock.h:	mutex_unlock(&chip->mutex);
+drivers/mtd/chips/gen_probe.c:			pchip->start = (i << cfi.chipshift);
+drivers/mtd/chips/gen_probe.c:			pchip->state = FL_READY;
+drivers/mtd/chips/gen_probe.c:			init_waitqueue_head(&pchip->wq);
+drivers/mtd/chips/gen_probe.c:			mutex_init(&pchip->mutex);
+drivers/mtd/devices/docg3.c:	{ .compatible = "m-systems,diskonchip-g3" },
+drivers/mtd/devices/spear_smi.c:	/* Matches chip-id to entire list of 'serial-nor flash' ids */
+drivers/mtd/lpddr/lpddr_cmds.c:			chip->start += j << lpddr->chipshift;
+drivers/mtd/lpddr/lpddr_cmds.c:			chip->oldstate = chip->state = FL_READY;
+drivers/mtd/lpddr/lpddr_cmds.c:			chip->priv = &shared[i];
+drivers/mtd/lpddr/lpddr_cmds.c:			init_waitqueue_head(&chip->wq);
+drivers/mtd/lpddr/lpddr_cmds.c:			mutex_init(&chip->mutex);
+drivers/mtd/lpddr/lpddr_cmds.c:	flstate_t chip_state = chip->state;
+drivers/mtd/lpddr/lpddr_cmds.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/lpddr/lpddr_cmds.c:		mutex_lock(&chip->mutex);
+drivers/mtd/lpddr/lpddr_cmds.c:		while (chip->state != chip_state) {
+drivers/mtd/lpddr/lpddr_cmds.c:			add_wait_queue(&chip->wq, &wait);
+drivers/mtd/lpddr/lpddr_cmds.c:			mutex_unlock(&chip->mutex);
+drivers/mtd/lpddr/lpddr_cmds.c:			remove_wait_queue(&chip->wq, &wait);
+drivers/mtd/lpddr/lpddr_cmds.c:			mutex_lock(&chip->mutex);
+drivers/mtd/lpddr/lpddr_cmds.c:		if (chip->erase_suspended || chip->write_suspended)  {
+drivers/mtd/lpddr/lpddr_cmds.c:			chip->erase_suspended = chip->write_suspended = 0;
+drivers/mtd/lpddr/lpddr_cmds.c:	chip->state = FL_READY;
+drivers/mtd/lpddr/lpddr_cmds.c:	if (chip->priv && (mode == FL_WRITING || mode == FL_ERASING)
+drivers/mtd/lpddr/lpddr_cmds.c:		&& chip->state != FL_SYNCING) {
+drivers/mtd/lpddr/lpddr_cmds.c:		struct flchip_shared *shared = chip->priv;
+drivers/mtd/lpddr/lpddr_cmds.c:			mutex_unlock(&chip->mutex);
+drivers/mtd/lpddr/lpddr_cmds.c:			mutex_lock(&chip->mutex);
+drivers/mtd/lpddr/lpddr_cmds.c:			if (chip->state == FL_SYNCING) {
+drivers/mtd/lpddr/lpddr_cmds.c:			add_wait_queue(&chip->wq, &wait);
+drivers/mtd/lpddr/lpddr_cmds.c:			mutex_unlock(&chip->mutex);
+drivers/mtd/lpddr/lpddr_cmds.c:			remove_wait_queue(&chip->wq, &wait);
+drivers/mtd/lpddr/lpddr_cmds.c:			mutex_lock(&chip->mutex);
+drivers/mtd/lpddr/lpddr_cmds.c:	if (FL_SYNCING == mode && FL_READY != chip->oldstate)
+drivers/mtd/lpddr/lpddr_cmds.c:	switch (chip->state) {
+drivers/mtd/lpddr/lpddr_cmds.c:		chip->oldstate = FL_ERASING;
+drivers/mtd/lpddr/lpddr_cmds.c:		chip->state = FL_ERASE_SUSPENDING;
+drivers/mtd/lpddr/lpddr_cmds.c:		chip->erase_suspended = 1;
+drivers/mtd/lpddr/lpddr_cmds.c:		chip->state = FL_READY;
+drivers/mtd/lpddr/lpddr_cmds.c:		if (mode == FL_READY && chip->oldstate == FL_READY)
+drivers/mtd/lpddr/lpddr_cmds.c:		add_wait_queue(&chip->wq, &wait);
+drivers/mtd/lpddr/lpddr_cmds.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/lpddr/lpddr_cmds.c:		remove_wait_queue(&chip->wq, &wait);
+drivers/mtd/lpddr/lpddr_cmds.c:		mutex_lock(&chip->mutex);
+drivers/mtd/lpddr/lpddr_cmds.c:	if (chip->priv) {
+drivers/mtd/lpddr/lpddr_cmds.c:		struct flchip_shared *shared = chip->priv;
+drivers/mtd/lpddr/lpddr_cmds.c:		if (shared->writing == chip && chip->oldstate == FL_READY) {
+drivers/mtd/lpddr/lpddr_cmds.c:				mutex_unlock(&chip->mutex);
+drivers/mtd/lpddr/lpddr_cmds.c:				mutex_lock(&chip->mutex);
+drivers/mtd/lpddr/lpddr_cmds.c:				wake_up(&chip->wq);
+drivers/mtd/lpddr/lpddr_cmds.c:			wake_up(&chip->wq);
+drivers/mtd/lpddr/lpddr_cmds.c:	switch (chip->oldstate) {
+drivers/mtd/lpddr/lpddr_cmds.c:		chip->oldstate = FL_READY;
+drivers/mtd/lpddr/lpddr_cmds.c:		chip->state = FL_ERASING;
+drivers/mtd/lpddr/lpddr_cmds.c:				map->name, chip->oldstate);
+drivers/mtd/lpddr/lpddr_cmds.c:	wake_up(&chip->wq);
+drivers/mtd/lpddr/lpddr_cmds.c:	mutex_lock(&chip->mutex);
+drivers/mtd/lpddr/lpddr_cmds.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/lpddr/lpddr_cmds.c:	chip->state = FL_WRITING;
+drivers/mtd/lpddr/lpddr_cmds.c:	mutex_unlock(&chip->mutex);
+drivers/mtd/lpddr/lpddr_cmds.c:	mutex_lock(&chip->mutex);
+drivers/mtd/lpddr/lpddr_cmds.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/lpddr/lpddr_cmds.c:	chip->state = FL_ERASING;
+drivers/mtd/lpddr/lpddr_cmds.c:	mutex_unlock(&chip->mutex);
+drivers/mtd/lpddr/lpddr_cmds.c:	mutex_lock(&chip->mutex);
+drivers/mtd/lpddr/lpddr_cmds.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/lpddr/lpddr_cmds.c:	mutex_unlock(&chip->mutex);
+drivers/mtd/lpddr/lpddr_cmds.c:	*mtdbuf = (void *)map->virt + chip->start + ofs;
+drivers/mtd/lpddr/lpddr_cmds.c:			last_end = chip->start;
+drivers/mtd/lpddr/lpddr_cmds.c:		else if (chip->start != last_end)
+drivers/mtd/lpddr/lpddr_cmds.c:		mutex_lock(&chip->mutex);
+drivers/mtd/lpddr/lpddr_cmds.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/lpddr/lpddr_cmds.c:		chip->state = FL_POINT;
+drivers/mtd/lpddr/lpddr_cmds.c:		chip->ref_point_counter++;
+drivers/mtd/lpddr/lpddr_cmds.c:		mutex_lock(&chip->mutex);
+drivers/mtd/lpddr/lpddr_cmds.c:		if (chip->state == FL_POINT) {
+drivers/mtd/lpddr/lpddr_cmds.c:			chip->ref_point_counter--;
+drivers/mtd/lpddr/lpddr_cmds.c:			if (chip->ref_point_counter == 0)
+drivers/mtd/lpddr/lpddr_cmds.c:				chip->state = FL_READY;
+drivers/mtd/lpddr/lpddr_cmds.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/lpddr/lpddr_cmds.c:	mutex_lock(&chip->mutex);
+drivers/mtd/lpddr/lpddr_cmds.c:		mutex_unlock(&chip->mutex);
+drivers/mtd/lpddr/lpddr_cmds.c:		chip->state = FL_LOCKING;
+drivers/mtd/lpddr/lpddr_cmds.c:		chip->state = FL_UNLOCKING;
+drivers/mtd/lpddr/lpddr_cmds.c:	mutex_unlock(&chip->mutex);
+drivers/mtd/nand/raw/atmel/nand-controller.c:	if (chip->options & NAND_BUSWIDTH_16)
+drivers/mtd/nand/raw/atmel/nand-controller.c:	nc = to_nand_controller(chip->controller);
+drivers/mtd/nand/raw/atmel/nand-controller.c:	if (chip->options & NAND_BUSWIDTH_16)
+drivers/mtd/nand/raw/atmel/nand-controller.c:	nc = to_nand_controller(chip->controller);
+drivers/mtd/nand/raw/atmel/nand-controller.c:	if (chip->options & NAND_BUSWIDTH_16)
+drivers/mtd/nand/raw/atmel/nand-controller.c:		chip->legacy.dev_ready = NULL;
+drivers/mtd/nand/raw/atmel/nand-controller.c:		chip->legacy.dev_ready = atmel_nand_dev_ready;
+drivers/mtd/nand/raw/atmel/nand-controller.c:	nc = to_hsmc_nand_controller(chip->controller);
+drivers/mtd/nand/raw/atmel/nand-controller.c:	nc = to_hsmc_nand_controller(chip->controller);
+drivers/mtd/nand/raw/atmel/nand-controller.c:		chip->legacy.dev_ready = atmel_hsmc_nand_dev_ready;
+drivers/mtd/nand/raw/atmel/nand-controller.c:	nc = to_hsmc_nand_controller(chip->controller);
+drivers/mtd/nand/raw/atmel/nand-controller.c:	nc = to_nand_controller(chip->controller);
+drivers/mtd/nand/raw/atmel/nand-controller.c:	nc = to_hsmc_nand_controller(chip->controller);
+drivers/mtd/nand/raw/atmel/nand-controller.c:		memcpy_toio(nc->sram.virt + mtd->writesize, chip->oob_poi,
+drivers/mtd/nand/raw/atmel/nand-controller.c:	nc = to_hsmc_nand_controller(chip->controller);
+drivers/mtd/nand/raw/atmel/nand-controller.c:		memcpy_fromio(chip->oob_poi, nc->sram.virt + mtd->writesize,
+drivers/mtd/nand/raw/atmel/nand-controller.c:	nc = to_hsmc_nand_controller(chip->controller);
+drivers/mtd/nand/raw/atmel/nand-controller.c:		if (chip->options & NAND_ROW_ADDR_3)
+drivers/mtd/nand/raw/atmel/nand-controller.c:	nc = to_nand_controller(chip->controller);
+drivers/mtd/nand/raw/atmel/nand-controller.c:	nc = to_nand_controller(chip->controller);
+drivers/mtd/nand/raw/atmel/nand-controller.c:	eccbuf = chip->oob_poi + oobregion.offset;
+drivers/mtd/nand/raw/atmel/nand-controller.c:	for (i = 0; i < chip->ecc.steps; i++) {
+drivers/mtd/nand/raw/atmel/nand-controller.c:		eccbuf += chip->ecc.bytes;
+drivers/mtd/nand/raw/atmel/nand-controller.c:	nc = to_nand_controller(chip->controller);
+drivers/mtd/nand/raw/atmel/nand-controller.c:	eccbuf = chip->oob_poi + oobregion.offset;
+drivers/mtd/nand/raw/atmel/nand-controller.c:	for (i = 0; i < chip->ecc.steps; i++) {
+drivers/mtd/nand/raw/atmel/nand-controller.c:							  chip->ecc.size,
+drivers/mtd/nand/raw/atmel/nand-controller.c:							  chip->ecc.bytes,
+drivers/mtd/nand/raw/atmel/nand-controller.c:							  chip->ecc.strength);
+drivers/mtd/nand/raw/atmel/nand-controller.c:		databuf += chip->ecc.size;
+drivers/mtd/nand/raw/atmel/nand-controller.c:		eccbuf += chip->ecc.bytes;
+drivers/mtd/nand/raw/atmel/nand-controller.c:	atmel_nand_write_buf(chip, chip->oob_poi, mtd->oobsize);
+drivers/mtd/nand/raw/atmel/nand-controller.c:	atmel_nand_read_buf(chip, chip->oob_poi, mtd->oobsize);
+drivers/mtd/nand/raw/atmel/nand-controller.c:	nc = to_hsmc_nand_controller(chip->controller);
+drivers/mtd/nand/raw/atmel/nand-controller.c:	atmel_nand_write_buf(chip, chip->oob_poi, mtd->oobsize);
+drivers/mtd/nand/raw/atmel/nand-controller.c:	status = chip->legacy.waitfunc(chip);
+drivers/mtd/nand/raw/atmel/nand-controller.c:	nc = to_hsmc_nand_controller(chip->controller);
+drivers/mtd/nand/raw/atmel/nand-controller.c:	nc = to_nand_controller(chip->controller);
+drivers/mtd/nand/raw/atmel/nand-controller.c:			chip->ecc.strength = val;
+drivers/mtd/nand/raw/atmel/nand-controller.c:			chip->ecc.size = val;
+drivers/mtd/nand/raw/atmel/nand-controller.c:	if (chip->ecc.options & NAND_ECC_MAXIMIZE)
+drivers/mtd/nand/raw/atmel/nand-controller.c:	else if (chip->ecc.strength)
+drivers/mtd/nand/raw/atmel/nand-controller.c:		req.ecc.strength = chip->ecc.strength;
+drivers/mtd/nand/raw/atmel/nand-controller.c:	else if (chip->base.eccreq.strength)
+drivers/mtd/nand/raw/atmel/nand-controller.c:		req.ecc.strength = chip->base.eccreq.strength;
+drivers/mtd/nand/raw/atmel/nand-controller.c:	if (chip->ecc.size)
+drivers/mtd/nand/raw/atmel/nand-controller.c:		req.ecc.sectorsize = chip->ecc.size;
+drivers/mtd/nand/raw/atmel/nand-controller.c:	else if (chip->base.eccreq.step_size)
+drivers/mtd/nand/raw/atmel/nand-controller.c:		req.ecc.sectorsize = chip->base.eccreq.step_size;
+drivers/mtd/nand/raw/atmel/nand-controller.c:	chip->ecc.algo = NAND_ECC_BCH;
+drivers/mtd/nand/raw/atmel/nand-controller.c:	chip->ecc.size = req.ecc.sectorsize;
+drivers/mtd/nand/raw/atmel/nand-controller.c:	chip->ecc.bytes = req.ecc.bytes / req.ecc.nsectors;
+drivers/mtd/nand/raw/atmel/nand-controller.c:	chip->ecc.strength = req.ecc.strength;
+drivers/mtd/nand/raw/atmel/nand-controller.c:	chip->options |= NAND_NO_SUBPAGE_WRITE;
+drivers/mtd/nand/raw/atmel/nand-controller.c:	nc = to_nand_controller(chip->controller);
+drivers/mtd/nand/raw/atmel/nand-controller.c:	switch (chip->ecc.mode) {
+drivers/mtd/nand/raw/atmel/nand-controller.c:		chip->ecc.read_page = atmel_nand_pmecc_read_page;
+drivers/mtd/nand/raw/atmel/nand-controller.c:		chip->ecc.write_page = atmel_nand_pmecc_write_page;
+drivers/mtd/nand/raw/atmel/nand-controller.c:		chip->ecc.read_page_raw = atmel_nand_pmecc_read_page_raw;
+drivers/mtd/nand/raw/atmel/nand-controller.c:		chip->ecc.write_page_raw = atmel_nand_pmecc_write_page_raw;
+drivers/mtd/nand/raw/atmel/nand-controller.c:			chip->ecc.mode);
+drivers/mtd/nand/raw/atmel/nand-controller.c:	if (chip->ecc.mode != NAND_ECC_HW)
+drivers/mtd/nand/raw/atmel/nand-controller.c:	chip->ecc.read_page = atmel_hsmc_nand_pmecc_read_page;
+drivers/mtd/nand/raw/atmel/nand-controller.c:	chip->ecc.write_page = atmel_hsmc_nand_pmecc_write_page;
+drivers/mtd/nand/raw/atmel/nand-controller.c:	chip->ecc.read_page_raw = atmel_hsmc_nand_pmecc_read_page_raw;
+drivers/mtd/nand/raw/atmel/nand-controller.c:	chip->ecc.write_page_raw = atmel_hsmc_nand_pmecc_write_page_raw;
+drivers/mtd/nand/raw/atmel/nand-controller.c:	chip->legacy.cmd_ctrl = atmel_nand_cmd_ctrl;
+drivers/mtd/nand/raw/atmel/nand-controller.c:	chip->legacy.read_byte = atmel_nand_read_byte;
+drivers/mtd/nand/raw/atmel/nand-controller.c:	chip->legacy.write_byte = atmel_nand_write_byte;
+drivers/mtd/nand/raw/atmel/nand-controller.c:	chip->legacy.read_buf = atmel_nand_read_buf;
+drivers/mtd/nand/raw/atmel/nand-controller.c:	chip->legacy.write_buf = atmel_nand_write_buf;
+drivers/mtd/nand/raw/atmel/nand-controller.c:	chip->legacy.select_chip = atmel_nand_select_chip;
+drivers/mtd/nand/raw/atmel/nand-controller.c:		chip->options |= NAND_KEEP_TIMINGS;
+drivers/mtd/nand/raw/atmel/nand-controller.c:	chip->legacy.chip_delay = 40;
+drivers/mtd/nand/raw/atmel/nand-controller.c:		chip->options |= NAND_USE_BOUNCE_BUFFER;
+drivers/mtd/nand/raw/atmel/nand-controller.c:		chip->ecc.mode = NAND_ECC_HW;
+drivers/mtd/nand/raw/atmel/nand-controller.c:	smc_nc = to_smc_nand_controller(chip->controller);
+drivers/mtd/nand/raw/atmel/nand-controller.c:	chip->legacy.cmd_ctrl = atmel_hsmc_nand_cmd_ctrl;
+drivers/mtd/nand/raw/atmel/nand-controller.c:	chip->legacy.select_chip = atmel_hsmc_nand_select_chip;
+drivers/mtd/nand/raw/atmel/nand-controller.c:	struct atmel_nand_controller *nc = to_nand_controller(chip->controller);
+drivers/mtd/nand/raw/bcm47xxnflash/ops_bcm4706.c:	BUG_ON(b47n->curr_page_addr & ~nand_chip->pagemask);
+drivers/mtd/nand/raw/bcm47xxnflash/ops_bcm4706.c:	/* Don't validate column using nand_chip->page_shift, it may be bigger
+drivers/mtd/nand/raw/bcm47xxnflash/ops_bcm4706.c:	BUG_ON(b47n->curr_page_addr & ~nand_chip->pagemask);
+drivers/mtd/nand/raw/bcm47xxnflash/ops_bcm4706.c:	/* Don't validate column using nand_chip->page_shift, it may be bigger
+drivers/mtd/nand/raw/bcm47xxnflash/ops_bcm4706.c:		nand_chip->legacy.cmd_ctrl(nand_chip, command, NAND_CTRL_CLE);
+drivers/mtd/nand/raw/bcm47xxnflash/ops_bcm4706.c:	nand_chip->legacy.select_chip = bcm47xxnflash_ops_bcm4706_select_chip;
+drivers/mtd/nand/raw/bcm47xxnflash/ops_bcm4706.c:	nand_chip->legacy.cmd_ctrl = bcm47xxnflash_ops_bcm4706_cmd_ctrl;
+drivers/mtd/nand/raw/bcm47xxnflash/ops_bcm4706.c:	nand_chip->legacy.dev_ready = bcm47xxnflash_ops_bcm4706_dev_ready;
+drivers/mtd/nand/raw/bcm47xxnflash/ops_bcm4706.c:	nand_chip->legacy.chip_delay = 50;
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	/* List of NAND hosts (one for each chip-select) */
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	const u8		*cs_offsets; /* within each chip-select */
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:/* Per chip-select offsets for v7.1 */
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:/* Per chip-select offsets for pre v7.1, except CS0 on <= v5.0 */
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:/* Per chip-select offset for <= v5.0 on CS0 only */
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	/* Per chip-select registers */
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	oobregion->offset = ((section + 1) * sas) - chip->ecc.bytes;
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	oobregion->length = chip->ecc.bytes;
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	if (sas <= chip->ecc.bytes)
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	oobregion->length = sas - chip->ecc.bytes;
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	if (section > 1 || sas - chip->ecc.bytes < 6 ||
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	    (section && sas - chip->ecc.bytes == 6))
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:		oobregion->length = sas - chip->ecc.bytes - 6;
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	u64 addr = (u64)page_addr << chip->page_shift;
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	void *oob = chip->oob_poi;
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	int page = addr >> chip->page_shift;
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	sas = mtd->oobsize / chip->ecc.steps;
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	ret = chip->ecc.read_page_raw(chip, buf, true, page);
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	for (i = 0; i < chip->ecc.steps; i++, oob += sas) {
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:		ecc_chunk = buf + chip->ecc.size * i;
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:						  chip->ecc.size,
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:						  chip->ecc.strength);
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	return brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:			NULL, (u8 *)chip->oob_poi);
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:		NULL, (u8 *)chip->oob_poi);
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	void *oob = oob_required ? chip->oob_poi : NULL;
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	void *oob = oob_required ? chip->oob_poi : NULL;
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:			      (u64)page << chip->page_shift, NULL,
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:			      chip->oob_poi);
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	ret = brcmnand_write(mtd, chip, (u64)page << chip->page_shift, NULL,
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:				 (u8 *)chip->oob_poi);
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	brcmnand_wr_corr_thresh(host, DIV_ROUND_UP(chip->ecc.strength * 3, 4));
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	cfg->device_width = (chip->options & NAND_BUSWIDTH_16) ? 16 : 8;
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	if (chip->ecc.mode != NAND_ECC_HW) {
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:			chip->ecc.mode);
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	if (chip->ecc.algo == NAND_ECC_UNKNOWN) {
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:		if (chip->ecc.strength == 1 && chip->ecc.size == 512)
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:			chip->ecc.algo = NAND_ECC_HAMMING;
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:			chip->ecc.algo = NAND_ECC_BCH;
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	if (chip->ecc.algo == NAND_ECC_HAMMING && (chip->ecc.strength != 1 ||
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:						   chip->ecc.size != 512)) {
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:			chip->ecc.strength, chip->ecc.size);
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	if (chip->ecc.mode != NAND_ECC_NONE &&
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	    (!chip->ecc.size || !chip->ecc.strength)) {
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:		if (chip->base.eccreq.step_size && chip->base.eccreq.strength) {
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:			chip->ecc.size = chip->base.eccreq.step_size;
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:			chip->ecc.strength = chip->base.eccreq.strength;
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:				chip->ecc.size, chip->ecc.strength);
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	switch (chip->ecc.size) {
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:		if (chip->ecc.algo == NAND_ECC_HAMMING)
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:			cfg->ecc_level = chip->ecc.strength;
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:		if (chip->ecc.strength & 0x1) {
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:		cfg->ecc_level = chip->ecc.strength >> 1;
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:			chip->ecc.size);
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	chip->options |= NAND_NO_SUBPAGE_WRITE;
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	chip->options |= NAND_USE_BOUNCE_BUFFER;
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	if (chip->bbt_options & NAND_BBT_USE_FLASH)
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:		chip->bbt_options |= NAND_BBT_NO_OOB;
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	chip->ecc.size = host->hwcfg.sector_size_1k ? 1024 : 512;
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:		dev_err(&pdev->dev, "can't get chip-select\n");
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	chip->legacy.cmd_ctrl = brcmnand_cmd_ctrl;
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	chip->legacy.cmdfunc = brcmnand_cmdfunc;
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	chip->legacy.waitfunc = brcmnand_waitfunc;
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	chip->legacy.read_byte = brcmnand_read_byte;
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	chip->legacy.read_buf = brcmnand_read_buf;
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	chip->legacy.write_buf = brcmnand_write_buf;
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	chip->ecc.mode = NAND_ECC_HW;
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	chip->ecc.read_page = brcmnand_read_page;
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	chip->ecc.write_page = brcmnand_write_page;
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	chip->ecc.read_page_raw = brcmnand_read_page_raw;
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	chip->ecc.write_page_raw = brcmnand_write_page_raw;
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	chip->ecc.write_oob_raw = brcmnand_write_oob_raw;
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	chip->ecc.read_oob_raw = brcmnand_read_oob_raw;
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	chip->ecc.read_oob = brcmnand_read_oob;
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	chip->ecc.write_oob = brcmnand_write_oob;
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	chip->controller = &ctrl->controller;
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:				continue; /* Try all chip-selects */
+drivers/mtd/nand/raw/brcmnand/brcmnand.c:	/* No chip-selects could initialize properly */
+drivers/mtd/nand/raw/cadence-nand-controller.c:	struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
+drivers/mtd/nand/raw/cadence-nand-controller.c:	u32 last_sec_size = cdns_chip->sector_size;
+drivers/mtd/nand/raw/cadence-nand-controller.c:		sec_cnt = cdns_chip->sector_count;
+drivers/mtd/nand/raw/cadence-nand-controller.c:		sec_size = cdns_chip->sector_size;
+drivers/mtd/nand/raw/cadence-nand-controller.c:		data_ctrl_size = cdns_chip->avail_oob_size;
+drivers/mtd/nand/raw/cadence-nand-controller.c:		sec_cnt = cdns_chip->sector_count;
+drivers/mtd/nand/raw/cadence-nand-controller.c:		last_sec_size = cdns_chip->sector_size
+drivers/mtd/nand/raw/cadence-nand-controller.c:			+ cdns_chip->avail_oob_size;
+drivers/mtd/nand/raw/cadence-nand-controller.c:		sec_size = cdns_chip->sector_size;
+drivers/mtd/nand/raw/cadence-nand-controller.c:		offset = mtd->writesize + cdns_chip->bbm_offs;
+drivers/mtd/nand/raw/cadence-nand-controller.c:	struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
+drivers/mtd/nand/raw/cadence-nand-controller.c:	cadence_nand_set_timings(cdns_ctrl, &cdns_chip->timings);
+drivers/mtd/nand/raw/cadence-nand-controller.c:				      cdns_chip->corr_str_idx);
+drivers/mtd/nand/raw/cadence-nand-controller.c:					 chip->ecc.strength);
+drivers/mtd/nand/raw/cadence-nand-controller.c:	struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
+drivers/mtd/nand/raw/cadence-nand-controller.c:	u8 thread_nr = cdns_chip->cs[chip->cur_cs];
+drivers/mtd/nand/raw/cadence-nand-controller.c:				       cdns_chip->cs[chip->cur_cs],
+drivers/mtd/nand/raw/cadence-nand-controller.c:	struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
+drivers/mtd/nand/raw/cadence-nand-controller.c:					    cdns_chip->cs[chip->cur_cs],
+drivers/mtd/nand/raw/cadence-nand-controller.c:	memcpy(buf + cdns_chip->bbm_offs, cdns_ctrl->buf, cdns_chip->bbm_len);
+drivers/mtd/nand/raw/cadence-nand-controller.c:	struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
+drivers/mtd/nand/raw/cadence-nand-controller.c:	cadence_nand_set_skip_bytes_conf(cdns_ctrl, cdns_chip->bbm_len,
+drivers/mtd/nand/raw/cadence-nand-controller.c:					 + cdns_chip->bbm_offs,
+drivers/mtd/nand/raw/cadence-nand-controller.c:		marker_val = *(u16 *)(chip->oob_poi
+drivers/mtd/nand/raw/cadence-nand-controller.c:				      + cdns_chip->bbm_offs);
+drivers/mtd/nand/raw/cadence-nand-controller.c:		       cdns_chip->avail_oob_size);
+drivers/mtd/nand/raw/cadence-nand-controller.c:			oob = chip->oob_poi;
+drivers/mtd/nand/raw/cadence-nand-controller.c:						    cdns_chip->cs[chip->cur_cs],
+drivers/mtd/nand/raw/cadence-nand-controller.c:						    cdns_chip->avail_oob_size,
+drivers/mtd/nand/raw/cadence-nand-controller.c:		memcpy(cdns_ctrl->buf + mtd->writesize, chip->oob_poi,
+drivers/mtd/nand/raw/cadence-nand-controller.c:		       cdns_chip->avail_oob_size);
+drivers/mtd/nand/raw/cadence-nand-controller.c:					  cdns_chip->cs[chip->cur_cs],
+drivers/mtd/nand/raw/cadence-nand-controller.c:					  + cdns_chip->avail_oob_size,
+drivers/mtd/nand/raw/cadence-nand-controller.c:	struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
+drivers/mtd/nand/raw/cadence-nand-controller.c:	struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
+drivers/mtd/nand/raw/cadence-nand-controller.c:	int ecc_steps = chip->ecc.steps;
+drivers/mtd/nand/raw/cadence-nand-controller.c:	int ecc_size = chip->ecc.size;
+drivers/mtd/nand/raw/cadence-nand-controller.c:	int ecc_bytes = chip->ecc.bytes;
+drivers/mtd/nand/raw/cadence-nand-controller.c:	int oob_skip = cdns_chip->bbm_len;
+drivers/mtd/nand/raw/cadence-nand-controller.c:		const u8 *oob = chip->oob_poi;
+drivers/mtd/nand/raw/cadence-nand-controller.c:		u32 oob_data_offset = (cdns_chip->sector_count - 1) *
+drivers/mtd/nand/raw/cadence-nand-controller.c:			(cdns_chip->sector_size + chip->ecc.bytes)
+drivers/mtd/nand/raw/cadence-nand-controller.c:			+ cdns_chip->sector_size + oob_skip;
+drivers/mtd/nand/raw/cadence-nand-controller.c:		       cdns_chip->avail_oob_size);
+drivers/mtd/nand/raw/cadence-nand-controller.c:		oob += cdns_chip->avail_oob_size;
+drivers/mtd/nand/raw/cadence-nand-controller.c:				pos += cdns_chip->avail_oob_size;
+drivers/mtd/nand/raw/cadence-nand-controller.c:					  cdns_chip->cs[chip->cur_cs],
+drivers/mtd/nand/raw/cadence-nand-controller.c:	struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
+drivers/mtd/nand/raw/cadence-nand-controller.c:	cadence_nand_set_skip_bytes_conf(cdns_ctrl, cdns_chip->bbm_len,
+drivers/mtd/nand/raw/cadence-nand-controller.c:					 + cdns_chip->bbm_offs, 1);
+drivers/mtd/nand/raw/cadence-nand-controller.c:			oob = chip->oob_poi;
+drivers/mtd/nand/raw/cadence-nand-controller.c:						    cdns_chip->cs[chip->cur_cs],
+drivers/mtd/nand/raw/cadence-nand-controller.c:						    cdns_chip->avail_oob_size,
+drivers/mtd/nand/raw/cadence-nand-controller.c:						    cdns_chip->cs[chip->cur_cs],
+drivers/mtd/nand/raw/cadence-nand-controller.c:						    + cdns_chip->avail_oob_size,
+drivers/mtd/nand/raw/cadence-nand-controller.c:			memcpy(chip->oob_poi,
+drivers/mtd/nand/raw/cadence-nand-controller.c:		if (cadence_nand_read_bbm(chip, page, chip->oob_poi))
+drivers/mtd/nand/raw/cadence-nand-controller.c:	struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
+drivers/mtd/nand/raw/cadence-nand-controller.c:	struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
+drivers/mtd/nand/raw/cadence-nand-controller.c:	int oob_skip = cdns_chip->bbm_len;
+drivers/mtd/nand/raw/cadence-nand-controller.c:	int ecc_steps = chip->ecc.steps;
+drivers/mtd/nand/raw/cadence-nand-controller.c:	int ecc_size = chip->ecc.size;
+drivers/mtd/nand/raw/cadence-nand-controller.c:	int ecc_bytes = chip->ecc.bytes;
+drivers/mtd/nand/raw/cadence-nand-controller.c:					    cdns_chip->cs[chip->cur_cs],
+drivers/mtd/nand/raw/cadence-nand-controller.c:		u8 *oob = chip->oob_poi;
+drivers/mtd/nand/raw/cadence-nand-controller.c:		u32 oob_data_offset = (cdns_chip->sector_count - 1) *
+drivers/mtd/nand/raw/cadence-nand-controller.c:			(cdns_chip->sector_size + chip->ecc.bytes)
+drivers/mtd/nand/raw/cadence-nand-controller.c:			+ cdns_chip->sector_size + oob_skip;
+drivers/mtd/nand/raw/cadence-nand-controller.c:		       cdns_chip->avail_oob_size);
+drivers/mtd/nand/raw/cadence-nand-controller.c:		oob += cdns_chip->avail_oob_size;
+drivers/mtd/nand/raw/cadence-nand-controller.c:				pos += cdns_chip->avail_oob_size;
+drivers/mtd/nand/raw/cadence-nand-controller.c:	struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
+drivers/mtd/nand/raw/cadence-nand-controller.c:	if (!(chip->options & NAND_BUSWIDTH_16))
+drivers/mtd/nand/raw/cadence-nand-controller.c:	struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
+drivers/mtd/nand/raw/cadence-nand-controller.c:					    cdns_chip->cs[chip->cur_cs],
+drivers/mtd/nand/raw/cadence-nand-controller.c:	struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
+drivers/mtd/nand/raw/cadence-nand-controller.c:					    cdns_chip->cs[chip->cur_cs],
+drivers/mtd/nand/raw/cadence-nand-controller.c:			.cs = chip->cur_cs,
+drivers/mtd/nand/raw/cadence-nand-controller.c:		ret = chip->controller->ops->exec_op(chip, &nand_op, false);
+drivers/mtd/nand/raw/cadence-nand-controller.c:	struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
+drivers/mtd/nand/raw/cadence-nand-controller.c:					    cdns_chip->cs[chip->cur_cs],
+drivers/mtd/nand/raw/cadence-nand-controller.c:	struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
+drivers/mtd/nand/raw/cadence-nand-controller.c:					     BIT(cdns_chip->cs[chip->cur_cs]),
+drivers/mtd/nand/raw/cadence-nand-controller.c:	oobregion->offset = cdns_chip->bbm_len;
+drivers/mtd/nand/raw/cadence-nand-controller.c:	oobregion->length = cdns_chip->avail_oob_size
+drivers/mtd/nand/raw/cadence-nand-controller.c:		- cdns_chip->bbm_len;
+drivers/mtd/nand/raw/cadence-nand-controller.c:	oobregion->offset = cdns_chip->avail_oob_size;
+drivers/mtd/nand/raw/cadence-nand-controller.c:	oobregion->length = chip->ecc.total;
+drivers/mtd/nand/raw/cadence-nand-controller.c:	struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
+drivers/mtd/nand/raw/cadence-nand-controller.c:	struct cadence_nand_timings *t = &cdns_chip->timings;
+drivers/mtd/nand/raw/cadence-nand-controller.c:	struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller);
+drivers/mtd/nand/raw/cadence-nand-controller.c:	u32 ecc_size = cdns_chip->sector_count * chip->ecc.bytes;
+drivers/mtd/nand/raw/cadence-nand-controller.c:	if (chip->options & NAND_BUSWIDTH_16) {
+drivers/mtd/nand/raw/cadence-nand-controller.c:	chip->bbt_options |= NAND_BBT_USE_FLASH;
+drivers/mtd/nand/raw/cadence-nand-controller.c:	chip->bbt_options |= NAND_BBT_NO_OOB;
+drivers/mtd/nand/raw/cadence-nand-controller.c:	chip->ecc.mode = NAND_ECC_HW;
+drivers/mtd/nand/raw/cadence-nand-controller.c:	chip->options |= NAND_NO_SUBPAGE_WRITE;
+drivers/mtd/nand/raw/cadence-nand-controller.c:	cdns_chip->bbm_offs = chip->badblockpos;
+drivers/mtd/nand/raw/cadence-nand-controller.c:	if (chip->options & NAND_BUSWIDTH_16) {
+drivers/mtd/nand/raw/cadence-nand-controller.c:		cdns_chip->bbm_offs &= ~0x01;
+drivers/mtd/nand/raw/cadence-nand-controller.c:		cdns_chip->bbm_len = 2;
+drivers/mtd/nand/raw/cadence-nand-controller.c:		cdns_chip->bbm_len = 1;
+drivers/mtd/nand/raw/cadence-nand-controller.c:				   mtd->oobsize - cdns_chip->bbm_len);
+drivers/mtd/nand/raw/cadence-nand-controller.c:		chip->ecc.size, chip->ecc.strength, chip->ecc.bytes);
+drivers/mtd/nand/raw/cadence-nand-controller.c:	cdns_chip->sector_size = chip->ecc.size;
+drivers/mtd/nand/raw/cadence-nand-controller.c:	cdns_chip->sector_count = mtd->writesize / cdns_chip->sector_size;
+drivers/mtd/nand/raw/cadence-nand-controller.c:	cdns_chip->avail_oob_size = mtd->oobsize - ecc_size;
+drivers/mtd/nand/raw/cadence-nand-controller.c:	if (cdns_chip->avail_oob_size > max_oob_data_size)
+drivers/mtd/nand/raw/cadence-nand-controller.c:		cdns_chip->avail_oob_size = max_oob_data_size;
+drivers/mtd/nand/raw/cadence-nand-controller.c:	if ((cdns_chip->avail_oob_size + cdns_chip->bbm_len + ecc_size)
+drivers/mtd/nand/raw/cadence-nand-controller.c:		cdns_chip->avail_oob_size -= 4;
+drivers/mtd/nand/raw/cadence-nand-controller.c:	ret = cadence_nand_get_ecc_strength_idx(cdns_ctrl, chip->ecc.strength);
+drivers/mtd/nand/raw/cadence-nand-controller.c:	cdns_chip->corr_str_idx = (u8)ret;
+drivers/mtd/nand/raw/cadence-nand-controller.c:				      cdns_chip->corr_str_idx);
+drivers/mtd/nand/raw/cadence-nand-controller.c:					 chip->ecc.strength);
+drivers/mtd/nand/raw/cadence-nand-controller.c:	chip->ecc.read_page = cadence_nand_read_page;
+drivers/mtd/nand/raw/cadence-nand-controller.c:	chip->ecc.read_page_raw = cadence_nand_read_page_raw;
+drivers/mtd/nand/raw/cadence-nand-controller.c:	chip->ecc.write_page = cadence_nand_write_page;
+drivers/mtd/nand/raw/cadence-nand-controller.c:	chip->ecc.write_page_raw = cadence_nand_write_page_raw;
+drivers/mtd/nand/raw/cadence-nand-controller.c:	chip->ecc.read_oob = cadence_nand_read_oob;
+drivers/mtd/nand/raw/cadence-nand-controller.c:	chip->ecc.write_oob = cadence_nand_write_oob;
+drivers/mtd/nand/raw/cadence-nand-controller.c:	chip->ecc.read_oob_raw = cadence_nand_read_oob_raw;
+drivers/mtd/nand/raw/cadence-nand-controller.c:	chip->ecc.write_oob_raw = cadence_nand_write_oob_raw;
+drivers/mtd/nand/raw/cadence-nand-controller.c:	cdns_chip->nsels = nsels;
+drivers/mtd/nand/raw/cadence-nand-controller.c:		cdns_chip->cs[i] = cs;
+drivers/mtd/nand/raw/cadence-nand-controller.c:	chip = &cdns_chip->chip;
+drivers/mtd/nand/raw/cadence-nand-controller.c:	chip->controller = &cdns_ctrl->controller;
+drivers/mtd/nand/raw/cadence-nand-controller.c:	chip->ecc.mode = NAND_ECC_HW;
+drivers/mtd/nand/raw/cadence-nand-controller.c:	ret = nand_scan(chip, cdns_chip->nsels);
+drivers/mtd/nand/raw/cadence-nand-controller.c:	list_add_tail(&cdns_chip->node, &cdns_ctrl->chips);
+drivers/mtd/nand/raw/cafe_nand.c:	return nand_prog_page_op(chip, page, mtd->writesize, chip->oob_poi,
+drivers/mtd/nand/raw/cafe_nand.c:	return nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
+drivers/mtd/nand/raw/cafe_nand.c: * @oob_required:	caller expects OOB data read to chip->oob_poi
+drivers/mtd/nand/raw/cafe_nand.c:	chip->legacy.read_buf(chip, chip->oob_poi, mtd->oobsize);
+drivers/mtd/nand/raw/cafe_nand.c:		u8 *oob = chip->oob_poi;
+drivers/mtd/nand/raw/cafe_nand.c:	oobregion->length = chip->ecc.total;
+drivers/mtd/nand/raw/cafe_nand.c:	oobregion->offset = chip->ecc.total;
+drivers/mtd/nand/raw/cafe_nand.c:	oobregion->length = mtd->oobsize - chip->ecc.total;
+drivers/mtd/nand/raw/cafe_nand.c:	chip->legacy.write_buf(chip, chip->oob_poi, mtd->oobsize);
+drivers/mtd/nand/raw/davinci_nand.c:			if ((diff >> (12 + 3)) < chip->ecc.size) {
+drivers/mtd/nand/raw/davinci_nand.c:		ioread32_rep(chip->legacy.IO_ADDR_R, buf, len >> 2);
+drivers/mtd/nand/raw/davinci_nand.c:		ioread16_rep(chip->legacy.IO_ADDR_R, buf, len >> 1);
+drivers/mtd/nand/raw/davinci_nand.c:		ioread8_rep(chip->legacy.IO_ADDR_R, buf, len);
+drivers/mtd/nand/raw/davinci_nand.c:		iowrite32_rep(chip->legacy.IO_ADDR_R, buf, len >> 2);
+drivers/mtd/nand/raw/davinci_nand.c:		iowrite16_rep(chip->legacy.IO_ADDR_R, buf, len >> 1);
+drivers/mtd/nand/raw/davinci_nand.c:		iowrite8_rep(chip->legacy.IO_ADDR_R, buf, len);
+drivers/mtd/nand/raw/denali.c:	return container_of(chip->controller, struct denali_controller,
+drivers/mtd/nand/raw/denali.c:	iowrite32(1 << (chip->phys_erase_shift - chip->page_shift),
+drivers/mtd/nand/raw/denali.c:	iowrite32(chip->options & NAND_BUSWIDTH_16 ? 1 : 0,
+drivers/mtd/nand/raw/denali.c:	iowrite32(chip->options & NAND_ROW_ADDR_3 ?
+drivers/mtd/nand/raw/denali.c:		  FIELD_PREP(ECC_CORRECTION__VALUE, chip->ecc.strength),
+drivers/mtd/nand/raw/denali.c:	iowrite32(chip->ecc.size, denali->reg + CFG_DATA_BLOCK_SIZE);
+drivers/mtd/nand/raw/denali.c:	iowrite32(chip->ecc.size, denali->reg + CFG_LAST_DATA_BLOCK_SIZE);
+drivers/mtd/nand/raw/denali.c:	iowrite32(chip->ecc.steps, denali->reg + CFG_NUM_DATA_BLOCKS);
+drivers/mtd/nand/raw/denali.c:	if (chip->options & NAND_KEEP_TIMINGS)
+drivers/mtd/nand/raw/denali.c:	struct nand_ecc_ctrl *ecc = &chip->ecc;
+drivers/mtd/nand/raw/denali.c:	struct nand_ecc_ctrl *ecc = &chip->ecc;
+drivers/mtd/nand/raw/denali.c:	return denali_read_raw(chip, buf, oob_required ? chip->oob_poi : NULL,
+drivers/mtd/nand/raw/denali.c:	return denali_write_raw(chip, buf, oob_required ? chip->oob_poi : NULL,
+drivers/mtd/nand/raw/denali.c:	return denali_read_raw(chip, NULL, chip->oob_poi, page);
+drivers/mtd/nand/raw/denali.c:	return denali_write_raw(chip, NULL, chip->oob_poi, page);
+drivers/mtd/nand/raw/denali.c:	struct nand_ecc_ctrl *ecc = &chip->ecc;
+drivers/mtd/nand/raw/denali.c:	u8 *ecc_code = chip->oob_poi + denali->oob_skip_bytes;
+drivers/mtd/nand/raw/denali.c:		*uncor_ecc_flags = GENMASK(chip->ecc.steps - 1, 0);
+drivers/mtd/nand/raw/denali.c:	unsigned int ecc_size = chip->ecc.size;
+drivers/mtd/nand/raw/denali.c:	denali_select_target(chip, chip->cur_cs);
+drivers/mtd/nand/raw/denali.c:	oobregion->length = chip->ecc.total;
+drivers/mtd/nand/raw/denali.c:	oobregion->offset = chip->ecc.total + denali->oob_skip_bytes;
+drivers/mtd/nand/raw/denali.c:	memorg = nanddev_get_memorg(&chip->base);
+drivers/mtd/nand/raw/denali.c:	chip->page_shift += 1;
+drivers/mtd/nand/raw/denali.c:	chip->phys_erase_shift += 1;
+drivers/mtd/nand/raw/denali.c:	chip->bbt_erase_shift += 1;
+drivers/mtd/nand/raw/denali.c:	chip->chip_shift += 1;
+drivers/mtd/nand/raw/denali.c:	chip->pagemask <<= 1;
+drivers/mtd/nand/raw/denali.c:	chip->ecc.size <<= 1;
+drivers/mtd/nand/raw/denali.c:	chip->ecc.bytes <<= 1;
+drivers/mtd/nand/raw/denali.c:	chip->ecc.strength <<= 1;
+drivers/mtd/nand/raw/denali.c:		chip->ecc.size, chip->ecc.strength, chip->ecc.bytes);
+drivers/mtd/nand/raw/denali.c:			       chip->options & NAND_BUSWIDTH_16);
+drivers/mtd/nand/raw/denali.c:				chip->options & NAND_BUSWIDTH_16);
+drivers/mtd/nand/raw/denali.c:	struct nand_chip *chip = &dchip->chip;
+drivers/mtd/nand/raw/denali.c:	chip->controller = &denali->controller;
+drivers/mtd/nand/raw/denali.c:	for (i = 0; i < dchip->nsels; i++) {
+drivers/mtd/nand/raw/denali.c:		unsigned int bank = dchip->sels[i].bank;
+drivers/mtd/nand/raw/denali.c:			if (bank == dchip->sels[j].bank) {
+drivers/mtd/nand/raw/denali.c:		chip->options |= NAND_USE_BOUNCE_BUFFER;
+drivers/mtd/nand/raw/denali.c:		chip->buf_align = 16;
+drivers/mtd/nand/raw/denali.c:		chip->options |= NAND_KEEP_TIMINGS;
+drivers/mtd/nand/raw/denali.c:	chip->bbt_options |= NAND_BBT_USE_FLASH;
+drivers/mtd/nand/raw/denali.c:	chip->bbt_options |= NAND_BBT_NO_OOB;
+drivers/mtd/nand/raw/denali.c:	chip->options |= NAND_NO_SUBPAGE_WRITE;
+drivers/mtd/nand/raw/denali.c:	chip->ecc.mode = NAND_ECC_HW_SYNDROME;
+drivers/mtd/nand/raw/denali.c:	chip->ecc.read_page = denali_read_page;
+drivers/mtd/nand/raw/denali.c:	chip->ecc.write_page = denali_write_page;
+drivers/mtd/nand/raw/denali.c:	chip->ecc.read_page_raw = denali_read_page_raw;
+drivers/mtd/nand/raw/denali.c:	chip->ecc.write_page_raw = denali_write_page_raw;
+drivers/mtd/nand/raw/denali.c:	chip->ecc.read_oob = denali_read_oob;
+drivers/mtd/nand/raw/denali.c:	chip->ecc.write_oob = denali_write_oob;
+drivers/mtd/nand/raw/denali.c:	ret = nand_scan(chip, dchip->nsels);
+drivers/mtd/nand/raw/denali.c:	list_add_tail(&dchip->node, &denali->chips);
+drivers/mtd/nand/raw/denali.c:		nand_release(&dchip->chip);
+drivers/mtd/nand/raw/denali_dt.c:	dchip->nsels = nsels;
+drivers/mtd/nand/raw/denali_dt.c:		dchip->sels[i].bank = bank;
+drivers/mtd/nand/raw/denali_dt.c:		nand_set_flash_node(&dchip->chip, chip_np);
+drivers/mtd/nand/raw/denali_pci.c:	dchip->chip.ecc.options |= NAND_ECC_MAXIMIZE;
+drivers/mtd/nand/raw/denali_pci.c:	dchip->nsels = nsels;
+drivers/mtd/nand/raw/denali_pci.c:		dchip->sels[i].bank = i;
+drivers/mtd/nand/raw/fsl_elbc_nand.c:	if (section >= chip->ecc.steps)
+drivers/mtd/nand/raw/fsl_elbc_nand.c:	oobregion->length = chip->ecc.bytes;
+drivers/mtd/nand/raw/fsl_elbc_nand.c:	if (section > chip->ecc.steps)
+drivers/mtd/nand/raw/fsl_elbc_nand.c:		if (section < chip->ecc.steps)
+drivers/mtd/nand/raw/fsl_elbc_nand.c:	         chip->phys_erase_shift, chip->page_shift);
+drivers/mtd/nand/raw/fsl_elbc_nand.c:	if (chip->ecc.mode != NAND_ECC_HW)
+drivers/mtd/nand/raw/fsl_elbc_nand.c:		fsl_elbc_read_buf(chip, chip->oob_poi, mtd->oobsize);
+drivers/mtd/nand/raw/fsl_elbc_nand.c:	fsl_elbc_write_buf(chip, chip->oob_poi, mtd->oobsize);
+drivers/mtd/nand/raw/fsl_elbc_nand.c:	fsl_elbc_write_buf(chip, chip->oob_poi, mtd->oobsize);
+drivers/mtd/nand/raw/fsl_elbc_nand.c:	chip->legacy.read_byte = fsl_elbc_read_byte;
+drivers/mtd/nand/raw/fsl_elbc_nand.c:	chip->legacy.write_buf = fsl_elbc_write_buf;
+drivers/mtd/nand/raw/fsl_elbc_nand.c:	chip->legacy.read_buf = fsl_elbc_read_buf;
+drivers/mtd/nand/raw/fsl_elbc_nand.c:	chip->legacy.select_chip = fsl_elbc_select_chip;
+drivers/mtd/nand/raw/fsl_elbc_nand.c:	chip->legacy.cmdfunc = fsl_elbc_cmdfunc;
+drivers/mtd/nand/raw/fsl_elbc_nand.c:	chip->legacy.waitfunc = fsl_elbc_wait;
+drivers/mtd/nand/raw/fsl_elbc_nand.c:	chip->legacy.set_features = nand_get_set_features_notsupp;
+drivers/mtd/nand/raw/fsl_elbc_nand.c:	chip->legacy.get_features = nand_get_set_features_notsupp;
+drivers/mtd/nand/raw/fsl_elbc_nand.c:	chip->bbt_td = &bbt_main_descr;
+drivers/mtd/nand/raw/fsl_elbc_nand.c:	chip->bbt_md = &bbt_mirror_descr;
+drivers/mtd/nand/raw/fsl_elbc_nand.c:	chip->bbt_options = NAND_BBT_USE_FLASH;
+drivers/mtd/nand/raw/fsl_elbc_nand.c:	chip->controller = &elbc_fcm_ctrl->controller;
+drivers/mtd/nand/raw/fsl_elbc_nand.c:	switch (chip->ecc.mode) {
+drivers/mtd/nand/raw/fsl_elbc_nand.c:			chip->ecc.read_page = fsl_elbc_read_page;
+drivers/mtd/nand/raw/fsl_elbc_nand.c:			chip->ecc.write_page = fsl_elbc_write_page;
+drivers/mtd/nand/raw/fsl_elbc_nand.c:			chip->ecc.write_subpage = fsl_elbc_write_subpage;
+drivers/mtd/nand/raw/fsl_elbc_nand.c:			chip->ecc.mode = NAND_ECC_HW;
+drivers/mtd/nand/raw/fsl_elbc_nand.c:			chip->ecc.size = 512;
+drivers/mtd/nand/raw/fsl_elbc_nand.c:			chip->ecc.bytes = 3;
+drivers/mtd/nand/raw/fsl_elbc_nand.c:			chip->ecc.strength = 1;
+drivers/mtd/nand/raw/fsl_elbc_nand.c:			chip->ecc.mode = NAND_ECC_SOFT;
+drivers/mtd/nand/raw/fsl_elbc_nand.c:			chip->ecc.algo = NAND_ECC_HAMMING;
+drivers/mtd/nand/raw/fsl_elbc_nand.c:	if (chip->pagemask & 0xffff0000)
+drivers/mtd/nand/raw/fsl_elbc_nand.c:	if (chip->pagemask & 0xff000000)
+drivers/mtd/nand/raw/fsl_elbc_nand.c:	        nanddev_ntargets(&chip->base));
+drivers/mtd/nand/raw/fsl_elbc_nand.c:	        nanddev_target_size(&chip->base));
+drivers/mtd/nand/raw/fsl_elbc_nand.c:	        chip->pagemask);
+drivers/mtd/nand/raw/fsl_elbc_nand.c:	        chip->legacy.chip_delay);
+drivers/mtd/nand/raw/fsl_elbc_nand.c:	        chip->badblockpos);
+drivers/mtd/nand/raw/fsl_elbc_nand.c:	        chip->chip_shift);
+drivers/mtd/nand/raw/fsl_elbc_nand.c:	        chip->page_shift);
+drivers/mtd/nand/raw/fsl_elbc_nand.c:	        chip->phys_erase_shift);
+drivers/mtd/nand/raw/fsl_elbc_nand.c:	        chip->ecc.mode);
+drivers/mtd/nand/raw/fsl_elbc_nand.c:	        chip->ecc.steps);
+drivers/mtd/nand/raw/fsl_elbc_nand.c:	        chip->ecc.bytes);
+drivers/mtd/nand/raw/fsl_elbc_nand.c:	        chip->ecc.total);
+drivers/mtd/nand/raw/fsl_ifc_nand.c:	oobregion->length = chip->ecc.total;
+drivers/mtd/nand/raw/fsl_ifc_nand.c:	    !(chip->options & NAND_BUSWIDTH_16)) {
+drivers/mtd/nand/raw/fsl_ifc_nand.c:		oobregion->offset = chip->ecc.total + 8;
+drivers/mtd/nand/raw/fsl_ifc_nand.c:		int sector_start = bufnum * chip->ecc.steps;
+drivers/mtd/nand/raw/fsl_ifc_nand.c:		int sector_end = sector_start + chip->ecc.steps - 1;
+drivers/mtd/nand/raw/fsl_ifc_nand.c:		if (chip->ecc.mode == NAND_ECC_HW)
+drivers/mtd/nand/raw/fsl_ifc_nand.c:		if (chip->options & NAND_BUSWIDTH_16)
+drivers/mtd/nand/raw/fsl_ifc_nand.c:	u8 *ecc = chip->oob_poi;
+drivers/mtd/nand/raw/fsl_ifc_nand.c:	const int ecc_size = chip->ecc.bytes;
+drivers/mtd/nand/raw/fsl_ifc_nand.c:	const int pkt_size = chip->ecc.size;
+drivers/mtd/nand/raw/fsl_ifc_nand.c:	for (i = 0; i < chip->ecc.steps; ++i) {
+drivers/mtd/nand/raw/fsl_ifc_nand.c:						  chip->ecc.strength);
+drivers/mtd/nand/raw/fsl_ifc_nand.c:		fsl_ifc_read_buf(chip, chip->oob_poi, mtd->oobsize);
+drivers/mtd/nand/raw/fsl_ifc_nand.c:			fsl_ifc_read_buf(chip, chip->oob_poi, mtd->oobsize);
+drivers/mtd/nand/raw/fsl_ifc_nand.c:	fsl_ifc_write_buf(chip, chip->oob_poi, mtd->oobsize);
+drivers/mtd/nand/raw/fsl_ifc_nand.c:		nanddev_ntargets(&chip->base));
+drivers/mtd/nand/raw/fsl_ifc_nand.c:	        nanddev_target_size(&chip->base));
+drivers/mtd/nand/raw/fsl_ifc_nand.c:							chip->pagemask);
+drivers/mtd/nand/raw/fsl_ifc_nand.c:		chip->legacy.chip_delay);
+drivers/mtd/nand/raw/fsl_ifc_nand.c:							chip->badblockpos);
+drivers/mtd/nand/raw/fsl_ifc_nand.c:							chip->chip_shift);
+drivers/mtd/nand/raw/fsl_ifc_nand.c:							chip->page_shift);
+drivers/mtd/nand/raw/fsl_ifc_nand.c:							chip->phys_erase_shift);
+drivers/mtd/nand/raw/fsl_ifc_nand.c:							chip->ecc.mode);
+drivers/mtd/nand/raw/fsl_ifc_nand.c:							chip->ecc.steps);
+drivers/mtd/nand/raw/fsl_ifc_nand.c:							chip->ecc.bytes);
+drivers/mtd/nand/raw/fsl_ifc_nand.c:							chip->ecc.total);
+drivers/mtd/nand/raw/fsl_ifc_nand.c:		chip->legacy.read_byte = fsl_ifc_read_byte16;
+drivers/mtd/nand/raw/fsl_ifc_nand.c:		chip->legacy.read_byte = fsl_ifc_read_byte;
+drivers/mtd/nand/raw/fsl_ifc_nand.c:	chip->legacy.write_buf = fsl_ifc_write_buf;
+drivers/mtd/nand/raw/fsl_ifc_nand.c:	chip->legacy.read_buf = fsl_ifc_read_buf;
+drivers/mtd/nand/raw/fsl_ifc_nand.c:	chip->legacy.select_chip = fsl_ifc_select_chip;
+drivers/mtd/nand/raw/fsl_ifc_nand.c:	chip->legacy.cmdfunc = fsl_ifc_cmdfunc;
+drivers/mtd/nand/raw/fsl_ifc_nand.c:	chip->legacy.waitfunc = fsl_ifc_wait;
+drivers/mtd/nand/raw/fsl_ifc_nand.c:	chip->legacy.set_features = nand_get_set_features_notsupp;
+drivers/mtd/nand/raw/fsl_ifc_nand.c:	chip->legacy.get_features = nand_get_set_features_notsupp;
+drivers/mtd/nand/raw/fsl_ifc_nand.c:	chip->bbt_td = &bbt_main_descr;
+drivers/mtd/nand/raw/fsl_ifc_nand.c:	chip->bbt_md = &bbt_mirror_descr;
+drivers/mtd/nand/raw/fsl_ifc_nand.c:	chip->bbt_options = NAND_BBT_USE_FLASH;
+drivers/mtd/nand/raw/fsl_ifc_nand.c:	chip->options = NAND_NO_SUBPAGE_WRITE;
+drivers/mtd/nand/raw/fsl_ifc_nand.c:		chip->legacy.read_byte = fsl_ifc_read_byte16;
+drivers/mtd/nand/raw/fsl_ifc_nand.c:		chip->options |= NAND_BUSWIDTH_16;
+drivers/mtd/nand/raw/fsl_ifc_nand.c:		chip->legacy.read_byte = fsl_ifc_read_byte;
+drivers/mtd/nand/raw/fsl_ifc_nand.c:	chip->controller = &ifc_nand_ctrl->controller;
+drivers/mtd/nand/raw/fsl_ifc_nand.c:	chip->ecc.read_page = fsl_ifc_read_page;
+drivers/mtd/nand/raw/fsl_ifc_nand.c:	chip->ecc.write_page = fsl_ifc_write_page;
+drivers/mtd/nand/raw/fsl_ifc_nand.c:		if (!(chip->options & NAND_BUSWIDTH_16)) {
+drivers/mtd/nand/raw/fsl_ifc_nand.c:		chip->ecc.mode = NAND_ECC_HW;
+drivers/mtd/nand/raw/fsl_ifc_nand.c:		chip->ecc.size = 512;
+drivers/mtd/nand/raw/fsl_ifc_nand.c:			chip->ecc.bytes = 8;
+drivers/mtd/nand/raw/fsl_ifc_nand.c:			chip->ecc.strength = 4;
+drivers/mtd/nand/raw/fsl_ifc_nand.c:			chip->ecc.bytes = 16;
+drivers/mtd/nand/raw/fsl_ifc_nand.c:			chip->ecc.strength = 8;
+drivers/mtd/nand/raw/fsl_ifc_nand.c:		chip->ecc.mode = NAND_ECC_SOFT;
+drivers/mtd/nand/raw/fsl_ifc_nand.c:		chip->ecc.algo = NAND_ECC_HAMMING;
+drivers/mtd/nand/raw/fsl_upm.c:	fsl_upm_run_pattern(&fun->upm, chip->legacy.IO_ADDR_R, mar);
+drivers/mtd/nand/raw/fsl_upm.c:		chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
+drivers/mtd/nand/raw/fsl_upm.c:		chip->legacy.IO_ADDR_R = fun->io_base + fun->mchip_offsets[mchip_nr];
+drivers/mtd/nand/raw/fsl_upm.c:		chip->legacy.IO_ADDR_W = chip->legacy.IO_ADDR_R;
+drivers/mtd/nand/raw/fsl_upm.c:	prop = of_get_property(ofdev->dev.of_node, "chip-delay", NULL);
+drivers/mtd/nand/raw/fsmc_nand.c:	if (section >= chip->ecc.steps)
+drivers/mtd/nand/raw/fsmc_nand.c:	if (section >= chip->ecc.steps)
+drivers/mtd/nand/raw/fsmc_nand.c:	if (section < chip->ecc.steps - 1)
+drivers/mtd/nand/raw/fsmc_nand.c:	if (section >= chip->ecc.steps)
+drivers/mtd/nand/raw/fsmc_nand.c:	oobregion->length = chip->ecc.bytes;
+drivers/mtd/nand/raw/fsmc_nand.c:	if (section >= chip->ecc.steps)
+drivers/mtd/nand/raw/fsmc_nand.c:	if (section < chip->ecc.steps - 1)
+drivers/mtd/nand/raw/fsmc_nand.c: * @oob_required:	caller expects OOB data read to chip->oob_poi
+drivers/mtd/nand/raw/fsmc_nand.c:	int i, j, s, stat, eccsize = chip->ecc.size;
+drivers/mtd/nand/raw/fsmc_nand.c:	int eccbytes = chip->ecc.bytes;
+drivers/mtd/nand/raw/fsmc_nand.c:	int eccsteps = chip->ecc.steps;
+drivers/mtd/nand/raw/fsmc_nand.c:	u8 *ecc_calc = chip->ecc.calc_buf;
+drivers/mtd/nand/raw/fsmc_nand.c:	u8 *ecc_code = chip->ecc.code_buf;
+drivers/mtd/nand/raw/fsmc_nand.c:		chip->ecc.hwctl(chip, NAND_ECC_READ);
+drivers/mtd/nand/raw/fsmc_nand.c:			if (chip->options & NAND_BUSWIDTH_16)
+drivers/mtd/nand/raw/fsmc_nand.c:		memcpy(&ecc_code[i], oob, chip->ecc.bytes);
+drivers/mtd/nand/raw/fsmc_nand.c:		chip->ecc.calculate(chip, p, &ecc_calc[i]);
+drivers/mtd/nand/raw/fsmc_nand.c:		stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]);
+drivers/mtd/nand/raw/fsmc_nand.c:		int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8);
+drivers/mtd/nand/raw/fsmc_nand.c:		int bits_data = count_written_bits(dat, chip->ecc.size, 8);
+drivers/mtd/nand/raw/fsmc_nand.c:				memset(dat, 0xff, chip->ecc.size);
+drivers/mtd/nand/raw/fsmc_nand.c:		if (err_idx[i] < chip->ecc.size * 8) {
+drivers/mtd/nand/raw/gpio.c:	if (!of_property_read_u32(dev->of_node, "chip-delay", &val))
+drivers/mtd/nand/raw/gpio.c:	chip->legacy.IO_ADDR_R = devm_ioremap_resource(dev, res);
+drivers/mtd/nand/raw/gpio.c:	if (IS_ERR(chip->legacy.IO_ADDR_R))
+drivers/mtd/nand/raw/gpio.c:		return PTR_ERR(chip->legacy.IO_ADDR_R);
+drivers/mtd/nand/raw/gpio.c:		chip->legacy.dev_ready = gpio_nand_devready;
+drivers/mtd/nand/raw/gpio.c:	chip->legacy.IO_ADDR_W	= chip->legacy.IO_ADDR_R;
+drivers/mtd/nand/raw/gpio.c:	chip->ecc.mode		= NAND_ECC_SOFT;
+drivers/mtd/nand/raw/gpio.c:	chip->ecc.algo		= NAND_ECC_HAMMING;
+drivers/mtd/nand/raw/gpio.c:	chip->options		= gpiomtd->plat.options;
+drivers/mtd/nand/raw/gpio.c:	chip->legacy.chip_delay	= gpiomtd->plat.chip_delay;
+drivers/mtd/nand/raw/gpio.c:	chip->legacy.cmd_ctrl	= gpio_nand_cmd_ctrl;
+drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c:			chip->base.eccreq.strength,
+drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c:			chip->base.eccreq.step_size);
+drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c:	if (chip->ecc.strength > 0 && chip->ecc.size > 0)
+drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c:		return set_geometry_by_ecc_info(this, chip->ecc.strength,
+drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c:						chip->ecc.size);
+drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c:		if (!(chip->base.eccreq.strength > 0 &&
+drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c:		      chip->base.eccreq.step_size > 0))
+drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c:						chip->base.eccreq.strength,
+drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c:						chip->base.eccreq.step_size);
+drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c:		memset(chip->oob_poi, ~0, mtd->oobsize);
+drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c:		chip->oob_poi[0] = ((uint8_t *)this->auxiliary_virt)[0];
+drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c:	int size = chip->ecc.size; /* ECC chunk size */
+drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c:	memcpy(this->auxiliary_virt, chip->oob_poi, nfc_geo->auxiliary_size);
+drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c:	memset(chip->oob_poi, ~0, mtd->oobsize);
+drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c:	ret = nand_read_page_op(chip, page, mtd->writesize, chip->oob_poi,
+drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c:		ret = nand_read_page_op(chip, page, 0, chip->oob_poi, 1);
+drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c:				 chip->oob_poi + of.offset, of.length);
+drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c:	uint8_t *oob = chip->oob_poi;
+drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c:	uint8_t *oob = chip->oob_poi;
+drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c:	chipnr = (int)(ofs >> chip->chip_shift);
+drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c:	page = (int)(ofs >> chip->page_shift);
+drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c:		status = chip->ecc.write_page_raw(chip, buffer, 0, page);
+drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c:	block_count = nanddev_eraseblocks_per_target(&chip->base);
+drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c:		chipnr = block >> (chip->chip_shift - chip->phys_erase_shift);
+drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c:		page = block << (chip->phys_erase_shift - chip->page_shift);
+drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c:		byte = block <<  chip->phys_erase_shift;
+drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c:			ret = chip->legacy.block_markbad(chip, byte);
+drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c:	struct nand_ecc_ctrl *ecc = &chip->ecc;
+drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c:		chip->options |= NAND_SUBPAGE_READ;
+drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c:	if (chip->bbt_options & NAND_BBT_USE_FLASH) {
+drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c:		chip->bbt_options |= NAND_BBT_NO_OOB;
+drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c:	chip->options |= NAND_SKIP_BBTSCAN;
+drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c:	chip->legacy.block_markbad = gpmi_block_markbad;
+drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c:	chip->badblock_pattern	= &gpmi_bbt_descr;
+drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c:	chip->options		|= NAND_NO_SUBPAGE_WRITE;
+drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c:	chip->controller = &this->base;
+drivers/mtd/nand/raw/hisi504_nand.c:	if (chip->ecc.mode == NAND_ECC_NONE) {
+drivers/mtd/nand/raw/hisi504_nand.c:		if (chip->options & NAND_BUSWIDTH_16 &&
+drivers/mtd/nand/raw/hisi504_nand.c:		if (chip->options & NAND_ROW_ADDR_3) {
+drivers/mtd/nand/raw/hisi504_nand.c:		if (chip->ecc.mode == NAND_ECC_HW)
+drivers/mtd/nand/raw/hisi504_nand.c:	chip->legacy.read_buf(chip, chip->oob_poi, mtd->oobsize);
+drivers/mtd/nand/raw/hisi504_nand.c:		switch (chip->ecc.strength) {
+drivers/mtd/nand/raw/hisi504_nand.c:	nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
+drivers/mtd/nand/raw/hisi504_nand.c:		chip->legacy.write_buf(chip, chip->oob_poi, mtd->oobsize);
+drivers/mtd/nand/raw/hisi504_nand.c:		| ((chip->options & NAND_BUSWIDTH_16) ?
+drivers/mtd/nand/raw/hisi504_nand.c:	size = chip->ecc.size;
+drivers/mtd/nand/raw/hisi504_nand.c:	strength = chip->ecc.strength;
+drivers/mtd/nand/raw/hisi504_nand.c:	chip->ecc.size = size;
+drivers/mtd/nand/raw/hisi504_nand.c:	chip->ecc.strength = strength;
+drivers/mtd/nand/raw/hisi504_nand.c:	chip->ecc.read_page = hisi_nand_read_page_hwecc;
+drivers/mtd/nand/raw/hisi504_nand.c:	chip->ecc.read_oob = hisi_nand_read_oob;
+drivers/mtd/nand/raw/hisi504_nand.c:	chip->ecc.write_page = hisi_nand_write_page_hwecc;
+drivers/mtd/nand/raw/hisi504_nand.c:	switch (chip->ecc.strength) {
+drivers/mtd/nand/raw/hisi504_nand.c:		dev_err(dev, "not support strength: %d\n", chip->ecc.strength);
+drivers/mtd/nand/raw/hisi504_nand.c:	if (chip->ecc.mode == NAND_ECC_HW)
+drivers/mtd/nand/raw/hisi504_nand.c:	chip->legacy.cmdfunc	= hisi_nfc_cmdfunc;
+drivers/mtd/nand/raw/hisi504_nand.c:	chip->legacy.select_chip	= hisi_nfc_select_chip;
+drivers/mtd/nand/raw/hisi504_nand.c:	chip->legacy.read_byte	= hisi_nfc_read_byte;
+drivers/mtd/nand/raw/hisi504_nand.c:	chip->legacy.write_buf	= hisi_nfc_write_buf;
+drivers/mtd/nand/raw/hisi504_nand.c:	chip->legacy.read_buf	= hisi_nfc_read_buf;
+drivers/mtd/nand/raw/hisi504_nand.c:	chip->legacy.chip_delay	= HINFC504_CHIP_DELAY;
+drivers/mtd/nand/raw/hisi504_nand.c:	chip->legacy.set_features	= nand_get_set_features_notsupp;
+drivers/mtd/nand/raw/hisi504_nand.c:	chip->legacy.get_features	= nand_get_set_features_notsupp;
+drivers/mtd/nand/raw/hisi504_nand.c:	chip->legacy.dummy_controller.ops = &hisi_nfc_controller_ops;
+drivers/mtd/nand/raw/hisi504_nand.c:	for (cs = 0; cs < nanddev_ntargets(&chip->base); cs++)
+drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c:	struct nand_ecc_ctrl *ecc = &chip->ecc;
+drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c:	struct nand_ecc_ctrl *ecc = &chip->ecc;
+drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c:	struct nand_ecc_ctrl *ecc = &chip->ecc;
+drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c:	struct nand_ecc_ctrl *ecc = &chip->ecc;
+drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c:	struct ingenic_nfc *nfc = to_ingenic_nfc(chip->controller);
+drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c:	if (chip->ecc.strength == 4) {
+drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c:		chip->ecc.bytes = 9;
+drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c:		chip->ecc.bytes = fls((1 + 8) * chip->ecc.size)	*
+drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c:				  (chip->ecc.strength / 8);
+drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c:	switch (chip->ecc.mode) {
+drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c:		chip->ecc.hwctl = ingenic_nand_ecc_hwctl;
+drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c:		chip->ecc.calculate = ingenic_nand_ecc_calculate;
+drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c:		chip->ecc.correct = ingenic_nand_ecc_correct;
+drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c:			 chip->ecc.strength, chip->ecc.size, chip->ecc.bytes);
+drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c:			chip->ecc.mode);
+drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c:	if (chip->ecc.mode != NAND_ECC_HW)
+drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c:	eccbytes = mtd->writesize / chip->ecc.size * chip->ecc.bytes;
+drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c:	if (chip->bbt_options & NAND_BBT_USE_FLASH)
+drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c:		chip->bbt_options |= NAND_BBT_NO_OOB;
+drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c:	chip->legacy.IO_ADDR_R = cs->base + nfc->soc_info->data_offset;
+drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c:	chip->legacy.IO_ADDR_W = cs->base + nfc->soc_info->data_offset;
+drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c:	chip->legacy.chip_delay = RB_DELAY_US;
+drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c:	chip->options = NAND_NO_SUBPAGE_WRITE;
+drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c:	chip->legacy.select_chip = ingenic_nand_select_chip;
+drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c:	chip->legacy.cmd_ctrl = ingenic_nand_cmd_ctrl;
+drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c:	chip->ecc.mode = NAND_ECC_HW;
+drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c:	chip->controller = &nfc->controller;
+drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c:	chip->controller->ops = &ingenic_nand_controller_ops;
+drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c:		nand_release(&chip->chip);
+drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c:		list_del(&chip->chip_list);
+drivers/mtd/nand/raw/internals.h:	if (!chip->controller || !chip->controller->ops ||
+drivers/mtd/nand/raw/internals.h:	    !chip->controller->ops->exec_op)
+drivers/mtd/nand/raw/internals.h:	if (WARN_ON(op->cs >= nanddev_ntargets(&chip->base)))
+drivers/mtd/nand/raw/internals.h:	return chip->controller->ops->exec_op(chip, op, false);
+drivers/mtd/nand/raw/internals.h:	if (!chip->controller || !chip->controller->ops ||
+drivers/mtd/nand/raw/internals.h:	    !chip->controller->ops->setup_data_interface)
+drivers/mtd/nand/raw/internals.h:	if (chip->options & NAND_KEEP_TIMINGS)
+drivers/mtd/nand/raw/lpc32xx_mlc.c:	if (section >= nand_chip->ecc.steps)
+drivers/mtd/nand/raw/lpc32xx_mlc.c:	oobregion->offset = ((section + 1) * 16) - nand_chip->ecc.bytes;
+drivers/mtd/nand/raw/lpc32xx_mlc.c:	oobregion->length = nand_chip->ecc.bytes;
+drivers/mtd/nand/raw/lpc32xx_mlc.c:	if (section >= nand_chip->ecc.steps)
+drivers/mtd/nand/raw/lpc32xx_mlc.c:	oobregion->length = 16 - nand_chip->ecc.bytes;
+drivers/mtd/nand/raw/lpc32xx_mlc.c:	uint8_t *oobbuf = chip->oob_poi;
+drivers/mtd/nand/raw/lpc32xx_mlc.c:	const uint8_t *oobbuf = chip->oob_poi;
+drivers/mtd/nand/raw/lpc32xx_mlc.c:	chip->ecc.mode = NAND_ECC_HW;
+drivers/mtd/nand/raw/lpc32xx_mlc.c:	chip->ecc.size = 512;
+drivers/mtd/nand/raw/lpc32xx_mlc.c:	nand_chip->legacy.cmd_ctrl = lpc32xx_nand_cmd_ctrl;
+drivers/mtd/nand/raw/lpc32xx_mlc.c:	nand_chip->legacy.dev_ready = lpc32xx_nand_device_ready;
+drivers/mtd/nand/raw/lpc32xx_mlc.c:	nand_chip->legacy.chip_delay = 25; /* us */
+drivers/mtd/nand/raw/lpc32xx_mlc.c:	nand_chip->legacy.IO_ADDR_R = MLC_DATA(host->io_base);
+drivers/mtd/nand/raw/lpc32xx_mlc.c:	nand_chip->legacy.IO_ADDR_W = MLC_DATA(host->io_base);
+drivers/mtd/nand/raw/lpc32xx_mlc.c:	nand_chip->ecc.hwctl = lpc32xx_ecc_enable;
+drivers/mtd/nand/raw/lpc32xx_mlc.c:	nand_chip->ecc.read_page_raw = lpc32xx_read_page;
+drivers/mtd/nand/raw/lpc32xx_mlc.c:	nand_chip->ecc.read_page = lpc32xx_read_page;
+drivers/mtd/nand/raw/lpc32xx_mlc.c:	nand_chip->ecc.write_page_raw = lpc32xx_write_page_lowlevel;
+drivers/mtd/nand/raw/lpc32xx_mlc.c:	nand_chip->ecc.write_page = lpc32xx_write_page_lowlevel;
+drivers/mtd/nand/raw/lpc32xx_mlc.c:	nand_chip->ecc.write_oob = lpc32xx_write_oob;
+drivers/mtd/nand/raw/lpc32xx_mlc.c:	nand_chip->ecc.read_oob = lpc32xx_read_oob;
+drivers/mtd/nand/raw/lpc32xx_mlc.c:	nand_chip->ecc.strength = 4;
+drivers/mtd/nand/raw/lpc32xx_mlc.c:	nand_chip->ecc.bytes = 10;
+drivers/mtd/nand/raw/lpc32xx_mlc.c:	nand_chip->legacy.waitfunc = lpc32xx_waitfunc;
+drivers/mtd/nand/raw/lpc32xx_mlc.c:	nand_chip->options = NAND_NO_SUBPAGE_WRITE;
+drivers/mtd/nand/raw/lpc32xx_mlc.c:	nand_chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
+drivers/mtd/nand/raw/lpc32xx_mlc.c:	nand_chip->bbt_td = &lpc32xx_nand_bbt;
+drivers/mtd/nand/raw/lpc32xx_mlc.c:	nand_chip->bbt_md = &lpc32xx_nand_bbt_mirror;
+drivers/mtd/nand/raw/lpc32xx_mlc.c:	nand_chip->legacy.dummy_controller.ops = &lpc32xx_nand_controller_ops;
+drivers/mtd/nand/raw/lpc32xx_slc.c:	return nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
+drivers/mtd/nand/raw/lpc32xx_slc.c:	return nand_prog_page_op(chip, page, mtd->writesize, chip->oob_poi,
+drivers/mtd/nand/raw/lpc32xx_slc.c:	for (i = 0; i < chip->ecc.steps; i++) {
+drivers/mtd/nand/raw/lpc32xx_slc.c:				       dma_buf + i * chip->ecc.size,
+drivers/mtd/nand/raw/lpc32xx_slc.c:				       mtd->writesize / chip->ecc.steps, dir);
+drivers/mtd/nand/raw/lpc32xx_slc.c:		if (i == chip->ecc.steps - 1)
+drivers/mtd/nand/raw/lpc32xx_slc.c:	host->ecc_buf[chip->ecc.steps - 1] =
+drivers/mtd/nand/raw/lpc32xx_slc.c:	status = lpc32xx_xfer(mtd, buf, chip->ecc.steps, 1);
+drivers/mtd/nand/raw/lpc32xx_slc.c:	chip->legacy.read_buf(chip, chip->oob_poi, mtd->oobsize);
+drivers/mtd/nand/raw/lpc32xx_slc.c:	lpc32xx_slc_ecc_copy(tmpecc, (uint32_t *) host->ecc_buf, chip->ecc.steps);
+drivers/mtd/nand/raw/lpc32xx_slc.c:	oobecc = chip->oob_poi + oobregion.offset;
+drivers/mtd/nand/raw/lpc32xx_slc.c:	for (i = 0; i < chip->ecc.steps; i++) {
+drivers/mtd/nand/raw/lpc32xx_slc.c:		stat = chip->ecc.correct(chip, buf, oobecc,
+drivers/mtd/nand/raw/lpc32xx_slc.c:					 &tmpecc[i * chip->ecc.bytes]);
+drivers/mtd/nand/raw/lpc32xx_slc.c:		buf += chip->ecc.size;
+drivers/mtd/nand/raw/lpc32xx_slc.c:		oobecc += chip->ecc.bytes;
+drivers/mtd/nand/raw/lpc32xx_slc.c:	chip->legacy.read_buf(chip, buf, chip->ecc.size * chip->ecc.steps);
+drivers/mtd/nand/raw/lpc32xx_slc.c:	chip->legacy.read_buf(chip, chip->oob_poi, mtd->oobsize);
+drivers/mtd/nand/raw/lpc32xx_slc.c:	error = lpc32xx_xfer(mtd, (uint8_t *)buf, chip->ecc.steps, 0);
+drivers/mtd/nand/raw/lpc32xx_slc.c:	pb = chip->oob_poi + oobregion.offset;
+drivers/mtd/nand/raw/lpc32xx_slc.c:	lpc32xx_slc_ecc_copy(pb, (uint32_t *)host->ecc_buf, chip->ecc.steps);
+drivers/mtd/nand/raw/lpc32xx_slc.c:	chip->legacy.write_buf(chip, chip->oob_poi, mtd->oobsize);
+drivers/mtd/nand/raw/lpc32xx_slc.c:				chip->ecc.size * chip->ecc.steps);
+drivers/mtd/nand/raw/lpc32xx_slc.c:	chip->legacy.write_buf(chip, chip->oob_poi, mtd->oobsize);
+drivers/mtd/nand/raw/lpc32xx_slc.c:	chip->ecc.size = 256;
+drivers/mtd/nand/raw/lpc32xx_slc.c:	chip->ecc.bytes = LPC32XX_SLC_DEV_ECC_BYTES;
+drivers/mtd/nand/raw/lpc32xx_slc.c:	chip->ecc.prepad = 0;
+drivers/mtd/nand/raw/lpc32xx_slc.c:	chip->ecc.postpad = 0;
+drivers/mtd/nand/raw/lpc32xx_slc.c:	if ((chip->bbt_options & NAND_BBT_USE_FLASH) &&
+drivers/mtd/nand/raw/lpc32xx_slc.c:		chip->bbt_td = &bbt_smallpage_main_descr;
+drivers/mtd/nand/raw/lpc32xx_slc.c:		chip->bbt_md = &bbt_smallpage_mirror_descr;
+drivers/mtd/nand/raw/lpc32xx_slc.c:	chip->legacy.IO_ADDR_R = SLC_DATA(host->io_base);
+drivers/mtd/nand/raw/lpc32xx_slc.c:	chip->legacy.IO_ADDR_W = SLC_DATA(host->io_base);
+drivers/mtd/nand/raw/lpc32xx_slc.c:	chip->legacy.cmd_ctrl = lpc32xx_nand_cmd_ctrl;
+drivers/mtd/nand/raw/lpc32xx_slc.c:	chip->legacy.dev_ready = lpc32xx_nand_device_ready;
+drivers/mtd/nand/raw/lpc32xx_slc.c:	chip->legacy.chip_delay = 20; /* 20us command delay time */
+drivers/mtd/nand/raw/lpc32xx_slc.c:	chip->ecc.mode = NAND_ECC_HW_SYNDROME;
+drivers/mtd/nand/raw/lpc32xx_slc.c:	chip->legacy.read_byte = lpc32xx_nand_read_byte;
+drivers/mtd/nand/raw/lpc32xx_slc.c:	chip->legacy.read_buf = lpc32xx_nand_read_buf;
+drivers/mtd/nand/raw/lpc32xx_slc.c:	chip->legacy.write_buf = lpc32xx_nand_write_buf;
+drivers/mtd/nand/raw/lpc32xx_slc.c:	chip->ecc.read_page_raw = lpc32xx_nand_read_page_raw_syndrome;
+drivers/mtd/nand/raw/lpc32xx_slc.c:	chip->ecc.read_page = lpc32xx_nand_read_page_syndrome;
+drivers/mtd/nand/raw/lpc32xx_slc.c:	chip->ecc.write_page_raw = lpc32xx_nand_write_page_raw_syndrome;
+drivers/mtd/nand/raw/lpc32xx_slc.c:	chip->ecc.write_page = lpc32xx_nand_write_page_syndrome;
+drivers/mtd/nand/raw/lpc32xx_slc.c:	chip->ecc.write_oob = lpc32xx_nand_write_oob_syndrome;
+drivers/mtd/nand/raw/lpc32xx_slc.c:	chip->ecc.read_oob = lpc32xx_nand_read_oob_syndrome;
+drivers/mtd/nand/raw/lpc32xx_slc.c:	chip->ecc.calculate = lpc32xx_nand_ecc_calculate;
+drivers/mtd/nand/raw/lpc32xx_slc.c:	chip->ecc.correct = nand_correct_data;
+drivers/mtd/nand/raw/lpc32xx_slc.c:	chip->ecc.strength = 1;
+drivers/mtd/nand/raw/lpc32xx_slc.c:	chip->ecc.hwctl = lpc32xx_nand_ecc_enable;
+drivers/mtd/nand/raw/lpc32xx_slc.c:	chip->legacy.dummy_controller.ops = &lpc32xx_nand_controller_ops;
+drivers/mtd/nand/raw/marvell_nand.c:	struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
+drivers/mtd/nand/raw/marvell_nand.c:	if (!(chip->options & NAND_BUSWIDTH_16))
+drivers/mtd/nand/raw/marvell_nand.c:	struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
+drivers/mtd/nand/raw/marvell_nand.c:	struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
+drivers/mtd/nand/raw/marvell_nand.c:	struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
+drivers/mtd/nand/raw/marvell_nand.c:	struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
+drivers/mtd/nand/raw/marvell_nand.c:	struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
+drivers/mtd/nand/raw/marvell_nand.c:	struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
+drivers/mtd/nand/raw/marvell_nand.c:	struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
+drivers/mtd/nand/raw/marvell_nand.c:		if (chip->ecc.algo == NAND_ECC_BCH)
+drivers/mtd/nand/raw/marvell_nand.c:	struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
+drivers/mtd/nand/raw/marvell_nand.c:		if (chip->ecc.algo == NAND_ECC_BCH)
+drivers/mtd/nand/raw/marvell_nand.c:					 spare, spare_len, chip->ecc.strength);
+drivers/mtd/nand/raw/marvell_nand.c:	struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
+drivers/mtd/nand/raw/marvell_nand.c:		if (chip->ecc.algo == NAND_ECC_BCH)
+drivers/mtd/nand/raw/marvell_nand.c:	struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
+drivers/mtd/nand/raw/marvell_nand.c:	marvell_nfc_select_target(chip, chip->cur_cs);
+drivers/mtd/nand/raw/marvell_nand.c:	return marvell_nfc_hw_ecc_hmg_do_read_page(chip, buf, chip->oob_poi,
+drivers/mtd/nand/raw/marvell_nand.c:	marvell_nfc_select_target(chip, chip->cur_cs);
+drivers/mtd/nand/raw/marvell_nand.c:	marvell_nfc_hw_ecc_hmg_do_read_page(chip, buf, chip->oob_poi, false,
+drivers/mtd/nand/raw/marvell_nand.c:	marvell_nfc_select_target(chip, chip->cur_cs);
+drivers/mtd/nand/raw/marvell_nand.c:	return marvell_nfc_hw_ecc_hmg_do_read_page(chip, buf, chip->oob_poi,
+drivers/mtd/nand/raw/marvell_nand.c:	struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
+drivers/mtd/nand/raw/marvell_nand.c:				  PSEC_TO_MSEC(chip->data_interface.timings.sdr.tPROG_max));
+drivers/mtd/nand/raw/marvell_nand.c:	marvell_nfc_select_target(chip, chip->cur_cs);
+drivers/mtd/nand/raw/marvell_nand.c:	return marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi,
+drivers/mtd/nand/raw/marvell_nand.c:	marvell_nfc_select_target(chip, chip->cur_cs);
+drivers/mtd/nand/raw/marvell_nand.c:	ret = marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi,
+drivers/mtd/nand/raw/marvell_nand.c:	marvell_nfc_select_target(chip, chip->cur_cs);
+drivers/mtd/nand/raw/marvell_nand.c:	return marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi,
+drivers/mtd/nand/raw/marvell_nand.c:	u8 *oob = chip->oob_poi;
+drivers/mtd/nand/raw/marvell_nand.c:	marvell_nfc_select_target(chip, chip->cur_cs);
+drivers/mtd/nand/raw/marvell_nand.c:		memset(chip->oob_poi, 0xFF, mtd->oobsize);
+drivers/mtd/nand/raw/marvell_nand.c:	struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
+drivers/mtd/nand/raw/marvell_nand.c:	u8 *data = buf, *spare = chip->oob_poi;
+drivers/mtd/nand/raw/marvell_nand.c:	marvell_nfc_select_target(chip, chip->cur_cs);
+drivers/mtd/nand/raw/marvell_nand.c:		memset(chip->oob_poi, 0xFF, mtd->oobsize);
+drivers/mtd/nand/raw/marvell_nand.c:						   chip->oob_poi + spare_off, spare_len,
+drivers/mtd/nand/raw/marvell_nand.c:					   chip->oob_poi + ecc_off, ecc_len,
+drivers/mtd/nand/raw/marvell_nand.c:					      chip->oob_poi + spare_off, spare_len,
+drivers/mtd/nand/raw/marvell_nand.c:					      chip->oob_poi + ecc_off, ecc_len,
+drivers/mtd/nand/raw/marvell_nand.c:	return chip->ecc.read_page_raw(chip, buf, true, page);
+drivers/mtd/nand/raw/marvell_nand.c:	return chip->ecc.read_page(chip, buf, true, page);
+drivers/mtd/nand/raw/marvell_nand.c:	marvell_nfc_select_target(chip, chip->cur_cs);
+drivers/mtd/nand/raw/marvell_nand.c:			nand_write_data_op(chip, chip->oob_poi + spare_offset,
+drivers/mtd/nand/raw/marvell_nand.c:			nand_write_data_op(chip, chip->oob_poi + ecc_offset,
+drivers/mtd/nand/raw/marvell_nand.c:	struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
+drivers/mtd/nand/raw/marvell_nand.c:	const u8 *spare = chip->oob_poi;
+drivers/mtd/nand/raw/marvell_nand.c:	marvell_nfc_select_target(chip, chip->cur_cs);
+drivers/mtd/nand/raw/marvell_nand.c:		memset(chip->oob_poi, 0xFF, mtd->oobsize);
+drivers/mtd/nand/raw/marvell_nand.c:				  PSEC_TO_MSEC(chip->data_interface.timings.sdr.tPROG_max));
+drivers/mtd/nand/raw/marvell_nand.c:	return chip->ecc.write_page_raw(chip, buf, true, page);
+drivers/mtd/nand/raw/marvell_nand.c:	return chip->ecc.write_page(chip, buf, true, page);
+drivers/mtd/nand/raw/marvell_nand.c:	struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
+drivers/mtd/nand/raw/marvell_nand.c:	struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
+drivers/mtd/nand/raw/marvell_nand.c:		struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
+drivers/mtd/nand/raw/marvell_nand.c:		struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
+drivers/mtd/nand/raw/marvell_nand.c:	struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
+drivers/mtd/nand/raw/marvell_nand.c:	struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
+drivers/mtd/nand/raw/marvell_nand.c:			chip->bbt_options |= NAND_BBT_NO_OOB_BBM;
+drivers/mtd/nand/raw/marvell_nand.c:		chip->ecc.algo = NAND_ECC_HAMMING;
+drivers/mtd/nand/raw/marvell_nand.c:		chip->ecc.algo = NAND_ECC_BCH;
+drivers/mtd/nand/raw/marvell_nand.c:	struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
+drivers/mtd/nand/raw/marvell_nand.c:		if (chip->base.eccreq.step_size && chip->base.eccreq.strength) {
+drivers/mtd/nand/raw/marvell_nand.c:			ecc->size = chip->base.eccreq.step_size;
+drivers/mtd/nand/raw/marvell_nand.c:			ecc->strength = chip->base.eccreq.strength;
+drivers/mtd/nand/raw/marvell_nand.c:	struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
+drivers/mtd/nand/raw/marvell_nand.c:	struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
+drivers/mtd/nand/raw/marvell_nand.c:		chip->bbt_options |= NAND_BBT_USE_FLASH;
+drivers/mtd/nand/raw/marvell_nand.c:	if (chip->bbt_options & NAND_BBT_USE_FLASH) {
+drivers/mtd/nand/raw/marvell_nand.c:		chip->bbt_options |= NAND_BBT_NO_OOB_BBM;
+drivers/mtd/nand/raw/marvell_nand.c:		chip->bbt_td = &bbt_main_descr;
+drivers/mtd/nand/raw/marvell_nand.c:		chip->bbt_md = &bbt_mirror_descr;
+drivers/mtd/nand/raw/marvell_nand.c:	/* Save the chip-specific fields of NDCR */
+drivers/mtd/nand/raw/marvell_nand.c:	if (chip->options & NAND_BUSWIDTH_16)
+drivers/mtd/nand/raw/marvell_nand.c:	if (chip->options & NAND_ROW_ADDR_3)
+drivers/mtd/nand/raw/marvell_nand.c:		chip->ecc.size = pdata->ecc_step_size;
+drivers/mtd/nand/raw/marvell_nand.c:		chip->ecc.strength = pdata->ecc_strength;
+drivers/mtd/nand/raw/marvell_nand.c:	ret = marvell_nand_ecc_init(mtd, &chip->ecc);
+drivers/mtd/nand/raw/marvell_nand.c:	if (chip->ecc.mode == NAND_ECC_HW) {
+drivers/mtd/nand/raw/marvell_nand.c:		chip->options |= NAND_NO_SUBPAGE_WRITE;
+drivers/mtd/nand/raw/marvell_nand.c:	chip->controller = &nfc->controller;
+drivers/mtd/nand/raw/marvell_nand.c:		chip->options |= NAND_KEEP_TIMINGS;
+drivers/mtd/nand/raw/marvell_nand.c:	chip->ecc.mode = NAND_ECC_HW;
+drivers/mtd/nand/raw/marvell_nand.c:	chip->options |= NAND_BUSWIDTH_AUTO;
+drivers/mtd/nand/raw/marvell_nand.c:		marvell_nfc_wait_ndrun(&chip->chip);
+drivers/mtd/nand/raw/meson_nand.c:	if (chip < 0 || WARN_ON_ONCE(chip >= meson_chip->nsels))
+drivers/mtd/nand/raw/meson_nand.c:	nfc->param.chip_select = meson_chip->sels[chip] ? NAND_CE1 : NAND_CE0;
+drivers/mtd/nand/raw/meson_nand.c:	nfc->timing.twb = meson_chip->twb;
+drivers/mtd/nand/raw/meson_nand.c:	nfc->timing.tadl = meson_chip->tadl;
+drivers/mtd/nand/raw/meson_nand.c:	nfc->timing.tbers_max = meson_chip->tbers_max;
+drivers/mtd/nand/raw/meson_nand.c:	if (nfc->clk_rate != meson_chip->clk_rate) {
+drivers/mtd/nand/raw/meson_nand.c:		ret = clk_set_rate(nfc->device_clk, meson_chip->clk_rate);
+drivers/mtd/nand/raw/meson_nand.c:		nfc->clk_rate = meson_chip->clk_rate;
+drivers/mtd/nand/raw/meson_nand.c:	if (nfc->bus_timing != meson_chip->bus_timing) {
+drivers/mtd/nand/raw/meson_nand.c:		value = (NFC_CLK_CYCLE - 1) | (meson_chip->bus_timing << 5);
+drivers/mtd/nand/raw/meson_nand.c:		nfc->bus_timing =  meson_chip->bus_timing;
+drivers/mtd/nand/raw/meson_nand.c:	u32 bch = meson_chip->bch_mode, cmd;
+drivers/mtd/nand/raw/meson_nand.c:	return meson_chip->data_buf + len;
+drivers/mtd/nand/raw/meson_nand.c:	return meson_chip->data_buf + len;
+drivers/mtd/nand/raw/meson_nand.c:		info = &meson_chip->info_buf[i];
+drivers/mtd/nand/raw/meson_nand.c:		info = &meson_chip->info_buf[i];
+drivers/mtd/nand/raw/meson_nand.c:		info = &meson_chip->info_buf[i];
+drivers/mtd/nand/raw/meson_nand.c:	ret = meson_nfc_dma_buffer_setup(nand, meson_chip->data_buf,
+drivers/mtd/nand/raw/meson_nand.c:					 data_len, meson_chip->info_buf,
+drivers/mtd/nand/raw/meson_nand.c:	memcpy(meson_chip->data_buf, buf, mtd->writesize);
+drivers/mtd/nand/raw/meson_nand.c:	memset(meson_chip->info_buf, 0, nand->ecc.steps * PER_INFO_BYTE);
+drivers/mtd/nand/raw/meson_nand.c:	info = &meson_chip->info_buf[neccpages - 1];
+drivers/mtd/nand/raw/meson_nand.c:	ret = meson_nfc_dma_buffer_setup(nand, meson_chip->data_buf,
+drivers/mtd/nand/raw/meson_nand.c:					 data_len, meson_chip->info_buf,
+drivers/mtd/nand/raw/meson_nand.c:	} else if (buf && buf != meson_chip->data_buf) {
+drivers/mtd/nand/raw/meson_nand.c:		memcpy(buf, meson_chip->data_buf, mtd->writesize);
+drivers/mtd/nand/raw/meson_nand.c:					  meson_chip->level1_divider *
+drivers/mtd/nand/raw/meson_nand.c:	kfree(meson_chip->info_buf);
+drivers/mtd/nand/raw/meson_nand.c:	kfree(meson_chip->data_buf);
+drivers/mtd/nand/raw/meson_nand.c:	meson_chip->data_buf = kmalloc(page_bytes, GFP_KERNEL);
+drivers/mtd/nand/raw/meson_nand.c:	if (!meson_chip->data_buf)
+drivers/mtd/nand/raw/meson_nand.c:	meson_chip->info_buf = kmalloc(info_bytes, GFP_KERNEL);
+drivers/mtd/nand/raw/meson_nand.c:	if (!meson_chip->info_buf) {
+drivers/mtd/nand/raw/meson_nand.c:		kfree(meson_chip->data_buf);
+drivers/mtd/nand/raw/meson_nand.c:	meson_chip->twb = DIV_ROUND_UP(PSEC_TO_NSEC(timings->tWB_max),
+drivers/mtd/nand/raw/meson_nand.c:	meson_chip->tadl = DIV_ROUND_UP(PSEC_TO_NSEC(timings->tADL_min),
+drivers/mtd/nand/raw/meson_nand.c:	meson_chip->tbers_max = ilog2(tbers_clocks);
+drivers/mtd/nand/raw/meson_nand.c:		meson_chip->tbers_max++;
+drivers/mtd/nand/raw/meson_nand.c:	meson_chip->level1_divider = div;
+drivers/mtd/nand/raw/meson_nand.c:	meson_chip->clk_rate = 1000000000 / meson_chip->level1_divider;
+drivers/mtd/nand/raw/meson_nand.c:	meson_chip->bus_timing = (bt_min + bt_max) / 2 + 1;
+drivers/mtd/nand/raw/meson_nand.c:			meson_chip->bch_mode = meson_ecc[i].bch;
+drivers/mtd/nand/raw/meson_nand.c:					   meson_chip->sels[0]);
+drivers/mtd/nand/raw/meson_nand.c:	meson_chip->nsels = nsels;
+drivers/mtd/nand/raw/meson_nand.c:	nand = &meson_chip->nand;
+drivers/mtd/nand/raw/meson_nand.c:	list_add_tail(&meson_chip->node, &nfc->chips);
+drivers/mtd/nand/raw/meson_nand.c:		mtd = nand_to_mtd(&meson_chip->nand);
+drivers/mtd/nand/raw/meson_nand.c:		meson_nfc_free_buffer(&meson_chip->nand);
+drivers/mtd/nand/raw/meson_nand.c:		nand_cleanup(&meson_chip->nand);
+drivers/mtd/nand/raw/meson_nand.c:		list_del(&meson_chip->node);
+drivers/mtd/nand/raw/mpc5121_nfc.c:	u32 pagemask = chip->pagemask;
+drivers/mtd/nand/raw/mpc5121_nfc.c:		if (chip->options & NAND_BUSWIDTH_16)
+drivers/mtd/nand/raw/mpc5121_nfc.c:		chip->options |= NAND_BUSWIDTH_16;
+drivers/mtd/nand/raw/mpc5121_nfc.c:	chip->legacy.dev_ready = mpc5121_nfc_dev_ready;
+drivers/mtd/nand/raw/mpc5121_nfc.c:	chip->legacy.cmdfunc = mpc5121_nfc_command;
+drivers/mtd/nand/raw/mpc5121_nfc.c:	chip->legacy.read_byte = mpc5121_nfc_read_byte;
+drivers/mtd/nand/raw/mpc5121_nfc.c:	chip->legacy.read_buf = mpc5121_nfc_read_buf;
+drivers/mtd/nand/raw/mpc5121_nfc.c:	chip->legacy.write_buf = mpc5121_nfc_write_buf;
+drivers/mtd/nand/raw/mpc5121_nfc.c:	chip->legacy.select_chip = mpc5121_nfc_select_chip;
+drivers/mtd/nand/raw/mpc5121_nfc.c:	chip->legacy.set_features = nand_get_set_features_notsupp;
+drivers/mtd/nand/raw/mpc5121_nfc.c:	chip->legacy.get_features = nand_get_set_features_notsupp;
+drivers/mtd/nand/raw/mpc5121_nfc.c:	chip->bbt_options = NAND_BBT_USE_FLASH;
+drivers/mtd/nand/raw/mpc5121_nfc.c:	chip->ecc.mode = NAND_ECC_SOFT;
+drivers/mtd/nand/raw/mpc5121_nfc.c:	chip->ecc.algo = NAND_ECC_HAMMING;
+drivers/mtd/nand/raw/mpc5121_nfc.c:	/* Support external chip-select logic on ADS5121 board */
+drivers/mtd/nand/raw/mpc5121_nfc.c:		chip->legacy.select_chip = ads5121_select_chip;
+drivers/mtd/nand/raw/mtk_nand.c:	return (u8 *)p + i * chip->ecc.size;
+drivers/mtd/nand/raw/mtk_nand.c:		poi = chip->oob_poi + (i + 1) * mtk_nand->fdm.reg_size;
+drivers/mtd/nand/raw/mtk_nand.c:		poi = chip->oob_poi;
+drivers/mtd/nand/raw/mtk_nand.c:		poi = chip->oob_poi + i * mtk_nand->fdm.reg_size;
+drivers/mtd/nand/raw/mtk_nand.c:	return chip->ecc.size + mtk_nand->spare_per_sector;
+drivers/mtd/nand/raw/mtk_nand.c:	return nfc->buffer + i * mtk_data_len(chip) + chip->ecc.size;
+drivers/mtd/nand/raw/mtk_nand.c:		if (chip->ecc.size == 512)
+drivers/mtd/nand/raw/mtk_nand.c:		if (chip->ecc.size == 512)
+drivers/mtd/nand/raw/mtk_nand.c:		if (chip->ecc.size == 512)
+drivers/mtd/nand/raw/mtk_nand.c:	if (chip->ecc.size == 1024)
+drivers/mtd/nand/raw/mtk_nand.c:	nfc->ecc_cfg.strength = chip->ecc.strength;
+drivers/mtd/nand/raw/mtk_nand.c:	nfc->ecc_cfg.len = chip->ecc.size + mtk_nand->fdm.ecc_size;
+drivers/mtd/nand/raw/mtk_nand.c:	int size = chip->ecc.size + mtk_nand->fdm.reg_size;
+drivers/mtd/nand/raw/mtk_nand.c:		bad_pos += nand->bad_mark.sec * chip->ecc.size;
+drivers/mtd/nand/raw/mtk_nand.c:	swap(chip->oob_poi[0], buf[bad_pos]);
+drivers/mtd/nand/raw/mtk_nand.c:	start = offset / chip->ecc.size;
+drivers/mtd/nand/raw/mtk_nand.c:	end = DIV_ROUND_UP(offset + len, chip->ecc.size);
+drivers/mtd/nand/raw/mtk_nand.c:	for (i = 0; i < chip->ecc.steps; i++) {
+drivers/mtd/nand/raw/mtk_nand.c:		       chip->ecc.size);
+drivers/mtd/nand/raw/mtk_nand.c:	for (i = 0; i < chip->ecc.steps; i++) {
+drivers/mtd/nand/raw/mtk_nand.c:			       chip->ecc.size);
+drivers/mtd/nand/raw/mtk_nand.c:	for (i = 0; i < chip->ecc.steps; i++) {
+drivers/mtd/nand/raw/mtk_nand.c:	nfi_writel(nfc, chip->ecc.steps << CON_SEC_SHIFT, NFI_CON);
+drivers/mtd/nand/raw/mtk_nand.c:					ADDRCNTR_SEC(reg) >= chip->ecc.steps,
+drivers/mtd/nand/raw/mtk_nand.c:		memset(buf, 0xff, sectors * chip->ecc.size);
+drivers/mtd/nand/raw/mtk_nand.c:	start = data_offs / chip->ecc.size;
+drivers/mtd/nand/raw/mtk_nand.c:	end = DIV_ROUND_UP(data_offs + readlen, chip->ecc.size);
+drivers/mtd/nand/raw/mtk_nand.c:	column = start * (chip->ecc.size + spare);
+drivers/mtd/nand/raw/mtk_nand.c:	len = sectors * chip->ecc.size + (raw ? sectors * spare : 0);
+drivers/mtd/nand/raw/mtk_nand.c:	buf = bufpoi + start * chip->ecc.size;
+drivers/mtd/nand/raw/mtk_nand.c:	for (i = 0; i < chip->ecc.steps; i++) {
+drivers/mtd/nand/raw/mtk_nand.c:			       chip->ecc.size);
+drivers/mtd/nand/raw/mtk_nand.c:	eccsteps = mtd->writesize / chip->ecc.size;
+drivers/mtd/nand/raw/mtk_nand.c:	eccsteps = mtd->writesize / chip->ecc.size;
+drivers/mtd/nand/raw/mtk_nand.c:	fdm->reg_size = chip->spare_per_sector - ecc_bytes;
+drivers/mtd/nand/raw/mtk_nand.c:	if (chip->options & NAND_BUSWIDTH_16) {
+drivers/mtd/nand/raw/mtk_nand.c:	if (chip->bbt_options & NAND_BBT_USE_FLASH)
+drivers/mtd/nand/raw/mtk_nand.c:		chip->bbt_options |= NAND_BBT_NO_OOB;
+drivers/mtd/nand/raw/mtk_nand.c:	chip->nsels = nsels;
+drivers/mtd/nand/raw/mtk_nand.c:		chip->sels[i] = tmp;
+drivers/mtd/nand/raw/mtk_nand.c:	nand = &chip->nand;
+drivers/mtd/nand/raw/mtk_nand.c:	list_add_tail(&chip->node, &nfc->chips);
+drivers/mtd/nand/raw/mtk_nand.c:		nand_release(&chip->nand);
+drivers/mtd/nand/raw/mtk_nand.c:		list_del(&chip->node);
+drivers/mtd/nand/raw/mtk_nand.c:		nand = &chip->nand;
+drivers/mtd/nand/raw/mtk_nand.c:		for (i = 0; i < chip->nsels; i++)
+drivers/mtd/nand/raw/mxc_nand.c:			if (nand_chip->options & NAND_ROW_ADDR_3) {
+drivers/mtd/nand/raw/mxc_nand.c:	if (chip->ecc.mode != NAND_ECC_HW)
+drivers/mtd/nand/raw/mxc_nand.c:	if (chip->ecc.mode != NAND_ECC_HW)
+drivers/mtd/nand/raw/mxc_nand.c:		oob_buf = chip->oob_poi;
+drivers/mtd/nand/raw/mxc_nand.c:		oob_buf = chip->oob_poi;
+drivers/mtd/nand/raw/mxc_nand.c:	return host->devtype_data->read_page(chip, NULL, chip->oob_poi, 0,
+drivers/mtd/nand/raw/mxc_nand.c:	copy_spare(mtd, false, chip->oob_poi);
+drivers/mtd/nand/raw/mxc_nand.c:	if (nand_chip->options & NAND_BUSWIDTH_16) {
+drivers/mtd/nand/raw/mxc_nand.c:	if (section >= nand_chip->ecc.steps)
+drivers/mtd/nand/raw/mxc_nand.c:	if (section > nand_chip->ecc.steps)
+drivers/mtd/nand/raw/mxc_nand.c:		if (section < nand_chip->ecc.steps)
+drivers/mtd/nand/raw/mxc_nand.c:	int stepsize = nand_chip->ecc.bytes == 9 ? 16 : 26;
+drivers/mtd/nand/raw/mxc_nand.c:	if (section >= nand_chip->ecc.steps)
+drivers/mtd/nand/raw/mxc_nand.c:	oobregion->length = nand_chip->ecc.bytes;
+drivers/mtd/nand/raw/mxc_nand.c:	int stepsize = nand_chip->ecc.bytes == 9 ? 16 : 26;
+drivers/mtd/nand/raw/mxc_nand.c:	if (section >= nand_chip->ecc.steps)
+drivers/mtd/nand/raw/mxc_nand.c:	if (nand_chip->ecc.mode == NAND_ECC_HW && mtd->writesize)
+drivers/mtd/nand/raw/mxc_nand.c:		if (nand_chip->ecc.mode == NAND_ECC_HW)
+drivers/mtd/nand/raw/mxc_nand.c:	addr_phases = fls(chip->pagemask) >> 3;
+drivers/mtd/nand/raw/mxc_nand.c:		if (chip->ecc.mode == NAND_ECC_HW)
+drivers/mtd/nand/raw/mxc_nand.c:	if (!(chip->options & NAND_BUSWIDTH_16))
+drivers/mtd/nand/raw/mxc_nand.c:		chip->legacy.write_byte(chip, subfeature_param[i]);
+drivers/mtd/nand/raw/mxc_nand.c:		*subfeature_param++ = chip->legacy.read_byte(chip);
+drivers/mtd/nand/raw/mxc_nand.c:	switch (chip->ecc.mode) {
+drivers/mtd/nand/raw/mxc_nand.c:		chip->ecc.read_page = mxc_nand_read_page;
+drivers/mtd/nand/raw/mxc_nand.c:		chip->ecc.read_page_raw = mxc_nand_read_page_raw;
+drivers/mtd/nand/raw/mxc_nand.c:		chip->ecc.read_oob = mxc_nand_read_oob;
+drivers/mtd/nand/raw/mxc_nand.c:		chip->ecc.write_page = mxc_nand_write_page_ecc;
+drivers/mtd/nand/raw/mxc_nand.c:		chip->ecc.write_page_raw = mxc_nand_write_page_raw;
+drivers/mtd/nand/raw/mxc_nand.c:		chip->ecc.write_oob = mxc_nand_write_oob;
+drivers/mtd/nand/raw/mxc_nand.c:	if (chip->bbt_options & NAND_BBT_USE_FLASH) {
+drivers/mtd/nand/raw/mxc_nand.c:		chip->bbt_td = &bbt_main_descr;
+drivers/mtd/nand/raw/mxc_nand.c:		chip->bbt_md = &bbt_mirror_descr;
+drivers/mtd/nand/raw/mxc_nand.c:	if (!chip->ecc.bytes) {
+drivers/mtd/nand/raw/mxc_nand.c:			chip->ecc.bytes = 18;
+drivers/mtd/nand/raw/mxc_nand.c:			chip->ecc.bytes = 9;
+drivers/mtd/nand/raw/mxc_nand.c:	if (chip->ecc.mode == NAND_ECC_HW) {
+drivers/mtd/nand/raw/mxc_nand.c:			chip->ecc.strength = 1;
+drivers/mtd/nand/raw/mxc_nand.c:			chip->ecc.strength = (host->eccsize == 4) ? 4 : 8;
+drivers/mtd/nand/raw/mxic_nand.c:	nand_chip->priv = nfc;
+drivers/mtd/nand/raw/mxic_nand.c:	nand_chip->controller = &nfc->controller;
+drivers/mtd/nand/raw/nand_amd.c:	memorg = nanddev_get_memorg(&chip->base);
+drivers/mtd/nand/raw/nand_amd.c:	if (chip->id.data[4] != 0x00 && chip->id.data[5] == 0x00 &&
+drivers/mtd/nand/raw/nand_amd.c:	    chip->id.data[6] == 0x00 && chip->id.data[7] == 0x00 &&
+drivers/mtd/nand/raw/nand_amd.c:		memorg->pages_per_eraseblock <<= ((chip->id.data[3] & 0x03) << 1);
+drivers/mtd/nand/raw/nand_amd.c:		chip->options |= NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE |
+drivers/mtd/nand/raw/nand_base.c:	struct nand_ecc_ctrl *ecc = &chip->ecc;
+drivers/mtd/nand/raw/nand_base.c:	struct nand_ecc_ctrl *ecc = &chip->ecc;
+drivers/mtd/nand/raw/nand_base.c:	struct nand_ecc_ctrl *ecc = &chip->ecc;
+drivers/mtd/nand/raw/nand_base.c:	struct nand_ecc_ctrl *ecc = &chip->ecc;
+drivers/mtd/nand/raw/nand_base.c:	struct nand_ecc_ctrl *ecc = &chip->ecc;
+drivers/mtd/nand/raw/nand_base.c:	if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
+drivers/mtd/nand/raw/nand_base.c:	if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
+drivers/mtd/nand/raw/nand_base.c:	if (WARN_ON(cs > nanddev_ntargets(&chip->base)))
+drivers/mtd/nand/raw/nand_base.c:	chip->cur_cs = cs;
+drivers/mtd/nand/raw/nand_base.c:	if (chip->legacy.select_chip)
+drivers/mtd/nand/raw/nand_base.c:		chip->legacy.select_chip(chip, cs);
+drivers/mtd/nand/raw/nand_base.c:	if (chip->legacy.select_chip)
+drivers/mtd/nand/raw/nand_base.c:		chip->legacy.select_chip(chip, -1);
+drivers/mtd/nand/raw/nand_base.c:	chip->cur_cs = -1;
+drivers/mtd/nand/raw/nand_base.c:	mutex_unlock(&chip->controller->lock);
+drivers/mtd/nand/raw/nand_base.c:	mutex_unlock(&chip->lock);
+drivers/mtd/nand/raw/nand_base.c:			 chip->page_shift) & chip->pagemask;
+drivers/mtd/nand/raw/nand_base.c:	if (page == 0 && !(chip->options & bbm_flags))
+drivers/mtd/nand/raw/nand_base.c:	if (page == 0 && chip->options & NAND_BBM_FIRSTPAGE)
+drivers/mtd/nand/raw/nand_base.c:	if (page <= 1 && chip->options & NAND_BBM_SECONDPAGE)
+drivers/mtd/nand/raw/nand_base.c:	if (page <= last_page && chip->options & NAND_BBM_LASTPAGE)
+drivers/mtd/nand/raw/nand_base.c:	first_page = (int)(ofs >> chip->page_shift) & chip->pagemask;
+drivers/mtd/nand/raw/nand_base.c:		res = chip->ecc.read_oob(chip, first_page + page_offset);
+drivers/mtd/nand/raw/nand_base.c:		bad = chip->oob_poi[chip->badblockpos];
+drivers/mtd/nand/raw/nand_base.c:		if (likely(chip->badblockbits == 8))
+drivers/mtd/nand/raw/nand_base.c:			res = hweight8(bad) < chip->badblockbits;
+drivers/mtd/nand/raw/nand_base.c:	if (chip->legacy.block_bad)
+drivers/mtd/nand/raw/nand_base.c:		return chip->legacy.block_bad(chip, ofs);
+drivers/mtd/nand/raw/nand_base.c:	mutex_lock(&chip->lock);
+drivers/mtd/nand/raw/nand_base.c:	if (chip->suspended) {
+drivers/mtd/nand/raw/nand_base.c:		mutex_unlock(&chip->lock);
+drivers/mtd/nand/raw/nand_base.c:	mutex_lock(&chip->controller->lock);
+drivers/mtd/nand/raw/nand_base.c:	if (chip->options & NAND_BROKEN_XD)
+drivers/mtd/nand/raw/nand_base.c:	memset(chip->oob_poi, 0xff, mtd->oobsize);
+drivers/mtd/nand/raw/nand_base.c:		memcpy(chip->oob_poi + ops->ooboffs, oob, len);
+drivers/mtd/nand/raw/nand_base.c:		ret = mtd_ooblayout_set_databytes(mtd, oob, chip->oob_poi,
+drivers/mtd/nand/raw/nand_base.c:	chipnr = (int)(to >> chip->chip_shift);
+drivers/mtd/nand/raw/nand_base.c:	page = (int)(to >> chip->page_shift);
+drivers/mtd/nand/raw/nand_base.c:	if (page == chip->pagecache.page)
+drivers/mtd/nand/raw/nand_base.c:		chip->pagecache.page = -1;
+drivers/mtd/nand/raw/nand_base.c:		status = chip->ecc.write_oob_raw(chip, page & chip->pagemask);
+drivers/mtd/nand/raw/nand_base.c:		status = chip->ecc.write_oob(chip, page & chip->pagemask);
+drivers/mtd/nand/raw/nand_base.c:	ops.ooboffs = chip->badblockpos;
+drivers/mtd/nand/raw/nand_base.c:	if (chip->options & NAND_BUSWIDTH_16) {
+drivers/mtd/nand/raw/nand_base.c:	if (chip->legacy.block_markbad)
+drivers/mtd/nand/raw/nand_base.c:		return chip->legacy.block_markbad(chip, ofs);
+drivers/mtd/nand/raw/nand_base.c: * specify how to write bad block markers to OOB (chip->legacy.block_markbad).
+drivers/mtd/nand/raw/nand_base.c:	if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
+drivers/mtd/nand/raw/nand_base.c:		einfo.len = 1ULL << chip->phys_erase_shift;
+drivers/mtd/nand/raw/nand_base.c:	if (chip->bbt) {
+drivers/mtd/nand/raw/nand_base.c:	if (!chip->bbt)
+drivers/mtd/nand/raw/nand_base.c:	if (chip->bbt)
+drivers/mtd/nand/raw/nand_base.c:	timings = nand_get_sdr_timings(&chip->data_interface);
+drivers/mtd/nand/raw/nand_base.c:		if (chip->legacy.dev_ready) {
+drivers/mtd/nand/raw/nand_base.c:			if (chip->legacy.dev_ready(chip))
+drivers/mtd/nand/raw/nand_base.c:	return (chip->parameters.supports_set_get_features &&
+drivers/mtd/nand/raw/nand_base.c:		test_bit(addr, chip->parameters.get_feature_list));
+drivers/mtd/nand/raw/nand_base.c:	return (chip->parameters.supports_set_get_features &&
+drivers/mtd/nand/raw/nand_base.c:		test_bit(addr, chip->parameters.set_feature_list));
+drivers/mtd/nand/raw/nand_base.c:	ret = chip->controller->ops->setup_data_interface(chip, chipnr,
+drivers/mtd/nand/raw/nand_base.c:							&chip->data_interface);
+drivers/mtd/nand/raw/nand_base.c:		chip->onfi_timing_mode_default,
+drivers/mtd/nand/raw/nand_base.c:	ret = chip->controller->ops->setup_data_interface(chip, chipnr,
+drivers/mtd/nand/raw/nand_base.c:							&chip->data_interface);
+drivers/mtd/nand/raw/nand_base.c:	if (tmode_param[0] != chip->onfi_timing_mode_default) {
+drivers/mtd/nand/raw/nand_base.c:			chip->onfi_timing_mode_default);
+drivers/mtd/nand/raw/nand_base.c: * function nand_chip->data_interface is initialized with the best timing mode
+drivers/mtd/nand/raw/nand_base.c:	if (chip->parameters.onfi) {
+drivers/mtd/nand/raw/nand_base.c:		modes = chip->parameters.onfi->async_timing_mode;
+drivers/mtd/nand/raw/nand_base.c:		if (!chip->onfi_timing_mode_default)
+drivers/mtd/nand/raw/nand_base.c:		modes = GENMASK(chip->onfi_timing_mode_default, 0);
+drivers/mtd/nand/raw/nand_base.c:		ret = chip->controller->ops->setup_data_interface(chip,
+drivers/mtd/nand/raw/nand_base.c:						 &chip->data_interface);
+drivers/mtd/nand/raw/nand_base.c:			chip->onfi_timing_mode_default = mode;
+drivers/mtd/nand/raw/nand_base.c:	if (chip->options & NAND_BUSWIDTH_16) {
+drivers/mtd/nand/raw/nand_base.c:		nand_get_sdr_timings(&chip->data_interface);
+drivers/mtd/nand/raw/nand_base.c:	struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
+drivers/mtd/nand/raw/nand_base.c:		 !(chip->options & NAND_BUSWIDTH_16))
+drivers/mtd/nand/raw/nand_base.c:	if (chip->options & NAND_ROW_ADDR_3) {
+drivers/mtd/nand/raw/nand_base.c:		nand_get_sdr_timings(&chip->data_interface);
+drivers/mtd/nand/raw/nand_base.c:	struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
+drivers/mtd/nand/raw/nand_base.c:	if (chip->options & NAND_ROW_ADDR_3) {
+drivers/mtd/nand/raw/nand_base.c:	chip->legacy.cmdfunc(chip, NAND_CMD_READ0, offset_in_page, page);
+drivers/mtd/nand/raw/nand_base.c:		chip->legacy.read_buf(chip, buf, len);
+drivers/mtd/nand/raw/nand_base.c:			nand_get_sdr_timings(&chip->data_interface);
+drivers/mtd/nand/raw/nand_base.c:		struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
+drivers/mtd/nand/raw/nand_base.c:	chip->legacy.cmdfunc(chip, NAND_CMD_PARAM, page, -1);
+drivers/mtd/nand/raw/nand_base.c:		p[i] = chip->legacy.read_byte(chip);
+drivers/mtd/nand/raw/nand_base.c:			nand_get_sdr_timings(&chip->data_interface);
+drivers/mtd/nand/raw/nand_base.c:		struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
+drivers/mtd/nand/raw/nand_base.c:	chip->legacy.cmdfunc(chip, NAND_CMD_RNDOUT, offset_in_page, -1);
+drivers/mtd/nand/raw/nand_base.c:		chip->legacy.read_buf(chip, buf, len);
+drivers/mtd/nand/raw/nand_base.c:	chip->legacy.cmdfunc(chip, NAND_CMD_READOOB, offset_in_oob, page);
+drivers/mtd/nand/raw/nand_base.c:		chip->legacy.read_buf(chip, buf, len);
+drivers/mtd/nand/raw/nand_base.c:		nand_get_sdr_timings(&chip->data_interface);
+drivers/mtd/nand/raw/nand_base.c:	struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
+drivers/mtd/nand/raw/nand_base.c:	if (chip->options & NAND_ROW_ADDR_3)
+drivers/mtd/nand/raw/nand_base.c:			 !(chip->options & NAND_BUSWIDTH_16))
+drivers/mtd/nand/raw/nand_base.c:	chip->legacy.cmdfunc(chip, NAND_CMD_SEQIN, offset_in_page, page);
+drivers/mtd/nand/raw/nand_base.c:		chip->legacy.write_buf(chip, buf, len);
+drivers/mtd/nand/raw/nand_base.c:			nand_get_sdr_timings(&chip->data_interface);
+drivers/mtd/nand/raw/nand_base.c:		struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
+drivers/mtd/nand/raw/nand_base.c:		chip->legacy.cmdfunc(chip, NAND_CMD_PAGEPROG, -1, -1);
+drivers/mtd/nand/raw/nand_base.c:		ret = chip->legacy.waitfunc(chip);
+drivers/mtd/nand/raw/nand_base.c:		chip->legacy.cmdfunc(chip, NAND_CMD_SEQIN, offset_in_page,
+drivers/mtd/nand/raw/nand_base.c:		chip->legacy.write_buf(chip, buf, len);
+drivers/mtd/nand/raw/nand_base.c:		chip->legacy.cmdfunc(chip, NAND_CMD_PAGEPROG, -1, -1);
+drivers/mtd/nand/raw/nand_base.c:		status = chip->legacy.waitfunc(chip);
+drivers/mtd/nand/raw/nand_base.c:			nand_get_sdr_timings(&chip->data_interface);
+drivers/mtd/nand/raw/nand_base.c:		struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
+drivers/mtd/nand/raw/nand_base.c:	chip->legacy.cmdfunc(chip, NAND_CMD_RNDIN, offset_in_page, -1);
+drivers/mtd/nand/raw/nand_base.c:		chip->legacy.write_buf(chip, buf, len);
+drivers/mtd/nand/raw/nand_base.c:			nand_get_sdr_timings(&chip->data_interface);
+drivers/mtd/nand/raw/nand_base.c:		struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
+drivers/mtd/nand/raw/nand_base.c:	chip->legacy.cmdfunc(chip, NAND_CMD_READID, addr, -1);
+drivers/mtd/nand/raw/nand_base.c:		id[i] = chip->legacy.read_byte(chip);
+drivers/mtd/nand/raw/nand_base.c:			nand_get_sdr_timings(&chip->data_interface);
+drivers/mtd/nand/raw/nand_base.c:		struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
+drivers/mtd/nand/raw/nand_base.c:	chip->legacy.cmdfunc(chip, NAND_CMD_STATUS, -1, -1);
+drivers/mtd/nand/raw/nand_base.c:		*status = chip->legacy.read_byte(chip);
+drivers/mtd/nand/raw/nand_base.c:		struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
+drivers/mtd/nand/raw/nand_base.c:	chip->legacy.cmdfunc(chip, NAND_CMD_READ0, -1, -1);
+drivers/mtd/nand/raw/nand_base.c:			    (chip->phys_erase_shift - chip->page_shift);
+drivers/mtd/nand/raw/nand_base.c:			nand_get_sdr_timings(&chip->data_interface);
+drivers/mtd/nand/raw/nand_base.c:		struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
+drivers/mtd/nand/raw/nand_base.c:		if (chip->options & NAND_ROW_ADDR_3)
+drivers/mtd/nand/raw/nand_base.c:		chip->legacy.cmdfunc(chip, NAND_CMD_ERASE1, -1, page);
+drivers/mtd/nand/raw/nand_base.c:		chip->legacy.cmdfunc(chip, NAND_CMD_ERASE2, -1, -1);
+drivers/mtd/nand/raw/nand_base.c:		ret = chip->legacy.waitfunc(chip);
+drivers/mtd/nand/raw/nand_base.c:			nand_get_sdr_timings(&chip->data_interface);
+drivers/mtd/nand/raw/nand_base.c:		struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
+drivers/mtd/nand/raw/nand_base.c:	chip->legacy.cmdfunc(chip, NAND_CMD_SET_FEATURES, feature, -1);
+drivers/mtd/nand/raw/nand_base.c:		chip->legacy.write_byte(chip, params[i]);
+drivers/mtd/nand/raw/nand_base.c:	ret = chip->legacy.waitfunc(chip);
+drivers/mtd/nand/raw/nand_base.c:			nand_get_sdr_timings(&chip->data_interface);
+drivers/mtd/nand/raw/nand_base.c:		struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
+drivers/mtd/nand/raw/nand_base.c:	chip->legacy.cmdfunc(chip, NAND_CMD_GET_FEATURES, feature, -1);
+drivers/mtd/nand/raw/nand_base.c:		params[i] = chip->legacy.read_byte(chip);
+drivers/mtd/nand/raw/nand_base.c:		struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
+drivers/mtd/nand/raw/nand_base.c:	if (!chip->legacy.dev_ready)
+drivers/mtd/nand/raw/nand_base.c:		udelay(chip->legacy.chip_delay);
+drivers/mtd/nand/raw/nand_base.c:			nand_get_sdr_timings(&chip->data_interface);
+drivers/mtd/nand/raw/nand_base.c:		struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
+drivers/mtd/nand/raw/nand_base.c:	chip->legacy.cmdfunc(chip, NAND_CMD_RESET, -1, -1);
+drivers/mtd/nand/raw/nand_base.c:		struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
+drivers/mtd/nand/raw/nand_base.c:			p[i] = chip->legacy.read_byte(chip);
+drivers/mtd/nand/raw/nand_base.c:		chip->legacy.read_buf(chip, buf, len);
+drivers/mtd/nand/raw/nand_base.c:		struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
+drivers/mtd/nand/raw/nand_base.c:			chip->legacy.write_byte(chip, p[i]);
+drivers/mtd/nand/raw/nand_base.c:		chip->legacy.write_buf(chip, buf, len);
+drivers/mtd/nand/raw/nand_base.c:	struct nand_data_interface saved_data_intf = chip->data_interface;
+drivers/mtd/nand/raw/nand_base.c:	if (!chip->onfi_timing_mode_default)
+drivers/mtd/nand/raw/nand_base.c:	chip->data_interface = saved_data_intf;
+drivers/mtd/nand/raw/nand_base.c:	if (chip->legacy.get_features)
+drivers/mtd/nand/raw/nand_base.c:		return chip->legacy.get_features(chip, addr, subfeature_param);
+drivers/mtd/nand/raw/nand_base.c:	if (chip->legacy.set_features)
+drivers/mtd/nand/raw/nand_base.c:		return chip->legacy.set_features(chip, addr, subfeature_param);
+drivers/mtd/nand/raw/nand_base.c: * @oob_required: caller requires OOB data read to chip->oob_poi
+drivers/mtd/nand/raw/nand_base.c: * @oob_required: caller requires OOB data read to chip->oob_poi
+drivers/mtd/nand/raw/nand_base.c:		ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize,
+drivers/mtd/nand/raw/nand_base.c: * @oob_required: caller requires OOB data read to chip->oob_poi
+drivers/mtd/nand/raw/nand_base.c:	int eccsize = chip->ecc.size;
+drivers/mtd/nand/raw/nand_base.c:	int eccbytes = chip->ecc.bytes;
+drivers/mtd/nand/raw/nand_base.c:	uint8_t *oob = chip->oob_poi;
+drivers/mtd/nand/raw/nand_base.c:	for (steps = chip->ecc.steps; steps > 0; steps--) {
+drivers/mtd/nand/raw/nand_base.c:		if (chip->ecc.prepad) {
+drivers/mtd/nand/raw/nand_base.c:			ret = nand_read_data_op(chip, oob, chip->ecc.prepad,
+drivers/mtd/nand/raw/nand_base.c:			oob += chip->ecc.prepad;
+drivers/mtd/nand/raw/nand_base.c:		if (chip->ecc.postpad) {
+drivers/mtd/nand/raw/nand_base.c:			ret = nand_read_data_op(chip, oob, chip->ecc.postpad,
+drivers/mtd/nand/raw/nand_base.c:			oob += chip->ecc.postpad;
+drivers/mtd/nand/raw/nand_base.c:	size = mtd->oobsize - (oob - chip->oob_poi);
+drivers/mtd/nand/raw/nand_base.c: * @oob_required: caller requires OOB data read to chip->oob_poi
+drivers/mtd/nand/raw/nand_base.c:	int i, eccsize = chip->ecc.size, ret;
+drivers/mtd/nand/raw/nand_base.c:	int eccbytes = chip->ecc.bytes;
+drivers/mtd/nand/raw/nand_base.c:	int eccsteps = chip->ecc.steps;
+drivers/mtd/nand/raw/nand_base.c:	uint8_t *ecc_calc = chip->ecc.calc_buf;
+drivers/mtd/nand/raw/nand_base.c:	uint8_t *ecc_code = chip->ecc.code_buf;
+drivers/mtd/nand/raw/nand_base.c:	chip->ecc.read_page_raw(chip, buf, 1, page);
+drivers/mtd/nand/raw/nand_base.c:		chip->ecc.calculate(chip, p, &ecc_calc[i]);
+drivers/mtd/nand/raw/nand_base.c:	ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
+drivers/mtd/nand/raw/nand_base.c:					 chip->ecc.total);
+drivers/mtd/nand/raw/nand_base.c:	eccsteps = chip->ecc.steps;
+drivers/mtd/nand/raw/nand_base.c:		stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]);
+drivers/mtd/nand/raw/nand_base.c:	int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
+drivers/mtd/nand/raw/nand_base.c:	start_step = data_offs / chip->ecc.size;
+drivers/mtd/nand/raw/nand_base.c:	end_step = (data_offs + readlen - 1) / chip->ecc.size;
+drivers/mtd/nand/raw/nand_base.c:	index = start_step * chip->ecc.bytes;
+drivers/mtd/nand/raw/nand_base.c:	datafrag_len = num_steps * chip->ecc.size;
+drivers/mtd/nand/raw/nand_base.c:	eccfrag_len = num_steps * chip->ecc.bytes;
+drivers/mtd/nand/raw/nand_base.c:	data_col_addr = start_step * chip->ecc.size;
+drivers/mtd/nand/raw/nand_base.c:	for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
+drivers/mtd/nand/raw/nand_base.c:		chip->ecc.calculate(chip, p, &chip->ecc.calc_buf[i]);
+drivers/mtd/nand/raw/nand_base.c:						 chip->oob_poi, mtd->oobsize,
+drivers/mtd/nand/raw/nand_base.c:		if ((oobregion.offset + (num_steps * chip->ecc.bytes)) &
+drivers/mtd/nand/raw/nand_base.c:						 &chip->oob_poi[aligned_pos],
+drivers/mtd/nand/raw/nand_base.c:	ret = mtd_ooblayout_get_eccbytes(mtd, chip->ecc.code_buf,
+drivers/mtd/nand/raw/nand_base.c:					 chip->oob_poi, index, eccfrag_len);
+drivers/mtd/nand/raw/nand_base.c:	for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
+drivers/mtd/nand/raw/nand_base.c:		stat = chip->ecc.correct(chip, p, &chip->ecc.code_buf[i],
+drivers/mtd/nand/raw/nand_base.c:					 &chip->ecc.calc_buf[i]);
+drivers/mtd/nand/raw/nand_base.c:		    (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
+drivers/mtd/nand/raw/nand_base.c:			stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
+drivers/mtd/nand/raw/nand_base.c:						&chip->ecc.code_buf[i],
+drivers/mtd/nand/raw/nand_base.c:						chip->ecc.bytes,
+drivers/mtd/nand/raw/nand_base.c:						chip->ecc.strength);
+drivers/mtd/nand/raw/nand_base.c: * @oob_required: caller requires OOB data read to chip->oob_poi
+drivers/mtd/nand/raw/nand_base.c:	int i, eccsize = chip->ecc.size, ret;
+drivers/mtd/nand/raw/nand_base.c:	int eccbytes = chip->ecc.bytes;
+drivers/mtd/nand/raw/nand_base.c:	int eccsteps = chip->ecc.steps;
+drivers/mtd/nand/raw/nand_base.c:	uint8_t *ecc_calc = chip->ecc.calc_buf;
+drivers/mtd/nand/raw/nand_base.c:	uint8_t *ecc_code = chip->ecc.code_buf;
+drivers/mtd/nand/raw/nand_base.c:		chip->ecc.hwctl(chip, NAND_ECC_READ);
+drivers/mtd/nand/raw/nand_base.c:		chip->ecc.calculate(chip, p, &ecc_calc[i]);
+drivers/mtd/nand/raw/nand_base.c:	ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize, false);
+drivers/mtd/nand/raw/nand_base.c:	ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
+drivers/mtd/nand/raw/nand_base.c:					 chip->ecc.total);
+drivers/mtd/nand/raw/nand_base.c:	eccsteps = chip->ecc.steps;
+drivers/mtd/nand/raw/nand_base.c:		stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]);
+drivers/mtd/nand/raw/nand_base.c:		    (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
+drivers/mtd/nand/raw/nand_base.c:						chip->ecc.strength);
+drivers/mtd/nand/raw/nand_base.c: * @oob_required: caller requires OOB data read to chip->oob_poi
+drivers/mtd/nand/raw/nand_base.c:	int i, eccsize = chip->ecc.size, ret;
+drivers/mtd/nand/raw/nand_base.c:	int eccbytes = chip->ecc.bytes;
+drivers/mtd/nand/raw/nand_base.c:	int eccsteps = chip->ecc.steps;
+drivers/mtd/nand/raw/nand_base.c:	uint8_t *ecc_code = chip->ecc.code_buf;
+drivers/mtd/nand/raw/nand_base.c:	uint8_t *ecc_calc = chip->ecc.calc_buf;
+drivers/mtd/nand/raw/nand_base.c:	ret = nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
+drivers/mtd/nand/raw/nand_base.c:	ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
+drivers/mtd/nand/raw/nand_base.c:					 chip->ecc.total);
+drivers/mtd/nand/raw/nand_base.c:		chip->ecc.hwctl(chip, NAND_ECC_READ);
+drivers/mtd/nand/raw/nand_base.c:		chip->ecc.calculate(chip, p, &ecc_calc[i]);
+drivers/mtd/nand/raw/nand_base.c:		stat = chip->ecc.correct(chip, p, &ecc_code[i], NULL);
+drivers/mtd/nand/raw/nand_base.c:		    (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
+drivers/mtd/nand/raw/nand_base.c:						chip->ecc.strength);
+drivers/mtd/nand/raw/nand_base.c: * @oob_required: caller requires OOB data read to chip->oob_poi
+drivers/mtd/nand/raw/nand_base.c:	int ret, i, eccsize = chip->ecc.size;
+drivers/mtd/nand/raw/nand_base.c:	int eccbytes = chip->ecc.bytes;
+drivers/mtd/nand/raw/nand_base.c:	int eccsteps = chip->ecc.steps;
+drivers/mtd/nand/raw/nand_base.c:	int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
+drivers/mtd/nand/raw/nand_base.c:	uint8_t *oob = chip->oob_poi;
+drivers/mtd/nand/raw/nand_base.c:		chip->ecc.hwctl(chip, NAND_ECC_READ);
+drivers/mtd/nand/raw/nand_base.c:		if (chip->ecc.prepad) {
+drivers/mtd/nand/raw/nand_base.c:			ret = nand_read_data_op(chip, oob, chip->ecc.prepad,
+drivers/mtd/nand/raw/nand_base.c:			oob += chip->ecc.prepad;
+drivers/mtd/nand/raw/nand_base.c:		chip->ecc.hwctl(chip, NAND_ECC_READSYN);
+drivers/mtd/nand/raw/nand_base.c:		stat = chip->ecc.correct(chip, p, oob, NULL);
+drivers/mtd/nand/raw/nand_base.c:		if (chip->ecc.postpad) {
+drivers/mtd/nand/raw/nand_base.c:			ret = nand_read_data_op(chip, oob, chip->ecc.postpad,
+drivers/mtd/nand/raw/nand_base.c:			oob += chip->ecc.postpad;
+drivers/mtd/nand/raw/nand_base.c:		    (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
+drivers/mtd/nand/raw/nand_base.c:			stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
+drivers/mtd/nand/raw/nand_base.c:							   chip->ecc.strength);
+drivers/mtd/nand/raw/nand_base.c:	i = mtd->oobsize - (oob - chip->oob_poi);
+drivers/mtd/nand/raw/nand_base.c:		memcpy(oob, chip->oob_poi + ops->ooboffs, len);
+drivers/mtd/nand/raw/nand_base.c:		ret = mtd_ooblayout_get_databytes(mtd, oob, chip->oob_poi,
+drivers/mtd/nand/raw/nand_base.c:	if (retry_mode >= chip->read_retries)
+drivers/mtd/nand/raw/nand_base.c:	if (!chip->setup_read_retry)
+drivers/mtd/nand/raw/nand_base.c:	return chip->setup_read_retry(chip, retry_mode);
+drivers/mtd/nand/raw/nand_base.c:	if (!(chip->options & NAND_NEED_READRDY))
+drivers/mtd/nand/raw/nand_base.c:	sdr = nand_get_sdr_timings(&chip->data_interface);
+drivers/mtd/nand/raw/nand_base.c:	chipnr = (int)(from >> chip->chip_shift);
+drivers/mtd/nand/raw/nand_base.c:	realpage = (int)(from >> chip->page_shift);
+drivers/mtd/nand/raw/nand_base.c:	page = realpage & chip->pagemask;
+drivers/mtd/nand/raw/nand_base.c:		else if (chip->options & NAND_USE_BOUNCE_BUFFER)
+drivers/mtd/nand/raw/nand_base.c:						 chip->buf_align);
+drivers/mtd/nand/raw/nand_base.c:		if (realpage != chip->pagecache.page || oob) {
+drivers/mtd/nand/raw/nand_base.c:			bufpoi = use_bufpoi ? chip->data_buf : buf;
+drivers/mtd/nand/raw/nand_base.c:				ret = chip->ecc.read_page_raw(chip, bufpoi,
+drivers/mtd/nand/raw/nand_base.c:				ret = chip->ecc.read_subpage(chip, col, bytes,
+drivers/mtd/nand/raw/nand_base.c:				ret = chip->ecc.read_page(chip, bufpoi,
+drivers/mtd/nand/raw/nand_base.c:					chip->pagecache.page = -1;
+drivers/mtd/nand/raw/nand_base.c:					chip->pagecache.page = realpage;
+drivers/mtd/nand/raw/nand_base.c:					chip->pagecache.bitflips = ret;
+drivers/mtd/nand/raw/nand_base.c:					chip->pagecache.page = -1;
+drivers/mtd/nand/raw/nand_base.c:				memcpy(buf, chip->data_buf + col, bytes);
+drivers/mtd/nand/raw/nand_base.c:				if (retry_mode + 1 < chip->read_retries) {
+drivers/mtd/nand/raw/nand_base.c:			memcpy(buf, chip->data_buf + col, bytes);
+drivers/mtd/nand/raw/nand_base.c:					     chip->pagecache.bitflips);
+drivers/mtd/nand/raw/nand_base.c:		page = realpage & chip->pagemask;
+drivers/mtd/nand/raw/nand_base.c:	return nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
+drivers/mtd/nand/raw/nand_base.c:	int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
+drivers/mtd/nand/raw/nand_base.c:	int eccsize = chip->ecc.size;
+drivers/mtd/nand/raw/nand_base.c:	uint8_t *bufpoi = chip->oob_poi;
+drivers/mtd/nand/raw/nand_base.c:	ret = nand_read_page_op(chip, page, chip->ecc.size, NULL, 0);
+drivers/mtd/nand/raw/nand_base.c:	for (i = 0; i < chip->ecc.steps; i++) {
+drivers/mtd/nand/raw/nand_base.c:	return nand_prog_page_op(chip, page, mtd->writesize, chip->oob_poi,
+drivers/mtd/nand/raw/nand_base.c:	int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
+drivers/mtd/nand/raw/nand_base.c:	int eccsize = chip->ecc.size, length = mtd->oobsize;
+drivers/mtd/nand/raw/nand_base.c:	int ret, i, len, pos, sndcmd = 0, steps = chip->ecc.steps;
+drivers/mtd/nand/raw/nand_base.c:	const uint8_t *bufpoi = chip->oob_poi;
+drivers/mtd/nand/raw/nand_base.c:	if (!chip->ecc.prepad && !chip->ecc.postpad) {
+drivers/mtd/nand/raw/nand_base.c:	chipnr = (int)(from >> chip->chip_shift);
+drivers/mtd/nand/raw/nand_base.c:	realpage = (int)(from >> chip->page_shift);
+drivers/mtd/nand/raw/nand_base.c:	page = realpage & chip->pagemask;
+drivers/mtd/nand/raw/nand_base.c:			ret = chip->ecc.read_oob_raw(chip, page);
+drivers/mtd/nand/raw/nand_base.c:			ret = chip->ecc.read_oob(chip, page);
+drivers/mtd/nand/raw/nand_base.c:		page = realpage & chip->pagemask;
+drivers/mtd/nand/raw/nand_base.c: * @oob_required: must write chip->oob_poi to OOB
+drivers/mtd/nand/raw/nand_base.c: * @oob_required: must write chip->oob_poi to OOB
+drivers/mtd/nand/raw/nand_base.c:		ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize,
+drivers/mtd/nand/raw/nand_base.c: * @oob_required: must write chip->oob_poi to OOB
+drivers/mtd/nand/raw/nand_base.c:	int eccsize = chip->ecc.size;
+drivers/mtd/nand/raw/nand_base.c:	int eccbytes = chip->ecc.bytes;
+drivers/mtd/nand/raw/nand_base.c:	uint8_t *oob = chip->oob_poi;
+drivers/mtd/nand/raw/nand_base.c:	for (steps = chip->ecc.steps; steps > 0; steps--) {
+drivers/mtd/nand/raw/nand_base.c:		if (chip->ecc.prepad) {
+drivers/mtd/nand/raw/nand_base.c:			ret = nand_write_data_op(chip, oob, chip->ecc.prepad,
+drivers/mtd/nand/raw/nand_base.c:			oob += chip->ecc.prepad;
+drivers/mtd/nand/raw/nand_base.c:		if (chip->ecc.postpad) {
+drivers/mtd/nand/raw/nand_base.c:			ret = nand_write_data_op(chip, oob, chip->ecc.postpad,
+drivers/mtd/nand/raw/nand_base.c:			oob += chip->ecc.postpad;
+drivers/mtd/nand/raw/nand_base.c:	size = mtd->oobsize - (oob - chip->oob_poi);
+drivers/mtd/nand/raw/nand_base.c: * @oob_required: must write chip->oob_poi to OOB
+drivers/mtd/nand/raw/nand_base.c:	int i, eccsize = chip->ecc.size, ret;
+drivers/mtd/nand/raw/nand_base.c:	int eccbytes = chip->ecc.bytes;
+drivers/mtd/nand/raw/nand_base.c:	int eccsteps = chip->ecc.steps;
+drivers/mtd/nand/raw/nand_base.c:	uint8_t *ecc_calc = chip->ecc.calc_buf;
+drivers/mtd/nand/raw/nand_base.c:		chip->ecc.calculate(chip, p, &ecc_calc[i]);
+drivers/mtd/nand/raw/nand_base.c:	ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,
+drivers/mtd/nand/raw/nand_base.c:					 chip->ecc.total);
+drivers/mtd/nand/raw/nand_base.c:	return chip->ecc.write_page_raw(chip, buf, 1, page);
+drivers/mtd/nand/raw/nand_base.c: * @oob_required: must write chip->oob_poi to OOB
+drivers/mtd/nand/raw/nand_base.c:	int i, eccsize = chip->ecc.size, ret;
+drivers/mtd/nand/raw/nand_base.c:	int eccbytes = chip->ecc.bytes;
+drivers/mtd/nand/raw/nand_base.c:	int eccsteps = chip->ecc.steps;
+drivers/mtd/nand/raw/nand_base.c:	uint8_t *ecc_calc = chip->ecc.calc_buf;
+drivers/mtd/nand/raw/nand_base.c:		chip->ecc.hwctl(chip, NAND_ECC_WRITE);
+drivers/mtd/nand/raw/nand_base.c:		chip->ecc.calculate(chip, p, &ecc_calc[i]);
+drivers/mtd/nand/raw/nand_base.c:	ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,
+drivers/mtd/nand/raw/nand_base.c:					 chip->ecc.total);
+drivers/mtd/nand/raw/nand_base.c:	ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false);
+drivers/mtd/nand/raw/nand_base.c: * @oob_required: must write chip->oob_poi to OOB
+drivers/mtd/nand/raw/nand_base.c:	uint8_t *oob_buf  = chip->oob_poi;
+drivers/mtd/nand/raw/nand_base.c:	uint8_t *ecc_calc = chip->ecc.calc_buf;
+drivers/mtd/nand/raw/nand_base.c:	int ecc_size      = chip->ecc.size;
+drivers/mtd/nand/raw/nand_base.c:	int ecc_bytes     = chip->ecc.bytes;
+drivers/mtd/nand/raw/nand_base.c:	int ecc_steps     = chip->ecc.steps;
+drivers/mtd/nand/raw/nand_base.c:		chip->ecc.hwctl(chip, NAND_ECC_WRITE);
+drivers/mtd/nand/raw/nand_base.c:			chip->ecc.calculate(chip, buf, ecc_calc);
+drivers/mtd/nand/raw/nand_base.c:	/* copy calculated ECC for whole page to chip->buffer->oob */
+drivers/mtd/nand/raw/nand_base.c:	ecc_calc = chip->ecc.calc_buf;
+drivers/mtd/nand/raw/nand_base.c:	ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,
+drivers/mtd/nand/raw/nand_base.c:					 chip->ecc.total);
+drivers/mtd/nand/raw/nand_base.c:	ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false);
+drivers/mtd/nand/raw/nand_base.c: * @oob_required: must write chip->oob_poi to OOB
+drivers/mtd/nand/raw/nand_base.c:	int i, eccsize = chip->ecc.size;
+drivers/mtd/nand/raw/nand_base.c:	int eccbytes = chip->ecc.bytes;
+drivers/mtd/nand/raw/nand_base.c:	int eccsteps = chip->ecc.steps;
+drivers/mtd/nand/raw/nand_base.c:	uint8_t *oob = chip->oob_poi;
+drivers/mtd/nand/raw/nand_base.c:		chip->ecc.hwctl(chip, NAND_ECC_WRITE);
+drivers/mtd/nand/raw/nand_base.c:		if (chip->ecc.prepad) {
+drivers/mtd/nand/raw/nand_base.c:			ret = nand_write_data_op(chip, oob, chip->ecc.prepad,
+drivers/mtd/nand/raw/nand_base.c:			oob += chip->ecc.prepad;
+drivers/mtd/nand/raw/nand_base.c:		chip->ecc.calculate(chip, p, oob);
+drivers/mtd/nand/raw/nand_base.c:		if (chip->ecc.postpad) {
+drivers/mtd/nand/raw/nand_base.c:			ret = nand_write_data_op(chip, oob, chip->ecc.postpad,
+drivers/mtd/nand/raw/nand_base.c:			oob += chip->ecc.postpad;
+drivers/mtd/nand/raw/nand_base.c:	i = mtd->oobsize - (oob - chip->oob_poi);
+drivers/mtd/nand/raw/nand_base.c: * @oob_required: must write chip->oob_poi to OOB
+drivers/mtd/nand/raw/nand_base.c:	if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
+drivers/mtd/nand/raw/nand_base.c:		chip->ecc.write_subpage)
+drivers/mtd/nand/raw/nand_base.c:		status = chip->ecc.write_page_raw(chip, buf, oob_required,
+drivers/mtd/nand/raw/nand_base.c:		status = chip->ecc.write_subpage(chip, offset, data_len, buf,
+drivers/mtd/nand/raw/nand_base.c:		status = chip->ecc.write_page(chip, buf, oob_required, page);
+drivers/mtd/nand/raw/nand_base.c:#define NOTALIGNED(x)	((x & (chip->subpagesize - 1)) != 0)
+drivers/mtd/nand/raw/nand_base.c:	chipnr = (int)(to >> chip->chip_shift);
+drivers/mtd/nand/raw/nand_base.c:	realpage = (int)(to >> chip->page_shift);
+drivers/mtd/nand/raw/nand_base.c:	page = realpage & chip->pagemask;
+drivers/mtd/nand/raw/nand_base.c:	if (to <= ((loff_t)chip->pagecache.page << chip->page_shift) &&
+drivers/mtd/nand/raw/nand_base.c:	    ((loff_t)chip->pagecache.page << chip->page_shift) < (to + ops->len))
+drivers/mtd/nand/raw/nand_base.c:		chip->pagecache.page = -1;
+drivers/mtd/nand/raw/nand_base.c:		else if (chip->options & NAND_USE_BOUNCE_BUFFER)
+drivers/mtd/nand/raw/nand_base.c:						 chip->buf_align);
+drivers/mtd/nand/raw/nand_base.c:			memset(chip->oob_poi, 0xff, mtd->oobsize);
+drivers/mtd/nand/raw/nand_base.c:		page = realpage & chip->pagemask;
+drivers/mtd/nand/raw/nand_base.c:	int chipnr = (int)(to >> chip->chip_shift);
+drivers/mtd/nand/raw/nand_base.c:	return chip->write_oob(chip, to, ops);
+drivers/mtd/nand/raw/nand_base.c:	return chip->erase(chip, instr, 0);
+drivers/mtd/nand/raw/nand_base.c:	page = (int)(instr->addr >> chip->page_shift);
+drivers/mtd/nand/raw/nand_base.c:	chipnr = (int)(instr->addr >> chip->chip_shift);
+drivers/mtd/nand/raw/nand_base.c:	pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
+drivers/mtd/nand/raw/nand_base.c:					chip->page_shift, allowbbt)) {
+drivers/mtd/nand/raw/nand_base.c:		if (page <= chip->pagecache.page && chip->pagecache.page <
+drivers/mtd/nand/raw/nand_base.c:			chip->pagecache.page = -1;
+drivers/mtd/nand/raw/nand_base.c:		ret = nand_erase_op(chip, (page & chip->pagemask) >>
+drivers/mtd/nand/raw/nand_base.c:				    (chip->phys_erase_shift - chip->page_shift));
+drivers/mtd/nand/raw/nand_base.c:				((loff_t)page << chip->page_shift);
+drivers/mtd/nand/raw/nand_base.c:		len -= (1ULL << chip->phys_erase_shift);
+drivers/mtd/nand/raw/nand_base.c:		if (len && !(page & chip->pagemask)) {
+drivers/mtd/nand/raw/nand_base.c:	int chipnr = (int)(offs >> chip->chip_shift);
+drivers/mtd/nand/raw/nand_base.c:	mutex_lock(&chip->lock);
+drivers/mtd/nand/raw/nand_base.c:	chip->suspended = 1;
+drivers/mtd/nand/raw/nand_base.c:	mutex_unlock(&chip->lock);
+drivers/mtd/nand/raw/nand_base.c:	mutex_lock(&chip->lock);
+drivers/mtd/nand/raw/nand_base.c:	if (chip->suspended)
+drivers/mtd/nand/raw/nand_base.c:		chip->suspended = 0;
+drivers/mtd/nand/raw/nand_base.c:	mutex_unlock(&chip->lock);
+drivers/mtd/nand/raw/nand_base.c:	if (!chip->controller) {
+drivers/mtd/nand/raw/nand_base.c:		chip->controller = &chip->legacy.dummy_controller;
+drivers/mtd/nand/raw/nand_base.c:		nand_controller_init(chip->controller);
+drivers/mtd/nand/raw/nand_base.c:	if (!chip->buf_align)
+drivers/mtd/nand/raw/nand_base.c:		chip->buf_align = 1;
+drivers/mtd/nand/raw/nand_base.c:	chip->erase = nand_erase_nand;
+drivers/mtd/nand/raw/nand_base.c:	chip->write_oob = nand_write_oob_nand;
+drivers/mtd/nand/raw/nand_base.c:	u8 *id_data = chip->id.data;
+drivers/mtd/nand/raw/nand_base.c:	memorg = nanddev_get_memorg(&chip->base);
+drivers/mtd/nand/raw/nand_base.c:		chip->options |= NAND_BUSWIDTH_16;
+drivers/mtd/nand/raw/nand_base.c:	memorg = nanddev_get_memorg(&chip->base);
+drivers/mtd/nand/raw/nand_base.c:	if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
+drivers/mtd/nand/raw/nand_base.c:		chip->badblockpos = NAND_BBM_POS_LARGE;
+drivers/mtd/nand/raw/nand_base.c:		chip->badblockpos = NAND_BBM_POS_SMALL;
+drivers/mtd/nand/raw/nand_base.c:	u8 *id_data = chip->id.data;
+drivers/mtd/nand/raw/nand_base.c:	memorg = nanddev_get_memorg(&chip->base);
+drivers/mtd/nand/raw/nand_base.c:		chip->options |= type->options;
+drivers/mtd/nand/raw/nand_base.c:		chip->base.eccreq.strength = NAND_ECC_STRENGTH(type);
+drivers/mtd/nand/raw/nand_base.c:		chip->base.eccreq.step_size = NAND_ECC_STEP(type);
+drivers/mtd/nand/raw/nand_base.c:		chip->onfi_timing_mode_default =
+drivers/mtd/nand/raw/nand_base.c:		chip->parameters.model = kstrdup(type->name, GFP_KERNEL);
+drivers/mtd/nand/raw/nand_base.c:		if (!chip->parameters.model)
+drivers/mtd/nand/raw/nand_base.c:	if (chip->manufacturer.desc && chip->manufacturer.desc->ops &&
+drivers/mtd/nand/raw/nand_base.c:	    chip->manufacturer.desc->ops->detect) {
+drivers/mtd/nand/raw/nand_base.c:		memorg = nanddev_get_memorg(&chip->base);
+drivers/mtd/nand/raw/nand_base.c:		memorg->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]);
+drivers/mtd/nand/raw/nand_base.c:		chip->manufacturer.desc->ops->detect(chip);
+drivers/mtd/nand/raw/nand_base.c:	if (!chip->manufacturer.desc || !chip->manufacturer.desc->ops ||
+drivers/mtd/nand/raw/nand_base.c:	    !chip->manufacturer.desc->ops->init)
+drivers/mtd/nand/raw/nand_base.c:	return chip->manufacturer.desc->ops->init(chip);
+drivers/mtd/nand/raw/nand_base.c:	if (chip->manufacturer.desc && chip->manufacturer.desc->ops &&
+drivers/mtd/nand/raw/nand_base.c:	    chip->manufacturer.desc->ops->cleanup)
+drivers/mtd/nand/raw/nand_base.c:		chip->manufacturer.desc->ops->cleanup(chip);
+drivers/mtd/nand/raw/nand_base.c:	u8 *id_data = chip->id.data;
+drivers/mtd/nand/raw/nand_base.c:	memorg = nanddev_get_memorg(&chip->base);
+drivers/mtd/nand/raw/nand_base.c:	ret = nand_readid_op(chip, 0, id_data, sizeof(chip->id.data));
+drivers/mtd/nand/raw/nand_base.c:	chip->id.len = nand_id_len(id_data, ARRAY_SIZE(chip->id.data));
+drivers/mtd/nand/raw/nand_base.c:	chip->manufacturer.desc = manufacturer;
+drivers/mtd/nand/raw/nand_base.c:	busw = chip->options & NAND_BUSWIDTH_16;
+drivers/mtd/nand/raw/nand_base.c:	chip->options &= ~NAND_BUSWIDTH_16;
+drivers/mtd/nand/raw/nand_base.c:	chip->parameters.model = kstrdup(type->name, GFP_KERNEL);
+drivers/mtd/nand/raw/nand_base.c:	if (!chip->parameters.model)
+drivers/mtd/nand/raw/nand_base.c:	chip->options |= type->options;
+drivers/mtd/nand/raw/nand_base.c:		mtd->name = chip->parameters.model;
+drivers/mtd/nand/raw/nand_base.c:	if (chip->options & NAND_BUSWIDTH_AUTO) {
+drivers/mtd/nand/raw/nand_base.c:	} else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
+drivers/mtd/nand/raw/nand_base.c:			(chip->options & NAND_BUSWIDTH_16) ? 16 : 8);
+drivers/mtd/nand/raw/nand_base.c:	chip->page_shift = ffs(mtd->writesize) - 1;
+drivers/mtd/nand/raw/nand_base.c:	targetsize = nanddev_target_size(&chip->base);
+drivers/mtd/nand/raw/nand_base.c:	chip->pagemask = (targetsize >> chip->page_shift) - 1;
+drivers/mtd/nand/raw/nand_base.c:	chip->bbt_erase_shift = chip->phys_erase_shift =
+drivers/mtd/nand/raw/nand_base.c:		chip->chip_shift = ffs((unsigned)targetsize) - 1;
+drivers/mtd/nand/raw/nand_base.c:		chip->chip_shift = ffs((unsigned)(targetsize >> 32));
+drivers/mtd/nand/raw/nand_base.c:		chip->chip_shift += 32 - 1;
+drivers/mtd/nand/raw/nand_base.c:	if (chip->chip_shift - chip->page_shift > 16)
+drivers/mtd/nand/raw/nand_base.c:		chip->options |= NAND_ROW_ADDR_3;
+drivers/mtd/nand/raw/nand_base.c:	chip->badblockbits = 8;
+drivers/mtd/nand/raw/nand_base.c:		chip->parameters.model);
+drivers/mtd/nand/raw/nand_base.c:	kfree(chip->parameters.model);
+drivers/mtd/nand/raw/nand_base.c:		chip->options |= NAND_BUSWIDTH_16;
+drivers/mtd/nand/raw/nand_base.c:		chip->options |= NAND_IS_BOOT_MEDIUM;
+drivers/mtd/nand/raw/nand_base.c:		chip->bbt_options |= NAND_BBT_USE_FLASH;
+drivers/mtd/nand/raw/nand_base.c:		chip->ecc.mode = ecc_mode;
+drivers/mtd/nand/raw/nand_base.c:		chip->ecc.algo = ecc_algo;
+drivers/mtd/nand/raw/nand_base.c:		chip->ecc.strength = ecc_strength;
+drivers/mtd/nand/raw/nand_base.c:		chip->ecc.size = ecc_step;
+drivers/mtd/nand/raw/nand_base.c:		chip->ecc.options |= NAND_ECC_MAXIMIZE;
+drivers/mtd/nand/raw/nand_base.c:	memorg = nanddev_get_memorg(&chip->base);
+drivers/mtd/nand/raw/nand_base.c:	chip->cur_cs = -1;
+drivers/mtd/nand/raw/nand_base.c:	mutex_init(&chip->lock);
+drivers/mtd/nand/raw/nand_base.c:		if (!(chip->options & NAND_SCAN_SILENT_NODEV))
+drivers/mtd/nand/raw/nand_base.c:	nand_maf_id = chip->id.data[0];
+drivers/mtd/nand/raw/nand_base.c:	nand_dev_id = chip->id.data[1];
+drivers/mtd/nand/raw/nand_base.c:	mtd->size = i * nanddev_target_size(&chip->base);
+drivers/mtd/nand/raw/nand_base.c:	kfree(chip->parameters.model);
+drivers/mtd/nand/raw/nand_base.c:	kfree(chip->parameters.onfi);
+drivers/mtd/nand/raw/nand_base.c:	struct nand_ecc_ctrl *ecc = &chip->ecc;
+drivers/mtd/nand/raw/nand_base.c:	int preset_step = chip->ecc.size;
+drivers/mtd/nand/raw/nand_base.c:	int preset_strength = chip->ecc.strength;
+drivers/mtd/nand/raw/nand_base.c:			chip->ecc.bytes = ecc_bytes;
+drivers/mtd/nand/raw/nand_base.c:	int req_step = chip->base.eccreq.step_size;
+drivers/mtd/nand/raw/nand_base.c:	int req_strength = chip->base.eccreq.strength;
+drivers/mtd/nand/raw/nand_base.c:	chip->ecc.size = best_step;
+drivers/mtd/nand/raw/nand_base.c:	chip->ecc.strength = best_strength;
+drivers/mtd/nand/raw/nand_base.c:	chip->ecc.bytes = best_ecc_bytes;
+drivers/mtd/nand/raw/nand_base.c:		/* If chip->ecc.size is already set, respect it */
+drivers/mtd/nand/raw/nand_base.c:		if (chip->ecc.size && step_size != chip->ecc.size)
+drivers/mtd/nand/raw/nand_base.c:	chip->ecc.size = best_step;
+drivers/mtd/nand/raw/nand_base.c:	chip->ecc.strength = best_strength;
+drivers/mtd/nand/raw/nand_base.c:	chip->ecc.bytes = best_ecc_bytes;
+drivers/mtd/nand/raw/nand_base.c:	if (chip->ecc.size && chip->ecc.strength)
+drivers/mtd/nand/raw/nand_base.c:	if (chip->ecc.options & NAND_ECC_MAXIMIZE)
+drivers/mtd/nand/raw/nand_base.c:	struct nand_ecc_ctrl *ecc = &chip->ecc;
+drivers/mtd/nand/raw/nand_base.c:	if (ecc->size == 0 || chip->base.eccreq.step_size == 0)
+drivers/mtd/nand/raw/nand_base.c:	ds_corr = (mtd->writesize * chip->base.eccreq.strength) /
+drivers/mtd/nand/raw/nand_base.c:		  chip->base.eccreq.step_size;
+drivers/mtd/nand/raw/nand_base.c:	return corr >= ds_corr && ecc->strength >= chip->base.eccreq.strength;
+drivers/mtd/nand/raw/nand_base.c:	struct nand_ecc_ctrl *ecc = &chip->ecc;
+drivers/mtd/nand/raw/nand_base.c:	if (WARN_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
+drivers/mtd/nand/raw/nand_base.c:		   !(chip->bbt_options & NAND_BBT_USE_FLASH))) {
+drivers/mtd/nand/raw/nand_base.c:	chip->data_buf = kmalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL);
+drivers/mtd/nand/raw/nand_base.c:	if (!chip->data_buf)
+drivers/mtd/nand/raw/nand_base.c:	chip->oob_poi = chip->data_buf + mtd->writesize;
+drivers/mtd/nand/raw/nand_base.c:	if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
+drivers/mtd/nand/raw/nand_base.c:	chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
+drivers/mtd/nand/raw/nand_base.c:	chip->pagecache.page = -1;
+drivers/mtd/nand/raw/nand_base.c:		if (chip->page_shift > 9)
+drivers/mtd/nand/raw/nand_base.c:			chip->options |= NAND_SUBPAGE_READ;
+drivers/mtd/nand/raw/nand_base.c:	ret = nanddev_init(&chip->base, &rawnand_ops, mtd->owner);
+drivers/mtd/nand/raw/nand_base.c:	if (chip->options & NAND_ROM)
+drivers/mtd/nand/raw/nand_base.c:	for (i = 0; i < nanddev_ntargets(&chip->base); i++) {
+drivers/mtd/nand/raw/nand_base.c:	if (chip->options & NAND_SKIP_BBTSCAN)
+drivers/mtd/nand/raw/nand_base.c:	nanddev_cleanup(&chip->base);
+drivers/mtd/nand/raw/nand_base.c:	kfree(chip->data_buf);
+drivers/mtd/nand/raw/nand_base.c:	if (chip->controller->ops && chip->controller->ops->attach_chip)
+drivers/mtd/nand/raw/nand_base.c:		return chip->controller->ops->attach_chip(chip);
+drivers/mtd/nand/raw/nand_base.c:	if (chip->controller->ops && chip->controller->ops->detach_chip)
+drivers/mtd/nand/raw/nand_base.c:		chip->controller->ops->detach_chip(chip);
+drivers/mtd/nand/raw/nand_base.c:	if (chip->ecc.mode == NAND_ECC_SOFT &&
+drivers/mtd/nand/raw/nand_base.c:	    chip->ecc.algo == NAND_ECC_BCH)
+drivers/mtd/nand/raw/nand_base.c:		nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
+drivers/mtd/nand/raw/nand_base.c:	kfree(chip->bbt);
+drivers/mtd/nand/raw/nand_base.c:	kfree(chip->data_buf);
+drivers/mtd/nand/raw/nand_base.c:	kfree(chip->ecc.code_buf);
+drivers/mtd/nand/raw/nand_base.c:	kfree(chip->ecc.calc_buf);
+drivers/mtd/nand/raw/nand_base.c:	if (chip->badblock_pattern && chip->badblock_pattern->options
+drivers/mtd/nand/raw/nand_base.c:		kfree(chip->badblock_pattern);
+drivers/mtd/nand/raw/nand_bbt.c:	uint8_t entry = chip->bbt[block >> BBT_ENTRY_SHIFT];
+drivers/mtd/nand/raw/nand_bbt.c:	chip->bbt[block >> BBT_ENTRY_SHIFT] |= msk;
+drivers/mtd/nand/raw/nand_bch.c:	struct nand_bch_control *nbc = chip->ecc.priv;
+drivers/mtd/nand/raw/nand_bch.c:	memset(code, 0, chip->ecc.bytes);
+drivers/mtd/nand/raw/nand_bch.c:	encode_bch(nbc->bch, buf, chip->ecc.size, code);
+drivers/mtd/nand/raw/nand_bch.c:	for (i = 0; i < chip->ecc.bytes; i++)
+drivers/mtd/nand/raw/nand_bch.c:	struct nand_bch_control *nbc = chip->ecc.priv;
+drivers/mtd/nand/raw/nand_bch.c:	count = decode_bch(nbc->bch, NULL, chip->ecc.size, read_ecc, calc_ecc,
+drivers/mtd/nand/raw/nand_bch.c:			if (errloc[i] < (chip->ecc.size*8))
+drivers/mtd/nand/raw/nand_ecc.c:	bool sm_order = chip->ecc.options & NAND_ECC_SOFT_HAMMING_SM_ORDER;
+drivers/mtd/nand/raw/nand_ecc.c:	__nand_calculate_ecc(buf, chip->ecc.size, code, sm_order);
+drivers/mtd/nand/raw/nand_ecc.c:	bool sm_order = chip->ecc.options & NAND_ECC_SOFT_HAMMING_SM_ORDER;
+drivers/mtd/nand/raw/nand_ecc.c:	return __nand_correct_data(buf, read_ecc, calc_ecc, chip->ecc.size,
+drivers/mtd/nand/raw/nand_esmt.c:	if (chip->id.len >= 5 && nand_is_slc(chip)) {
+drivers/mtd/nand/raw/nand_esmt.c:		chip->base.eccreq.step_size = 512;
+drivers/mtd/nand/raw/nand_esmt.c:		switch (chip->id.data[4] & 0x3) {
+drivers/mtd/nand/raw/nand_esmt.c:			chip->base.eccreq.strength = 4;
+drivers/mtd/nand/raw/nand_esmt.c:			chip->base.eccreq.strength = 2;
+drivers/mtd/nand/raw/nand_esmt.c:			chip->base.eccreq.strength = 1;
+drivers/mtd/nand/raw/nand_esmt.c:			chip->base.eccreq.step_size = 0;
+drivers/mtd/nand/raw/nand_esmt.c:		chip->options |= NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE |
+drivers/mtd/nand/raw/nand_hynix.c:		struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
+drivers/mtd/nand/raw/nand_hynix.c:	chip->legacy.cmdfunc(chip, cmd, -1, -1);
+drivers/mtd/nand/raw/nand_hynix.c:		struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
+drivers/mtd/nand/raw/nand_hynix.c:	chip->legacy.cmdfunc(chip, NAND_CMD_NONE, column, -1);
+drivers/mtd/nand/raw/nand_hynix.c:	chip->legacy.write_byte(chip, val);
+drivers/mtd/nand/raw/nand_hynix.c:	chip->setup_read_retry = hynix_nand_setup_read_retry;
+drivers/mtd/nand/raw/nand_hynix.c:	chip->read_retries = nmodes;
+drivers/mtd/nand/raw/nand_hynix.c:		u8 nand_tech = chip->id.data[5] >> 4;
+drivers/mtd/nand/raw/nand_hynix.c:	memorg = nanddev_get_memorg(&chip->base);
+drivers/mtd/nand/raw/nand_hynix.c:	oobsize = ((chip->id.data[3] >> 2) & 0x3) |
+drivers/mtd/nand/raw/nand_hynix.c:		  ((chip->id.data[3] >> 4) & 0x4);
+drivers/mtd/nand/raw/nand_hynix.c:		if (chip->id.data[1] == 0xde)
+drivers/mtd/nand/raw/nand_hynix.c:	u8 ecc_level = (chip->id.data[4] >> 4) & 0x7;
+drivers/mtd/nand/raw/nand_hynix.c:		chip->base.eccreq.step_size = 1024;
+drivers/mtd/nand/raw/nand_hynix.c:			chip->base.eccreq.step_size = 0;
+drivers/mtd/nand/raw/nand_hynix.c:			chip->base.eccreq.strength = 0;
+drivers/mtd/nand/raw/nand_hynix.c:			chip->base.eccreq.strength = 4;
+drivers/mtd/nand/raw/nand_hynix.c:			chip->base.eccreq.strength = 24;
+drivers/mtd/nand/raw/nand_hynix.c:			chip->base.eccreq.strength = 32;
+drivers/mtd/nand/raw/nand_hynix.c:			chip->base.eccreq.strength = 40;
+drivers/mtd/nand/raw/nand_hynix.c:			chip->base.eccreq.strength = 50;
+drivers/mtd/nand/raw/nand_hynix.c:			chip->base.eccreq.strength = 60;
+drivers/mtd/nand/raw/nand_hynix.c:		u8 nand_tech = chip->id.data[5] & 0x7;
+drivers/mtd/nand/raw/nand_hynix.c:				chip->base.eccreq.step_size = 512;
+drivers/mtd/nand/raw/nand_hynix.c:				chip->base.eccreq.strength = 1 << ecc_level;
+drivers/mtd/nand/raw/nand_hynix.c:					chip->base.eccreq.step_size = 2048;
+drivers/mtd/nand/raw/nand_hynix.c:					chip->base.eccreq.step_size = 1024;
+drivers/mtd/nand/raw/nand_hynix.c:				chip->base.eccreq.strength = 24;
+drivers/mtd/nand/raw/nand_hynix.c:				chip->base.eccreq.step_size = 0;
+drivers/mtd/nand/raw/nand_hynix.c:				chip->base.eccreq.strength = 0;
+drivers/mtd/nand/raw/nand_hynix.c:				chip->base.eccreq.step_size = 512;
+drivers/mtd/nand/raw/nand_hynix.c:				chip->base.eccreq.strength = 1 << (ecc_level - 1);
+drivers/mtd/nand/raw/nand_hynix.c:				chip->base.eccreq.step_size = 1024;
+drivers/mtd/nand/raw/nand_hynix.c:				chip->base.eccreq.strength = 24 +
+drivers/mtd/nand/raw/nand_hynix.c:	if (nanddev_bits_per_cell(&chip->base) > 2)
+drivers/mtd/nand/raw/nand_hynix.c:		chip->options |= NAND_NEED_SCRAMBLING;
+drivers/mtd/nand/raw/nand_hynix.c:		nand_tech = chip->id.data[5] >> 4;
+drivers/mtd/nand/raw/nand_hynix.c:			chip->options |= NAND_NEED_SCRAMBLING;
+drivers/mtd/nand/raw/nand_hynix.c:		nand_tech = chip->id.data[5] & 0x7;
+drivers/mtd/nand/raw/nand_hynix.c:			chip->options |= NAND_NEED_SCRAMBLING;
+drivers/mtd/nand/raw/nand_hynix.c:	memorg = nanddev_get_memorg(&chip->base);
+drivers/mtd/nand/raw/nand_hynix.c:	if (chip->id.len < 6 || nand_is_slc(chip)) {
+drivers/mtd/nand/raw/nand_hynix.c:	memorg->pagesize = 2048 << (chip->id.data[3] & 0x03);
+drivers/mtd/nand/raw/nand_hynix.c:	tmp = (chip->id.data[3] >> 4) & 0x3;
+drivers/mtd/nand/raw/nand_hynix.c:	if (chip->id.data[3] & 0x80) {
+drivers/mtd/nand/raw/nand_hynix.c:		chip->options |= NAND_BBM_LASTPAGE;
+drivers/mtd/nand/raw/nand_hynix.c:		chip->options |= NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE;
+drivers/mtd/nand/raw/nand_jedec.c:	memorg = nanddev_get_memorg(&chip->base);
+drivers/mtd/nand/raw/nand_jedec.c:	chip->parameters.model = kstrdup(p->model, GFP_KERNEL);
+drivers/mtd/nand/raw/nand_jedec.c:	if (!chip->parameters.model) {
+drivers/mtd/nand/raw/nand_jedec.c:		chip->options |= NAND_BUSWIDTH_16;
+drivers/mtd/nand/raw/nand_jedec.c:		chip->base.eccreq.strength = ecc->ecc_bits;
+drivers/mtd/nand/raw/nand_jedec.c:		chip->base.eccreq.step_size = 1 << ecc->codeword_size;
+drivers/mtd/nand/raw/nand_legacy.c:	return readb(chip->legacy.IO_ADDR_R);
+drivers/mtd/nand/raw/nand_legacy.c:	return (uint8_t) cpu_to_le16(readw(chip->legacy.IO_ADDR_R));
+drivers/mtd/nand/raw/nand_legacy.c:		chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
+drivers/mtd/nand/raw/nand_legacy.c:	chip->legacy.write_buf(chip, &byte, 1);
+drivers/mtd/nand/raw/nand_legacy.c:	chip->legacy.write_buf(chip, (uint8_t *)&word, 2);
+drivers/mtd/nand/raw/nand_legacy.c:	iowrite8_rep(chip->legacy.IO_ADDR_W, buf, len);
+drivers/mtd/nand/raw/nand_legacy.c:	ioread8_rep(chip->legacy.IO_ADDR_R, buf, len);
+drivers/mtd/nand/raw/nand_legacy.c:	iowrite16_rep(chip->legacy.IO_ADDR_W, p, len >> 1);
+drivers/mtd/nand/raw/nand_legacy.c:	ioread16_rep(chip->legacy.IO_ADDR_R, p, len >> 1);
+drivers/mtd/nand/raw/nand_legacy.c:		if (chip->legacy.dev_ready(chip))
+drivers/mtd/nand/raw/nand_legacy.c:		if (chip->legacy.dev_ready(chip))
+drivers/mtd/nand/raw/nand_legacy.c:	if (!chip->legacy.dev_ready(chip))
+drivers/mtd/nand/raw/nand_legacy.c:		chip->legacy.cmd_ctrl(chip, readcmd, ctrl);
+drivers/mtd/nand/raw/nand_legacy.c:		chip->legacy.cmd_ctrl(chip, command, ctrl);
+drivers/mtd/nand/raw/nand_legacy.c:		if (chip->options & NAND_BUSWIDTH_16 &&
+drivers/mtd/nand/raw/nand_legacy.c:		chip->legacy.cmd_ctrl(chip, column, ctrl);
+drivers/mtd/nand/raw/nand_legacy.c:		chip->legacy.cmd_ctrl(chip, page_addr, ctrl);
+drivers/mtd/nand/raw/nand_legacy.c:		chip->legacy.cmd_ctrl(chip, page_addr >> 8, ctrl);
+drivers/mtd/nand/raw/nand_legacy.c:		if (chip->options & NAND_ROW_ADDR_3)
+drivers/mtd/nand/raw/nand_legacy.c:			chip->legacy.cmd_ctrl(chip, page_addr >> 16, ctrl);
+drivers/mtd/nand/raw/nand_legacy.c:	chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
+drivers/mtd/nand/raw/nand_legacy.c:		if (chip->legacy.dev_ready)
+drivers/mtd/nand/raw/nand_legacy.c:		udelay(chip->legacy.chip_delay);
+drivers/mtd/nand/raw/nand_legacy.c:		chip->legacy.cmd_ctrl(chip, NAND_CMD_STATUS,
+drivers/mtd/nand/raw/nand_legacy.c:		chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
+drivers/mtd/nand/raw/nand_legacy.c:		if (!chip->legacy.dev_ready) {
+drivers/mtd/nand/raw/nand_legacy.c:			udelay(chip->legacy.chip_delay);
+drivers/mtd/nand/raw/nand_legacy.c:	if (!(chip->options & NAND_WAIT_TCCS))
+drivers/mtd/nand/raw/nand_legacy.c:		ndelay(chip->data_interface.timings.sdr.tCCS_min / 1000);
+drivers/mtd/nand/raw/nand_legacy.c:		chip->legacy.cmd_ctrl(chip, command,
+drivers/mtd/nand/raw/nand_legacy.c:			if (chip->options & NAND_BUSWIDTH_16 &&
+drivers/mtd/nand/raw/nand_legacy.c:			chip->legacy.cmd_ctrl(chip, column, ctrl);
+drivers/mtd/nand/raw/nand_legacy.c:				chip->legacy.cmd_ctrl(chip, column >> 8, ctrl);
+drivers/mtd/nand/raw/nand_legacy.c:			chip->legacy.cmd_ctrl(chip, page_addr, ctrl);
+drivers/mtd/nand/raw/nand_legacy.c:			chip->legacy.cmd_ctrl(chip, page_addr >> 8,
+drivers/mtd/nand/raw/nand_legacy.c:			if (chip->options & NAND_ROW_ADDR_3)
+drivers/mtd/nand/raw/nand_legacy.c:				chip->legacy.cmd_ctrl(chip, page_addr >> 16,
+drivers/mtd/nand/raw/nand_legacy.c:	chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
+drivers/mtd/nand/raw/nand_legacy.c:		if (chip->legacy.dev_ready)
+drivers/mtd/nand/raw/nand_legacy.c:		udelay(chip->legacy.chip_delay);
+drivers/mtd/nand/raw/nand_legacy.c:		chip->legacy.cmd_ctrl(chip, NAND_CMD_STATUS,
+drivers/mtd/nand/raw/nand_legacy.c:		chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
+drivers/mtd/nand/raw/nand_legacy.c:		chip->legacy.cmd_ctrl(chip, NAND_CMD_RNDOUTSTART,
+drivers/mtd/nand/raw/nand_legacy.c:		chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
+drivers/mtd/nand/raw/nand_legacy.c:		chip->legacy.cmd_ctrl(chip, NAND_CMD_READSTART,
+drivers/mtd/nand/raw/nand_legacy.c:		chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE,
+drivers/mtd/nand/raw/nand_legacy.c:		if (!chip->legacy.dev_ready) {
+drivers/mtd/nand/raw/nand_legacy.c:			udelay(chip->legacy.chip_delay);
+drivers/mtd/nand/raw/nand_legacy.c:			if (chip->legacy.dev_ready) {
+drivers/mtd/nand/raw/nand_legacy.c:				if (chip->legacy.dev_ready(chip))
+drivers/mtd/nand/raw/nand_legacy.c:	unsigned int busw = chip->options & NAND_BUSWIDTH_16;
+drivers/mtd/nand/raw/nand_legacy.c:	if (!chip->legacy.chip_delay)
+drivers/mtd/nand/raw/nand_legacy.c:		chip->legacy.chip_delay = 20;
+drivers/mtd/nand/raw/nand_legacy.c:	if (!chip->legacy.cmdfunc)
+drivers/mtd/nand/raw/nand_legacy.c:		chip->legacy.cmdfunc = nand_command;
+drivers/mtd/nand/raw/nand_legacy.c:	if (chip->legacy.waitfunc == NULL)
+drivers/mtd/nand/raw/nand_legacy.c:		chip->legacy.waitfunc = nand_wait;
+drivers/mtd/nand/raw/nand_legacy.c:	if (!chip->legacy.select_chip)
+drivers/mtd/nand/raw/nand_legacy.c:		chip->legacy.select_chip = nand_select_chip;
+drivers/mtd/nand/raw/nand_legacy.c:	if (!chip->legacy.read_byte || chip->legacy.read_byte == nand_read_byte)
+drivers/mtd/nand/raw/nand_legacy.c:		chip->legacy.read_byte = busw ? nand_read_byte16 : nand_read_byte;
+drivers/mtd/nand/raw/nand_legacy.c:	if (!chip->legacy.write_buf || chip->legacy.write_buf == nand_write_buf)
+drivers/mtd/nand/raw/nand_legacy.c:		chip->legacy.write_buf = busw ? nand_write_buf16 : nand_write_buf;
+drivers/mtd/nand/raw/nand_legacy.c:	if (!chip->legacy.write_byte || chip->legacy.write_byte == nand_write_byte)
+drivers/mtd/nand/raw/nand_legacy.c:		chip->legacy.write_byte = busw ? nand_write_byte16 : nand_write_byte;
+drivers/mtd/nand/raw/nand_legacy.c:	if (!chip->legacy.read_buf || chip->legacy.read_buf == nand_read_buf)
+drivers/mtd/nand/raw/nand_legacy.c:		chip->legacy.read_buf = busw ? nand_read_buf16 : nand_read_buf;
+drivers/mtd/nand/raw/nand_legacy.c:	if (mtd->writesize > 512 && chip->legacy.cmdfunc == nand_command)
+drivers/mtd/nand/raw/nand_legacy.c:		chip->legacy.cmdfunc = nand_command_lp;
+drivers/mtd/nand/raw/nand_legacy.c:	if ((!chip->legacy.cmdfunc || !chip->legacy.select_chip) &&
+drivers/mtd/nand/raw/nand_legacy.c:	    !chip->legacy.cmd_ctrl) {
+drivers/mtd/nand/raw/nand_macronix.c:	if (!chip->parameters.supports_set_get_features ||
+drivers/mtd/nand/raw/nand_macronix.c:		      chip->parameters.set_feature_list))
+drivers/mtd/nand/raw/nand_macronix.c:	struct nand_parameters *p = &chip->parameters;
+drivers/mtd/nand/raw/nand_macronix.c:	chip->read_retries = MACRONIX_NUM_READ_RETRY_MODES;
+drivers/mtd/nand/raw/nand_macronix.c:	chip->setup_read_retry = macronix_nand_setup_read_retry;
+drivers/mtd/nand/raw/nand_macronix.c:	if (!chip->parameters.supports_set_get_features)
+drivers/mtd/nand/raw/nand_macronix.c:		if (!strcmp(broken_get_timings[i], chip->parameters.model))
+drivers/mtd/nand/raw/nand_macronix.c:	bitmap_clear(chip->parameters.get_feature_list,
+drivers/mtd/nand/raw/nand_macronix.c:	bitmap_clear(chip->parameters.set_feature_list,
+drivers/mtd/nand/raw/nand_macronix.c:		chip->options |= NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE;
+drivers/mtd/nand/raw/nand_micron.c:	struct nand_parameters *p = &chip->parameters;
+drivers/mtd/nand/raw/nand_micron.c:		chip->read_retries = micron->read_retry_options;
+drivers/mtd/nand/raw/nand_micron.c:		chip->setup_read_retry = micron_nand_setup_read_retry;
+drivers/mtd/nand/raw/nand_micron.c:	oobregion->offset = mtd->oobsize - chip->ecc.total;
+drivers/mtd/nand/raw/nand_micron.c:	oobregion->length = chip->ecc.total;
+drivers/mtd/nand/raw/nand_micron.c:	oobregion->length = mtd->oobsize - chip->ecc.total - 2;
+drivers/mtd/nand/raw/nand_micron.c:		ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize,
+drivers/mtd/nand/raw/nand_micron.c:	for (step = 0; step < chip->ecc.steps; step++) {
+drivers/mtd/nand/raw/nand_micron.c:		offs = step * chip->ecc.size;
+drivers/mtd/nand/raw/nand_micron.c:		for (i = 0; i < chip->ecc.size; i++)
+drivers/mtd/nand/raw/nand_micron.c:		corrbuf = chip->oob_poi + offs;
+drivers/mtd/nand/raw/nand_micron.c:		for (i = 0; i < chip->ecc.bytes + 4; i++)
+drivers/mtd/nand/raw/nand_micron.c:		if (WARN_ON(nbitflips > chip->ecc.strength))
+drivers/mtd/nand/raw/nand_micron.c:		ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize,
+drivers/mtd/nand/raw/nand_micron.c:	if (chip->ecc.strength == 4)
+drivers/mtd/nand/raw/nand_micron.c:	if (!chip->parameters.onfi)
+drivers/mtd/nand/raw/nand_micron.c:	if (nanddev_bits_per_cell(&chip->base) != 1)
+drivers/mtd/nand/raw/nand_micron.c:	if  (chip->base.eccreq.strength != 4 && chip->base.eccreq.strength != 8)
+drivers/mtd/nand/raw/nand_micron.c:	if (chip->id.len != 5 ||
+drivers/mtd/nand/raw/nand_micron.c:	    (chip->id.data[4] & MICRON_ID_INTERNAL_ECC_MASK) != 0x2)
+drivers/mtd/nand/raw/nand_micron.c:	if  (chip->base.eccreq.strength != 4 && chip->base.eccreq.strength != 8)
+drivers/mtd/nand/raw/nand_micron.c:	unsigned int page = eb * nanddev_page_per_eraseblock(&chip->base);
+drivers/mtd/nand/raw/nand_micron.c:					      nanddev_page_size(&chip->base)
+drivers/mtd/nand/raw/nand_micron.c:					      chip->data_buf, page,
+drivers/mtd/nand/raw/nand_micron.c:	unsigned int eb_sz = nanddev_eraseblock_size(&chip->base);
+drivers/mtd/nand/raw/nand_micron.c:	unsigned int eb_sz = nanddev_eraseblock_size(&chip->base);
+drivers/mtd/nand/raw/nand_micron.c:	unsigned int p_sz = nanddev_page_size(&chip->base);
+drivers/mtd/nand/raw/nand_micron.c:	unsigned int ppeb = nanddev_pages_per_eraseblock(&chip->base);
+drivers/mtd/nand/raw/nand_micron.c:	chip->options |= NAND_BBM_FIRSTPAGE;
+drivers/mtd/nand/raw/nand_micron.c:		chip->options |= NAND_BBM_SECONDPAGE;
+drivers/mtd/nand/raw/nand_micron.c:	    chip->ecc.mode != NAND_ECC_ON_DIE) {
+drivers/mtd/nand/raw/nand_micron.c:	if (chip->ecc.mode == NAND_ECC_ON_DIE) {
+drivers/mtd/nand/raw/nand_micron.c:		if (chip->base.eccreq.strength == 4) {
+drivers/mtd/nand/raw/nand_micron.c:		if (chip->base.eccreq.strength == 4)
+drivers/mtd/nand/raw/nand_micron.c:		chip->ecc.bytes = chip->base.eccreq.strength * 2;
+drivers/mtd/nand/raw/nand_micron.c:		chip->ecc.size = 512;
+drivers/mtd/nand/raw/nand_micron.c:		chip->ecc.strength = chip->base.eccreq.strength;
+drivers/mtd/nand/raw/nand_micron.c:		chip->ecc.algo = NAND_ECC_BCH;
+drivers/mtd/nand/raw/nand_micron.c:		chip->ecc.read_page = micron_nand_read_page_on_die_ecc;
+drivers/mtd/nand/raw/nand_micron.c:		chip->ecc.write_page = micron_nand_write_page_on_die_ecc;
+drivers/mtd/nand/raw/nand_micron.c:			chip->ecc.read_page_raw = nand_read_page_raw_notsupp;
+drivers/mtd/nand/raw/nand_micron.c:			chip->ecc.write_page_raw = nand_write_page_raw_notsupp;
+drivers/mtd/nand/raw/nand_micron.c:			chip->ecc.read_page_raw = nand_read_page_raw;
+drivers/mtd/nand/raw/nand_micron.c:			chip->ecc.write_page_raw = nand_write_page_raw;
+drivers/mtd/nand/raw/nand_micron.c:					   nanddev_neraseblocks(&chip->base),
+drivers/mtd/nand/raw/nand_micron.c:		chip->erase = micron_nand_erase;
+drivers/mtd/nand/raw/nand_micron.c:		chip->write_oob = micron_nand_write_oob;
+drivers/mtd/nand/raw/nand_onfi.c:	chip->base.eccreq.strength = ecc->ecc_bits;
+drivers/mtd/nand/raw/nand_onfi.c:	chip->base.eccreq.step_size = 1 << ecc->codeword_size;
+drivers/mtd/nand/raw/nand_onfi.c:	memorg = nanddev_get_memorg(&chip->base);
+drivers/mtd/nand/raw/nand_onfi.c:	if (chip->manufacturer.desc && chip->manufacturer.desc->ops &&
+drivers/mtd/nand/raw/nand_onfi.c:	    chip->manufacturer.desc->ops->fixup_onfi_param_page)
+drivers/mtd/nand/raw/nand_onfi.c:		chip->manufacturer.desc->ops->fixup_onfi_param_page(chip, p);
+drivers/mtd/nand/raw/nand_onfi.c:	chip->parameters.model = kstrdup(p->model, GFP_KERNEL);
+drivers/mtd/nand/raw/nand_onfi.c:	if (!chip->parameters.model) {
+drivers/mtd/nand/raw/nand_onfi.c:		chip->options |= NAND_BUSWIDTH_16;
+drivers/mtd/nand/raw/nand_onfi.c:		chip->base.eccreq.strength = p->ecc_bits;
+drivers/mtd/nand/raw/nand_onfi.c:		chip->base.eccreq.step_size = 512;
+drivers/mtd/nand/raw/nand_onfi.c:		 * by the chip->legacy.cmdfunc. So try to update the
+drivers/mtd/nand/raw/nand_onfi.c:		 * chip->legacy.cmdfunc now. We do not replace user supplied
+drivers/mtd/nand/raw/nand_onfi.c:		chip->parameters.supports_set_get_features = true;
+drivers/mtd/nand/raw/nand_onfi.c:		bitmap_set(chip->parameters.get_feature_list,
+drivers/mtd/nand/raw/nand_onfi.c:		bitmap_set(chip->parameters.set_feature_list,
+drivers/mtd/nand/raw/nand_onfi.c:	chip->parameters.onfi = onfi;
+drivers/mtd/nand/raw/nand_onfi.c:	kfree(chip->parameters.model);
+drivers/mtd/nand/raw/nand_samsung.c:	memorg = nanddev_get_memorg(&chip->base);
+drivers/mtd/nand/raw/nand_samsung.c:	if (chip->id.len == 6 && !nand_is_slc(chip) &&
+drivers/mtd/nand/raw/nand_samsung.c:	    chip->id.data[5] != 0x00) {
+drivers/mtd/nand/raw/nand_samsung.c:		u8 extid = chip->id.data[3];
+drivers/mtd/nand/raw/nand_samsung.c:		extid = (chip->id.data[4] >> 4) & 0x07;
+drivers/mtd/nand/raw/nand_samsung.c:			chip->base.eccreq.step_size = 512;
+drivers/mtd/nand/raw/nand_samsung.c:			chip->base.eccreq.strength = 1 << extid;
+drivers/mtd/nand/raw/nand_samsung.c:			chip->base.eccreq.step_size = 1024;
+drivers/mtd/nand/raw/nand_samsung.c:				chip->base.eccreq.strength = 24;
+drivers/mtd/nand/raw/nand_samsung.c:				chip->base.eccreq.strength = 40;
+drivers/mtd/nand/raw/nand_samsung.c:				chip->base.eccreq.strength = 60;
+drivers/mtd/nand/raw/nand_samsung.c:				chip->base.eccreq.step_size = 0;
+drivers/mtd/nand/raw/nand_samsung.c:			switch (chip->id.data[1]) {
+drivers/mtd/nand/raw/nand_samsung.c:				chip->base.eccreq.step_size = 512;
+drivers/mtd/nand/raw/nand_samsung.c:				chip->base.eccreq.strength = 1;
+drivers/mtd/nand/raw/nand_samsung.c:				if (chip->id.len > 4 &&
+drivers/mtd/nand/raw/nand_samsung.c:				    (chip->id.data[4] & GENMASK(1, 0)) == 0x1)
+drivers/mtd/nand/raw/nand_samsung.c:					chip->options |= NAND_NO_SUBPAGE_WRITE;
+drivers/mtd/nand/raw/nand_samsung.c:		chip->options |= NAND_SAMSUNG_LP_OPTIONS;
+drivers/mtd/nand/raw/nand_samsung.c:		chip->options |= NAND_BBM_LASTPAGE;
+drivers/mtd/nand/raw/nand_samsung.c:		chip->options |= NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE;
+drivers/mtd/nand/raw/nand_timings.c:	struct nand_data_interface *iface = &chip->data_interface;
+drivers/mtd/nand/raw/nand_timings.c:	struct onfi_params *onfi = chip->parameters.onfi;
+drivers/mtd/nand/raw/nand_toshiba.c:	 * This is why chip->ecc.bytes = 0.
+drivers/mtd/nand/raw/nand_toshiba.c:	chip->ecc.bytes = 0;
+drivers/mtd/nand/raw/nand_toshiba.c:	chip->ecc.size = 512;
+drivers/mtd/nand/raw/nand_toshiba.c:	chip->ecc.strength = 8;
+drivers/mtd/nand/raw/nand_toshiba.c:	chip->ecc.read_page = toshiba_nand_read_page_benand;
+drivers/mtd/nand/raw/nand_toshiba.c:	chip->ecc.read_subpage = toshiba_nand_read_subpage_benand;
+drivers/mtd/nand/raw/nand_toshiba.c:	chip->ecc.write_page = nand_write_page_raw;
+drivers/mtd/nand/raw/nand_toshiba.c:	chip->ecc.read_page_raw = nand_read_page_raw_notsupp;
+drivers/mtd/nand/raw/nand_toshiba.c:	chip->ecc.write_page_raw = nand_write_page_raw_notsupp;
+drivers/mtd/nand/raw/nand_toshiba.c:	chip->options |= NAND_SUBPAGE_READ;
+drivers/mtd/nand/raw/nand_toshiba.c:	memorg = nanddev_get_memorg(&chip->base);
+drivers/mtd/nand/raw/nand_toshiba.c:	if (chip->id.len >= 6 && nand_is_slc(chip) &&
+drivers/mtd/nand/raw/nand_toshiba.c:	    (chip->id.data[5] & 0x7) == 0x6 /* 24nm */ &&
+drivers/mtd/nand/raw/nand_toshiba.c:	    !(chip->id.data[4] & 0x80) /* !BENAND */) {
+drivers/mtd/nand/raw/nand_toshiba.c:	if (chip->id.len >= 6 && nand_is_slc(chip)) {
+drivers/mtd/nand/raw/nand_toshiba.c:		chip->base.eccreq.step_size = 512;
+drivers/mtd/nand/raw/nand_toshiba.c:		switch (chip->id.data[5] & 0x7) {
+drivers/mtd/nand/raw/nand_toshiba.c:			chip->base.eccreq.strength = 1;
+drivers/mtd/nand/raw/nand_toshiba.c:			chip->base.eccreq.strength = 4;
+drivers/mtd/nand/raw/nand_toshiba.c:			chip->base.eccreq.strength = 8;
+drivers/mtd/nand/raw/nand_toshiba.c:			chip->base.eccreq.step_size = 0;
+drivers/mtd/nand/raw/nand_toshiba.c:		chip->options |= NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE;
+drivers/mtd/nand/raw/nand_toshiba.c:	if (nand_is_slc(chip) && chip->ecc.mode == NAND_ECC_ON_DIE &&
+drivers/mtd/nand/raw/nand_toshiba.c:	    chip->id.data[4] & TOSHIBA_NAND_ID4_IS_BENAND)
+drivers/mtd/nand/raw/nandsim.c:	ns->busw = chip->options & NAND_BUSWIDTH_16 ? 16 : 8;
+drivers/mtd/nand/raw/nandsim.c:	ns->geom.pgshift  = chip->page_shift;
+drivers/mtd/nand/raw/nandsim.c:	chip->ecc.mode = NAND_ECC_SOFT;
+drivers/mtd/nand/raw/nandsim.c:	chip->ecc.algo = NAND_ECC_BCH;
+drivers/mtd/nand/raw/nandsim.c:	chip->ecc.size = 512;
+drivers/mtd/nand/raw/nandsim.c:	chip->ecc.strength = bch;
+drivers/mtd/nand/raw/nandsim.c:	chip->ecc.bytes = eccbytes;
+drivers/mtd/nand/raw/nandsim.c:	NS_INFO("Using %u-bit/%u bytes BCH ECC\n", bch, chip->ecc.size);
+drivers/mtd/nand/raw/nandsim.c:	chip->ecc.mode   = NAND_ECC_SOFT;
+drivers/mtd/nand/raw/nandsim.c:	chip->ecc.algo   = NAND_ECC_HAMMING;
+drivers/mtd/nand/raw/nandsim.c:	chip->options   |= NAND_SKIP_BBTSCAN;
+drivers/mtd/nand/raw/nandsim.c:		chip->bbt_options |= NAND_BBT_NO_OOB;
+drivers/mtd/nand/raw/nandsim.c:		chip->bbt_options |= NAND_BBT_USE_FLASH;
+drivers/mtd/nand/raw/nandsim.c:		chip->options |= NAND_BUSWIDTH_16;
+drivers/mtd/nand/raw/nandsim.c:	chip->controller = &ns->base;
+drivers/mtd/nand/raw/nandsim.c:		memorg = nanddev_get_memorg(&chip->base);
+drivers/mtd/nand/raw/nandsim.c:		targetsize = nanddev_target_size(&chip->base);
+drivers/mtd/nand/raw/nandsim.c:		chip->chip_shift = ffs(nsmtd->erasesize) + overridesize - 1;
+drivers/mtd/nand/raw/nandsim.c:		chip->pagemask = (targetsize >> chip->page_shift) - 1;
+drivers/mtd/nand/raw/ndfc.c:	chip->legacy.IO_ADDR_R = ndfc->ndfcbase + NDFC_DATA;
+drivers/mtd/nand/raw/ndfc.c:	chip->legacy.IO_ADDR_W = ndfc->ndfcbase + NDFC_DATA;
+drivers/mtd/nand/raw/ndfc.c:	chip->legacy.cmd_ctrl = ndfc_hwcontrol;
+drivers/mtd/nand/raw/ndfc.c:	chip->legacy.dev_ready = ndfc_ready;
+drivers/mtd/nand/raw/ndfc.c:	chip->legacy.select_chip = ndfc_select_chip;
+drivers/mtd/nand/raw/ndfc.c:	chip->legacy.chip_delay = 50;
+drivers/mtd/nand/raw/ndfc.c:	chip->controller = &ndfc->ndfc_control;
+drivers/mtd/nand/raw/ndfc.c:	chip->legacy.read_buf = ndfc_read_buf;
+drivers/mtd/nand/raw/ndfc.c:	chip->legacy.write_buf = ndfc_write_buf;
+drivers/mtd/nand/raw/ndfc.c:	chip->ecc.correct = nand_correct_data;
+drivers/mtd/nand/raw/ndfc.c:	chip->ecc.hwctl = ndfc_enable_hwecc;
+drivers/mtd/nand/raw/ndfc.c:	chip->ecc.calculate = ndfc_calculate_ecc;
+drivers/mtd/nand/raw/ndfc.c:	chip->ecc.mode = NAND_ECC_HW;
+drivers/mtd/nand/raw/ndfc.c:	chip->ecc.size = 256;
+drivers/mtd/nand/raw/ndfc.c:	chip->ecc.bytes = 3;
+drivers/mtd/nand/raw/ndfc.c:	chip->ecc.strength = 1;
+drivers/mtd/nand/raw/omap2.c:	unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
+drivers/mtd/nand/raw/omap2.c:		nsectors = chip->ecc.steps;
+drivers/mtd/nand/raw/omap2.c:		nsectors = chip->ecc.steps;
+drivers/mtd/nand/raw/omap2.c:		nsectors = chip->ecc.steps;
+drivers/mtd/nand/raw/omap2.c:	dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
+drivers/mtd/nand/raw/omap2.c: * @oob_required:	must write chip->oob_poi to OOB
+drivers/mtd/nand/raw/omap2.c:	uint8_t *ecc_calc = chip->ecc.calc_buf;
+drivers/mtd/nand/raw/omap2.c:	chip->ecc.hwctl(chip, NAND_ECC_WRITE);
+drivers/mtd/nand/raw/omap2.c:	chip->legacy.write_buf(chip, buf, mtd->writesize);
+drivers/mtd/nand/raw/omap2.c:	ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,
+drivers/mtd/nand/raw/omap2.c:					 chip->ecc.total);
+drivers/mtd/nand/raw/omap2.c:	chip->legacy.write_buf(chip, chip->oob_poi, mtd->oobsize);
+drivers/mtd/nand/raw/omap2.c: * @oob_required: must write chip->oob_poi to OOB
+drivers/mtd/nand/raw/omap2.c:	u8 *ecc_calc = chip->ecc.calc_buf;
+drivers/mtd/nand/raw/omap2.c:	int ecc_size      = chip->ecc.size;
+drivers/mtd/nand/raw/omap2.c:	int ecc_bytes     = chip->ecc.bytes;
+drivers/mtd/nand/raw/omap2.c:	int ecc_steps     = chip->ecc.steps;
+drivers/mtd/nand/raw/omap2.c:	chip->ecc.hwctl(chip, NAND_ECC_WRITE);
+drivers/mtd/nand/raw/omap2.c:	chip->legacy.write_buf(chip, buf, mtd->writesize);
+drivers/mtd/nand/raw/omap2.c:	/* copy calculated ECC for whole page to chip->buffer->oob */
+drivers/mtd/nand/raw/omap2.c:	ecc_calc = chip->ecc.calc_buf;
+drivers/mtd/nand/raw/omap2.c:	ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,
+drivers/mtd/nand/raw/omap2.c:					 chip->ecc.total);
+drivers/mtd/nand/raw/omap2.c:	chip->legacy.write_buf(chip, chip->oob_poi, mtd->oobsize);
+drivers/mtd/nand/raw/omap2.c: * @oob_required:	caller requires OOB data read to chip->oob_poi
+drivers/mtd/nand/raw/omap2.c:	uint8_t *ecc_calc = chip->ecc.calc_buf;
+drivers/mtd/nand/raw/omap2.c:	uint8_t *ecc_code = chip->ecc.code_buf;
+drivers/mtd/nand/raw/omap2.c:	chip->ecc.hwctl(chip, NAND_ECC_READ);
+drivers/mtd/nand/raw/omap2.c:	chip->legacy.read_buf(chip, buf, mtd->writesize);
+drivers/mtd/nand/raw/omap2.c:				   chip->oob_poi + BADBLOCK_MARKER_LENGTH,
+drivers/mtd/nand/raw/omap2.c:				   chip->ecc.total, false);
+drivers/mtd/nand/raw/omap2.c:	ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
+drivers/mtd/nand/raw/omap2.c:					 chip->ecc.total);
+drivers/mtd/nand/raw/omap2.c:	stat = chip->ecc.correct(chip, buf, ecc_code, ecc_calc);
+drivers/mtd/nand/raw/omap2.c:	    !(chip->options & NAND_BUSWIDTH_16))
+drivers/mtd/nand/raw/omap2.c:	oobregion->length = chip->ecc.total;
+drivers/mtd/nand/raw/omap2.c:	    !(chip->options & NAND_BUSWIDTH_16))
+drivers/mtd/nand/raw/omap2.c:	off += chip->ecc.total;
+drivers/mtd/nand/raw/omap2.c:	if (section >= chip->ecc.steps)
+drivers/mtd/nand/raw/omap2.c:	oobregion->offset = off + (section * (chip->ecc.bytes + 1));
+drivers/mtd/nand/raw/omap2.c:	oobregion->length = chip->ecc.bytes;
+drivers/mtd/nand/raw/omap2.c:	off += ((chip->ecc.bytes + 1) * chip->ecc.steps);
+drivers/mtd/nand/raw/omap2.c:	if (chip->bbt_options & NAND_BBT_USE_FLASH)
+drivers/mtd/nand/raw/omap2.c:		chip->bbt_options |= NAND_BBT_NO_OOB;
+drivers/mtd/nand/raw/omap2.c:		chip->options |= NAND_SKIP_BBTSCAN;
+drivers/mtd/nand/raw/omap2.c:		chip->legacy.read_buf = omap_read_buf_pref;
+drivers/mtd/nand/raw/omap2.c:		chip->legacy.write_buf = omap_write_buf_pref;
+drivers/mtd/nand/raw/omap2.c:			chip->legacy.read_buf = omap_read_buf_dma_pref;
+drivers/mtd/nand/raw/omap2.c:			chip->legacy.write_buf = omap_write_buf_dma_pref;
+drivers/mtd/nand/raw/omap2.c:		chip->legacy.read_buf = omap_read_buf_irq_pref;
+drivers/mtd/nand/raw/omap2.c:		chip->legacy.write_buf = omap_write_buf_irq_pref;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.mode = NAND_ECC_SOFT;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.algo = NAND_ECC_HAMMING;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.mode		= NAND_ECC_HW;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.bytes		= 3;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.size		= 512;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.strength	= 1;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.calculate	= omap_calculate_ecc;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.hwctl		= omap_enable_hwecc;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.correct	= omap_correct_data;
+drivers/mtd/nand/raw/omap2.c:		oobbytes_per_step	= chip->ecc.bytes;
+drivers/mtd/nand/raw/omap2.c:		if (!(chip->options & NAND_BUSWIDTH_16))
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.mode		= NAND_ECC_HW;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.size		= 512;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.bytes		= 7;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.strength	= 4;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.hwctl		= omap_enable_hwecc_bch;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.correct	= nand_bch_correct_data;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.calculate	= omap_calculate_ecc_bch_sw;
+drivers/mtd/nand/raw/omap2.c:		oobbytes_per_step	= chip->ecc.bytes + 1;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.priv		= nand_bch_init(mtd);
+drivers/mtd/nand/raw/omap2.c:		if (!chip->ecc.priv) {
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.mode		= NAND_ECC_HW;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.size		= 512;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.bytes		= 7 + 1;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.strength	= 4;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.hwctl		= omap_enable_hwecc_bch;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.correct	= omap_elm_correct_data;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.read_page	= omap_read_page_bch;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.write_page	= omap_write_page_bch;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.write_subpage	= omap_write_subpage_bch;
+drivers/mtd/nand/raw/omap2.c:		oobbytes_per_step	= chip->ecc.bytes;
+drivers/mtd/nand/raw/omap2.c:				 mtd->writesize / chip->ecc.size,
+drivers/mtd/nand/raw/omap2.c:				 chip->ecc.size, chip->ecc.bytes);
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.mode		= NAND_ECC_HW;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.size		= 512;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.bytes		= 13;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.strength	= 8;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.hwctl		= omap_enable_hwecc_bch;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.correct	= nand_bch_correct_data;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.calculate	= omap_calculate_ecc_bch_sw;
+drivers/mtd/nand/raw/omap2.c:		oobbytes_per_step	= chip->ecc.bytes + 1;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.priv		= nand_bch_init(mtd);
+drivers/mtd/nand/raw/omap2.c:		if (!chip->ecc.priv) {
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.mode		= NAND_ECC_HW;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.size		= 512;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.bytes		= 13 + 1;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.strength	= 8;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.hwctl		= omap_enable_hwecc_bch;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.correct	= omap_elm_correct_data;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.read_page	= omap_read_page_bch;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.write_page	= omap_write_page_bch;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.write_subpage	= omap_write_subpage_bch;
+drivers/mtd/nand/raw/omap2.c:		oobbytes_per_step	= chip->ecc.bytes;
+drivers/mtd/nand/raw/omap2.c:				 mtd->writesize / chip->ecc.size,
+drivers/mtd/nand/raw/omap2.c:				 chip->ecc.size, chip->ecc.bytes);
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.mode		= NAND_ECC_HW;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.size		= 512;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.bytes		= 26;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.strength	= 16;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.hwctl		= omap_enable_hwecc_bch;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.correct	= omap_elm_correct_data;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.read_page	= omap_read_page_bch;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.write_page	= omap_write_page_bch;
+drivers/mtd/nand/raw/omap2.c:		chip->ecc.write_subpage	= omap_write_subpage_bch;
+drivers/mtd/nand/raw/omap2.c:		oobbytes_per_step	= chip->ecc.bytes;
+drivers/mtd/nand/raw/omap2.c:				 mtd->writesize / chip->ecc.size,
+drivers/mtd/nand/raw/omap2.c:				 chip->ecc.size, chip->ecc.bytes);
+drivers/mtd/nand/raw/omap2.c:			 (mtd->writesize / chip->ecc.size));
+drivers/mtd/nand/raw/omap2.c:	nand_chip->ecc.priv	= NULL;
+drivers/mtd/nand/raw/omap2.c:	nand_chip->legacy.IO_ADDR_R = devm_ioremap_resource(&pdev->dev, res);
+drivers/mtd/nand/raw/omap2.c:	if (IS_ERR(nand_chip->legacy.IO_ADDR_R))
+drivers/mtd/nand/raw/omap2.c:		return PTR_ERR(nand_chip->legacy.IO_ADDR_R);
+drivers/mtd/nand/raw/omap2.c:	nand_chip->controller = &omap_gpmc_controller;
+drivers/mtd/nand/raw/omap2.c:	nand_chip->legacy.IO_ADDR_W = nand_chip->legacy.IO_ADDR_R;
+drivers/mtd/nand/raw/omap2.c:	nand_chip->legacy.cmd_ctrl  = omap_hwcontrol;
+drivers/mtd/nand/raw/omap2.c:		nand_chip->legacy.dev_ready = omap_dev_ready;
+drivers/mtd/nand/raw/omap2.c:		nand_chip->legacy.chip_delay = 0;
+drivers/mtd/nand/raw/omap2.c:		nand_chip->legacy.waitfunc = omap_wait;
+drivers/mtd/nand/raw/omap2.c:		nand_chip->legacy.chip_delay = 50;
+drivers/mtd/nand/raw/omap2.c:		nand_chip->bbt_options |= NAND_BBT_USE_FLASH;
+drivers/mtd/nand/raw/omap2.c:	nand_chip->options |= info->devsize & NAND_BUSWIDTH_16;
+drivers/mtd/nand/raw/omap2.c:	if (nand_chip->ecc.priv) {
+drivers/mtd/nand/raw/omap2.c:		nand_bch_free(nand_chip->ecc.priv);
+drivers/mtd/nand/raw/omap2.c:		nand_chip->ecc.priv = NULL;
+drivers/mtd/nand/raw/omap2.c:	if (nand_chip->ecc.priv) {
+drivers/mtd/nand/raw/omap2.c:		nand_bch_free(nand_chip->ecc.priv);
+drivers/mtd/nand/raw/omap2.c:		nand_chip->ecc.priv = NULL;
+drivers/mtd/nand/raw/orion_nand.c:	void __iomem *io_base = chip->legacy.IO_ADDR_R;
+drivers/mtd/nand/raw/orion_nand.c:						"chip-delay", &val))
+drivers/mtd/nand/raw/oxnas_nand.c:		chip->controller = &oxnas->base;
+drivers/mtd/nand/raw/oxnas_nand.c:		chip->legacy.cmd_ctrl = oxnas_nand_cmd_ctrl;
+drivers/mtd/nand/raw/oxnas_nand.c:		chip->legacy.read_buf = oxnas_nand_read_buf;
+drivers/mtd/nand/raw/oxnas_nand.c:		chip->legacy.read_byte = oxnas_nand_read_byte;
+drivers/mtd/nand/raw/oxnas_nand.c:		chip->legacy.write_buf = oxnas_nand_write_buf;
+drivers/mtd/nand/raw/oxnas_nand.c:		chip->legacy.chip_delay = 30;
+drivers/mtd/nand/raw/pasemi_nand.c:		memcpy_fromio(buf, chip->legacy.IO_ADDR_R, 0x800);
+drivers/mtd/nand/raw/pasemi_nand.c:	memcpy_fromio(buf, chip->legacy.IO_ADDR_R, len);
+drivers/mtd/nand/raw/pasemi_nand.c:		memcpy_toio(chip->legacy.IO_ADDR_R, buf, 0x800);
+drivers/mtd/nand/raw/pasemi_nand.c:	memcpy_toio(chip->legacy.IO_ADDR_R, buf, len);
+drivers/mtd/nand/raw/pasemi_nand.c:		out_8(chip->legacy.IO_ADDR_W + (1 << CLE_PIN_CTL), cmd);
+drivers/mtd/nand/raw/pasemi_nand.c:		out_8(chip->legacy.IO_ADDR_W + (1 << ALE_PIN_CTL), cmd);
+drivers/mtd/nand/raw/pasemi_nand.c:	chip->legacy.IO_ADDR_R = of_iomap(np, 0);
+drivers/mtd/nand/raw/pasemi_nand.c:	chip->legacy.IO_ADDR_W = chip->legacy.IO_ADDR_R;
+drivers/mtd/nand/raw/pasemi_nand.c:	if (!chip->legacy.IO_ADDR_R) {
+drivers/mtd/nand/raw/pasemi_nand.c:	chip->legacy.cmd_ctrl = pasemi_hwcontrol;
+drivers/mtd/nand/raw/pasemi_nand.c:	chip->legacy.dev_ready = pasemi_device_ready;
+drivers/mtd/nand/raw/pasemi_nand.c:	chip->legacy.read_buf = pasemi_read_buf;
+drivers/mtd/nand/raw/pasemi_nand.c:	chip->legacy.write_buf = pasemi_write_buf;
+drivers/mtd/nand/raw/pasemi_nand.c:	chip->legacy.chip_delay = 0;
+drivers/mtd/nand/raw/pasemi_nand.c:	chip->ecc.mode = NAND_ECC_SOFT;
+drivers/mtd/nand/raw/pasemi_nand.c:	chip->ecc.algo = NAND_ECC_HAMMING;
+drivers/mtd/nand/raw/pasemi_nand.c:	chip->bbt_options = NAND_BBT_USE_FLASH;
+drivers/mtd/nand/raw/pasemi_nand.c:	iounmap(chip->legacy.IO_ADDR_R);
+drivers/mtd/nand/raw/pasemi_nand.c:	iounmap(chip->legacy.IO_ADDR_R);
+drivers/mtd/nand/raw/qcom_nandc.c: * @buf_size/count/start:	markers for chip->legacy.read_buf/write_buf
+drivers/mtd/nand/raw/qcom_nandc.c:	return container_of(chip->controller, struct qcom_nand_controller,
+drivers/mtd/nand/raw/qcom_nandc.c:	if (chip->options & NAND_BUSWIDTH_16)
+drivers/mtd/nand/raw/qcom_nandc.c: * the following functions are used within chip->legacy.cmdfunc() to
+drivers/mtd/nand/raw/qcom_nandc.c:	struct nand_ecc_ctrl *ecc = &chip->ecc;
+drivers/mtd/nand/raw/qcom_nandc.c: * Implements chip->legacy.cmdfunc. It's  only used for a limited set of
+drivers/mtd/nand/raw/qcom_nandc.c:	struct nand_ecc_ctrl *ecc = &chip->ecc;
+drivers/mtd/nand/raw/qcom_nandc.c:	struct nand_ecc_ctrl *ecc = &chip->ecc;
+drivers/mtd/nand/raw/qcom_nandc.c: *    chip->data_buf if data buf is null and chip->oob_poi if oob buf
+drivers/mtd/nand/raw/qcom_nandc.c:	struct nand_ecc_ctrl *ecc = &chip->ecc;
+drivers/mtd/nand/raw/qcom_nandc.c:		oob_buf = chip->oob_poi;
+drivers/mtd/nand/raw/qcom_nandc.c:	struct nand_ecc_ctrl *ecc = &chip->ecc;
+drivers/mtd/nand/raw/qcom_nandc.c:	struct nand_ecc_ctrl *ecc = &chip->ecc;
+drivers/mtd/nand/raw/qcom_nandc.c:	struct nand_ecc_ctrl *ecc = &chip->ecc;
+drivers/mtd/nand/raw/qcom_nandc.c:	oob_buf = oob_required ? chip->oob_poi : NULL;
+drivers/mtd/nand/raw/qcom_nandc.c:	struct nand_ecc_ctrl *ecc = &chip->ecc;
+drivers/mtd/nand/raw/qcom_nandc.c:	u8 *data_buf = buf, *oob_buf = chip->oob_poi;
+drivers/mtd/nand/raw/qcom_nandc.c:	struct nand_ecc_ctrl *ecc = &chip->ecc;
+drivers/mtd/nand/raw/qcom_nandc.c:	return read_page_ecc(host, NULL, chip->oob_poi, page);
+drivers/mtd/nand/raw/qcom_nandc.c:	struct nand_ecc_ctrl *ecc = &chip->ecc;
+drivers/mtd/nand/raw/qcom_nandc.c:	oob_buf = chip->oob_poi;
+drivers/mtd/nand/raw/qcom_nandc.c:	struct nand_ecc_ctrl *ecc = &chip->ecc;
+drivers/mtd/nand/raw/qcom_nandc.c:	oob_buf = chip->oob_poi;
+drivers/mtd/nand/raw/qcom_nandc.c: * chip->oob_poi, and pad the data area with OxFF before writing.
+drivers/mtd/nand/raw/qcom_nandc.c:	struct nand_ecc_ctrl *ecc = &chip->ecc;
+drivers/mtd/nand/raw/qcom_nandc.c:	u8 *oob = chip->oob_poi;
+drivers/mtd/nand/raw/qcom_nandc.c:	struct nand_ecc_ctrl *ecc = &chip->ecc;
+drivers/mtd/nand/raw/qcom_nandc.c:	page = (int)(ofs >> chip->page_shift) & chip->pagemask;
+drivers/mtd/nand/raw/qcom_nandc.c:	if (chip->options & NAND_BUSWIDTH_16)
+drivers/mtd/nand/raw/qcom_nandc.c:	struct nand_ecc_ctrl *ecc = &chip->ecc;
+drivers/mtd/nand/raw/qcom_nandc.c:	page = (int)(ofs >> chip->page_shift) & chip->pagemask;
+drivers/mtd/nand/raw/qcom_nandc.c: * the three functions below implement chip->legacy.read_byte(),
+drivers/mtd/nand/raw/qcom_nandc.c: * chip->legacy.read_buf() and chip->legacy.write_buf() respectively. these
+drivers/mtd/nand/raw/qcom_nandc.c:	struct nand_ecc_ctrl *ecc = &chip->ecc;
+drivers/mtd/nand/raw/qcom_nandc.c:	struct nand_ecc_ctrl *ecc = &chip->ecc;
+drivers/mtd/nand/raw/qcom_nandc.c:	struct nand_ecc_ctrl *ecc = &chip->ecc;
+drivers/mtd/nand/raw/qcom_nandc.c:	wide_bus = chip->options & NAND_BUSWIDTH_16 ? true : false;
+drivers/mtd/nand/raw/qcom_nandc.c:		dev_err(dev, "can't get chip-select\n");
+drivers/mtd/nand/raw/qcom_nandc.c:	chip->legacy.cmdfunc	= qcom_nandc_command;
+drivers/mtd/nand/raw/qcom_nandc.c:	chip->legacy.select_chip	= qcom_nandc_select_chip;
+drivers/mtd/nand/raw/qcom_nandc.c:	chip->legacy.read_byte	= qcom_nandc_read_byte;
+drivers/mtd/nand/raw/qcom_nandc.c:	chip->legacy.read_buf	= qcom_nandc_read_buf;
+drivers/mtd/nand/raw/qcom_nandc.c:	chip->legacy.write_buf	= qcom_nandc_write_buf;
+drivers/mtd/nand/raw/qcom_nandc.c:	chip->legacy.set_features	= nand_get_set_features_notsupp;
+drivers/mtd/nand/raw/qcom_nandc.c:	chip->legacy.get_features	= nand_get_set_features_notsupp;
+drivers/mtd/nand/raw/qcom_nandc.c:	chip->legacy.block_bad		= qcom_nandc_block_bad;
+drivers/mtd/nand/raw/qcom_nandc.c:	chip->legacy.block_markbad	= qcom_nandc_block_markbad;
+drivers/mtd/nand/raw/qcom_nandc.c:	chip->controller = &nandc->controller;
+drivers/mtd/nand/raw/qcom_nandc.c:	chip->options |= NAND_NO_SUBPAGE_WRITE | NAND_USE_BOUNCE_BUFFER |
+drivers/mtd/nand/raw/r852.c:		if (chip->legacy.dev_ready(chip))
+drivers/mtd/nand/raw/r852.c:	return nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
+drivers/mtd/nand/raw/r852.c:		dev->chip->options |= NAND_ROM;
+drivers/mtd/nand/raw/r852.c:	chip->legacy.cmd_ctrl = r852_cmdctl;
+drivers/mtd/nand/raw/r852.c:	chip->legacy.waitfunc = r852_wait;
+drivers/mtd/nand/raw/r852.c:	chip->legacy.dev_ready = r852_ready;
+drivers/mtd/nand/raw/r852.c:	chip->legacy.read_byte = r852_read_byte;
+drivers/mtd/nand/raw/r852.c:	chip->legacy.read_buf = r852_read_buf;
+drivers/mtd/nand/raw/r852.c:	chip->legacy.write_buf = r852_write_buf;
+drivers/mtd/nand/raw/r852.c:	chip->ecc.mode = NAND_ECC_HW_SYNDROME;
+drivers/mtd/nand/raw/r852.c:	chip->ecc.size = R852_DMA_LEN;
+drivers/mtd/nand/raw/r852.c:	chip->ecc.bytes = SM_OOB_SIZE;
+drivers/mtd/nand/raw/r852.c:	chip->ecc.strength = 2;
+drivers/mtd/nand/raw/r852.c:	chip->ecc.hwctl = r852_ecc_hwctl;
+drivers/mtd/nand/raw/r852.c:	chip->ecc.calculate = r852_ecc_calculate;
+drivers/mtd/nand/raw/r852.c:	chip->ecc.correct = r852_ecc_correct;
+drivers/mtd/nand/raw/r852.c:	chip->ecc.read_oob = r852_read_oob;
+drivers/mtd/nand/raw/s3c2410.c:	chip->legacy.write_buf    = s3c2410_nand_write_buf;
+drivers/mtd/nand/raw/s3c2410.c:	chip->legacy.read_buf     = s3c2410_nand_read_buf;
+drivers/mtd/nand/raw/s3c2410.c:	chip->legacy.select_chip  = s3c2410_nand_select_chip;
+drivers/mtd/nand/raw/s3c2410.c:	chip->legacy.chip_delay   = 50;
+drivers/mtd/nand/raw/s3c2410.c:	chip->options	   = set->options;
+drivers/mtd/nand/raw/s3c2410.c:	chip->controller   = &info->controller;
+drivers/mtd/nand/raw/s3c2410.c:		chip->options |= NAND_KEEP_TIMINGS;
+drivers/mtd/nand/raw/s3c2410.c:		chip->legacy.IO_ADDR_W = regs + S3C2410_NFDATA;
+drivers/mtd/nand/raw/s3c2410.c:		chip->legacy.cmd_ctrl  = s3c2410_nand_hwcontrol;
+drivers/mtd/nand/raw/s3c2410.c:		chip->legacy.dev_ready = s3c2410_nand_devready;
+drivers/mtd/nand/raw/s3c2410.c:		chip->legacy.IO_ADDR_W = regs + S3C2440_NFDATA;
+drivers/mtd/nand/raw/s3c2410.c:		chip->legacy.cmd_ctrl  = s3c2440_nand_hwcontrol;
+drivers/mtd/nand/raw/s3c2410.c:		chip->legacy.dev_ready = s3c2440_nand_devready;
+drivers/mtd/nand/raw/s3c2410.c:		chip->legacy.read_buf  = s3c2440_nand_read_buf;
+drivers/mtd/nand/raw/s3c2410.c:		chip->legacy.write_buf	= s3c2440_nand_write_buf;
+drivers/mtd/nand/raw/s3c2410.c:		chip->legacy.IO_ADDR_W = regs + S3C2440_NFDATA;
+drivers/mtd/nand/raw/s3c2410.c:		chip->legacy.cmd_ctrl  = s3c2440_nand_hwcontrol;
+drivers/mtd/nand/raw/s3c2410.c:		chip->legacy.dev_ready = s3c2412_nand_devready;
+drivers/mtd/nand/raw/s3c2410.c:	chip->legacy.IO_ADDR_R = chip->legacy.IO_ADDR_W;
+drivers/mtd/nand/raw/s3c2410.c:	chip->ecc.mode = info->platform->ecc_mode;
+drivers/mtd/nand/raw/s3c2410.c:		chip->bbt_options |= NAND_BBT_USE_FLASH;
+drivers/mtd/nand/raw/s3c2410.c:	switch (chip->ecc.mode) {
+drivers/mtd/nand/raw/s3c2410.c:		chip->ecc.algo = NAND_ECC_HAMMING;
+drivers/mtd/nand/raw/s3c2410.c:		chip->ecc.calculate = s3c2410_nand_calculate_ecc;
+drivers/mtd/nand/raw/s3c2410.c:		chip->ecc.correct   = s3c2410_nand_correct_data;
+drivers/mtd/nand/raw/s3c2410.c:		chip->ecc.strength  = 1;
+drivers/mtd/nand/raw/s3c2410.c:			chip->ecc.hwctl	    = s3c2410_nand_enable_hwecc;
+drivers/mtd/nand/raw/s3c2410.c:			chip->ecc.calculate = s3c2410_nand_calculate_ecc;
+drivers/mtd/nand/raw/s3c2410.c:			chip->ecc.hwctl     = s3c2412_nand_enable_hwecc;
+drivers/mtd/nand/raw/s3c2410.c:			chip->ecc.calculate = s3c2412_nand_calculate_ecc;
+drivers/mtd/nand/raw/s3c2410.c:			chip->ecc.hwctl     = s3c2440_nand_enable_hwecc;
+drivers/mtd/nand/raw/s3c2410.c:			chip->ecc.calculate = s3c2440_nand_calculate_ecc;
+drivers/mtd/nand/raw/s3c2410.c:			chip, chip->page_shift);
+drivers/mtd/nand/raw/s3c2410.c:		if (chip->page_shift > 10) {
+drivers/mtd/nand/raw/s3c2410.c:			chip->ecc.size	    = 256;
+drivers/mtd/nand/raw/s3c2410.c:			chip->ecc.bytes	    = 3;
+drivers/mtd/nand/raw/s3c2410.c:			chip->ecc.size	    = 512;
+drivers/mtd/nand/raw/s3c2410.c:			chip->ecc.bytes	    = 3;
+drivers/mtd/nand/raw/s3c2410.c:	if (chip->bbt_options & NAND_BBT_USE_FLASH)
+drivers/mtd/nand/raw/s3c2410.c:		chip->options |= NAND_SKIP_BBTSCAN;
+drivers/mtd/nand/raw/sh_flctl.c:	oobregion->length = chip->ecc.bytes;
+drivers/mtd/nand/raw/sh_flctl.c:	if (section >= chip->ecc.steps)
+drivers/mtd/nand/raw/sh_flctl.c:	oobregion->length = chip->ecc.bytes;
+drivers/mtd/nand/raw/sh_flctl.c:	if (section >= chip->ecc.steps)
+drivers/mtd/nand/raw/sh_flctl.c:		chip->legacy.read_buf(chip, chip->oob_poi, mtd->oobsize);
+drivers/mtd/nand/raw/sh_flctl.c:	chip->legacy.write_buf(chip, chip->oob_poi, mtd->oobsize);
+drivers/mtd/nand/raw/sh_flctl.c:	u64 targetsize = nanddev_target_size(&chip->base);
+drivers/mtd/nand/raw/sh_flctl.c:	if (chip->options & NAND_BUSWIDTH_16)
+drivers/mtd/nand/raw/sh_flctl.c:			chip->badblock_pattern = &flctl_4secc_smallpage;
+drivers/mtd/nand/raw/sh_flctl.c:			chip->badblock_pattern = &flctl_4secc_largepage;
+drivers/mtd/nand/raw/sh_flctl.c:		chip->ecc.size = 512;
+drivers/mtd/nand/raw/sh_flctl.c:		chip->ecc.bytes = 10;
+drivers/mtd/nand/raw/sh_flctl.c:		chip->ecc.strength = 4;
+drivers/mtd/nand/raw/sh_flctl.c:		chip->ecc.read_page = flctl_read_page_hwecc;
+drivers/mtd/nand/raw/sh_flctl.c:		chip->ecc.write_page = flctl_write_page_hwecc;
+drivers/mtd/nand/raw/sh_flctl.c:		chip->ecc.mode = NAND_ECC_HW;
+drivers/mtd/nand/raw/sh_flctl.c:		chip->ecc.mode = NAND_ECC_SOFT;
+drivers/mtd/nand/raw/sh_flctl.c:		chip->ecc.algo = NAND_ECC_HAMMING;
+drivers/mtd/nand/raw/sharpsl.c:		writeb(cmd, chip->legacy.IO_ADDR_W);
+drivers/mtd/nand/raw/sm_common.c:	chip->badblockpos = 0x05;
+drivers/mtd/nand/raw/sm_common.c:	chip->badblockbits = 7;
+drivers/mtd/nand/raw/sm_common.c:	chip->legacy.block_markbad = sm_block_markbad;
+drivers/mtd/nand/raw/sm_common.c:	chip->options |= NAND_SKIP_BBTSCAN;
+drivers/mtd/nand/raw/sm_common.c:	chip->legacy.dummy_controller.ops = &sm_controller_ops;
+drivers/mtd/nand/raw/socrates_nand.c:	nand_chip->legacy.cmd_ctrl = socrates_nand_cmd_ctrl;
+drivers/mtd/nand/raw/socrates_nand.c:	nand_chip->legacy.read_byte = socrates_nand_read_byte;
+drivers/mtd/nand/raw/socrates_nand.c:	nand_chip->legacy.write_buf = socrates_nand_write_buf;
+drivers/mtd/nand/raw/socrates_nand.c:	nand_chip->legacy.read_buf = socrates_nand_read_buf;
+drivers/mtd/nand/raw/socrates_nand.c:	nand_chip->legacy.dev_ready = socrates_nand_device_ready;
+drivers/mtd/nand/raw/socrates_nand.c:	nand_chip->ecc.mode = NAND_ECC_SOFT;	/* enable ECC */
+drivers/mtd/nand/raw/socrates_nand.c:	nand_chip->ecc.algo = NAND_ECC_HAMMING;
+drivers/mtd/nand/raw/socrates_nand.c:	nand_chip->legacy.chip_delay = 20;	/* 20us command delay time */
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	if (chip->ecc.strength == FMC2_ECC_BCH8) {
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	} else if (chip->ecc.strength == FMC2_ECC_BCH4) {
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	if (chip->options & NAND_BUSWIDTH_16)
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:		dma_cfg.src_addr += chip->ecc.strength == FMC2_ECC_HAM ?
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:		fmc2->dma_ecc_len = chip->ecc.strength == FMC2_ECC_HAM ?
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	if (chip->ecc.strength != FMC2_ECC_HAM) {
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	if (chip->ecc.strength == FMC2_ECC_BCH8) {
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	return stm32_fmc2_bch_decode(chip->ecc.size, dat, ecc_sta);
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	int ret, i, s, stat, eccsize = chip->ecc.size;
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	int eccbytes = chip->ecc.bytes;
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	int eccsteps = chip->ecc.steps;
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	int eccstrength = chip->ecc.strength;
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	u8 *ecc_calc = chip->ecc.calc_buf;
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	u8 *ecc_code = chip->ecc.code_buf;
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:		chip->ecc.hwctl(chip, NAND_ECC_READ);
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:		stat = chip->ecc.correct(chip, p, ecc_code, ecc_calc);
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:						 chip->oob_poi, mtd->oobsize,
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	csqcfgr3 = FMC2_CSQCFGR3_SNBR(chip->ecc.steps - 1);
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:		if (chip->options & NAND_ROW_ADDR_3)
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	if (chip->options & NAND_BUSWIDTH_16)
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	if (chip->options & NAND_ROW_ADDR_3) {
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	int eccsteps = chip->ecc.steps;
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	int eccsize = chip->ecc.size;
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:						  chip->oob_poi, mtd->oobsize,
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	ret = stm32_fmc2_select_chip(chip, chip->cur_cs);
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	ret = stm32_fmc2_select_chip(chip, chip->cur_cs);
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	int eccbytes = chip->ecc.bytes;
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	int eccsteps = chip->ecc.steps;
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	int eccstrength = chip->ecc.strength;
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	int i, s, eccsize = chip->ecc.size;
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	u8 *ecc_calc = chip->ecc.calc_buf;
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	u8 *ecc_code = chip->ecc.code_buf;
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	ret = stm32_fmc2_select_chip(chip, chip->cur_cs);
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:							  chip->oob_poi,
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:					 chip->oob_poi, mtd->oobsize, false);
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:					 chip->ecc.total);
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	return chip->ecc.correct(chip, buf, ecc_code, ecc_calc);
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	ret = stm32_fmc2_select_chip(chip, chip->cur_cs);
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:						  chip->oob_poi, mtd->oobsize,
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	if (force_8bit && chip->options & NAND_BUSWIDTH_16)
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	if (force_8bit && chip->options & NAND_BUSWIDTH_16)
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	if (force_8bit && chip->options & NAND_BUSWIDTH_16)
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	if (force_8bit && chip->options & NAND_BUSWIDTH_16)
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:		chip->ecc.correct = stm32_fmc2_sequencer_correct;
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:		chip->ecc.write_page = stm32_fmc2_sequencer_write_page;
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:		chip->ecc.read_page = stm32_fmc2_sequencer_read_page;
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:		chip->ecc.write_page_raw = stm32_fmc2_sequencer_write_page_raw;
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:		chip->ecc.read_page_raw = stm32_fmc2_sequencer_read_page_raw;
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:		chip->ecc.hwctl = stm32_fmc2_hwctl;
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:		if (chip->ecc.strength == FMC2_ECC_HAM) {
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:			chip->ecc.calculate = stm32_fmc2_ham_calculate;
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:			chip->ecc.correct = stm32_fmc2_ham_correct;
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:			chip->ecc.options |= NAND_ECC_GENERIC_ERASED_CHECK;
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:			chip->ecc.calculate = stm32_fmc2_bch_calculate;
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:			chip->ecc.correct = stm32_fmc2_bch_correct;
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:			chip->ecc.read_page = stm32_fmc2_read_page;
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	if (chip->ecc.strength == FMC2_ECC_HAM)
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:		chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 4 : 3;
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	else if (chip->ecc.strength == FMC2_ECC_BCH8)
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:		chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 14 : 13;
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:		chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 8 : 7;
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	struct nand_ecc_ctrl *ecc = &chip->ecc;
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	struct nand_ecc_ctrl *ecc = &chip->ecc;
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	if (chip->ecc.mode != NAND_ECC_HW) {
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	if (mtd->writesize / chip->ecc.size > FMC2_MAX_SG) {
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	if (chip->bbt_options & NAND_BBT_USE_FLASH)
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:		chip->bbt_options |= NAND_BBT_NO_OOB;
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	if (chip->options & NAND_BUSWIDTH_16)
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	chip->controller = &fmc2->base;
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	chip->options |= NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE |
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	chip->ecc.mode = NAND_ECC_HW;
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	chip->ecc.size = FMC2_ECC_STEP_SIZE;
+drivers/mtd/nand/raw/stm32_fmc2_nand.c:	chip->ecc.strength = FMC2_ECC_BCH8;
+drivers/mtd/nand/raw/tango_nand.c:/* Offsets relative to chip->base */
+drivers/mtd/nand/raw/tango_nand.c:		writeb_relaxed(dat, tchip->base + PBUS_CMD);
+drivers/mtd/nand/raw/tango_nand.c:		writeb_relaxed(dat, tchip->base + PBUS_ADDR);
+drivers/mtd/nand/raw/tango_nand.c:	struct tango_nfc *nfc = to_tango_nfc(chip->controller);
+drivers/mtd/nand/raw/tango_nand.c:	return readb_relaxed(tchip->base + PBUS_DATA);
+drivers/mtd/nand/raw/tango_nand.c:	ioread8_rep(tchip->base + PBUS_DATA, buf, len);
+drivers/mtd/nand/raw/tango_nand.c:	iowrite8_rep(tchip->base + PBUS_DATA, buf, len);
+drivers/mtd/nand/raw/tango_nand.c:	struct tango_nfc *nfc = to_tango_nfc(chip->controller);
+drivers/mtd/nand/raw/tango_nand.c:	writel_relaxed(tchip->timing1, nfc->reg_base + NFC_TIMING1);
+drivers/mtd/nand/raw/tango_nand.c:	writel_relaxed(tchip->timing2, nfc->reg_base + NFC_TIMING2);
+drivers/mtd/nand/raw/tango_nand.c:	writel_relaxed(tchip->xfer_cfg, nfc->reg_base + NFC_XFER_CFG);
+drivers/mtd/nand/raw/tango_nand.c:	writel_relaxed(tchip->pkt_0_cfg, nfc->reg_base + NFC_PKT_0_CFG);
+drivers/mtd/nand/raw/tango_nand.c:	writel_relaxed(tchip->pkt_n_cfg, nfc->reg_base + NFC_PKT_N_CFG);
+drivers/mtd/nand/raw/tango_nand.c:	writel_relaxed(tchip->bb_cfg, nfc->reg_base + NFC_BB_CFG);
+drivers/mtd/nand/raw/tango_nand.c:	u8 *meta = chip->oob_poi + BBM_SIZE;
+drivers/mtd/nand/raw/tango_nand.c:	u8 *ecc = chip->oob_poi + BBM_SIZE + METADATA_SIZE;
+drivers/mtd/nand/raw/tango_nand.c:	const int ecc_size = chip->ecc.bytes;
+drivers/mtd/nand/raw/tango_nand.c:	const int pkt_size = chip->ecc.size;
+drivers/mtd/nand/raw/tango_nand.c:	for (i = 0; i < chip->ecc.steps; ++i) {
+drivers/mtd/nand/raw/tango_nand.c:						  chip->ecc.strength);
+drivers/mtd/nand/raw/tango_nand.c:	struct tango_nfc *nfc = to_tango_nfc(chip->controller);
+drivers/mtd/nand/raw/tango_nand.c:	struct tango_nfc *nfc = to_tango_nfc(chip->controller);
+drivers/mtd/nand/raw/tango_nand.c:		chip->ecc.read_oob(chip, page);
+drivers/mtd/nand/raw/tango_nand.c:		chip->ecc.read_oob_raw(chip, page);
+drivers/mtd/nand/raw/tango_nand.c:	struct tango_nfc *nfc = to_tango_nfc(chip->controller);
+drivers/mtd/nand/raw/tango_nand.c:	status = chip->legacy.waitfunc(chip);
+drivers/mtd/nand/raw/tango_nand.c:	const int ecc_size = chip->ecc.bytes;
+drivers/mtd/nand/raw/tango_nand.c:	const int pkt_size = chip->ecc.size;
+drivers/mtd/nand/raw/tango_nand.c:	const int ecc_size = chip->ecc.bytes;
+drivers/mtd/nand/raw/tango_nand.c:	const int pkt_size = chip->ecc.size;
+drivers/mtd/nand/raw/tango_nand.c:	raw_read(chip, buf, chip->oob_poi);
+drivers/mtd/nand/raw/tango_nand.c:	raw_write(chip, buf, chip->oob_poi);
+drivers/mtd/nand/raw/tango_nand.c:	raw_read(chip, NULL, chip->oob_poi);
+drivers/mtd/nand/raw/tango_nand.c:	raw_write(chip, NULL, chip->oob_poi);
+drivers/mtd/nand/raw/tango_nand.c:	struct nand_ecc_ctrl *ecc = &chip->ecc;
+drivers/mtd/nand/raw/tango_nand.c:	struct tango_nfc *nfc = to_tango_nfc(chip->controller);
+drivers/mtd/nand/raw/tango_nand.c:	tchip->timing1 = TIMING(Trdy, Textw, Twc, Twpw);
+drivers/mtd/nand/raw/tango_nand.c:	tchip->timing2 = TIMING(Tacc, Thold, Trpw, Textr);
+drivers/mtd/nand/raw/tango_nand.c:	struct nand_ecc_ctrl *ecc = &chip->ecc;
+drivers/mtd/nand/raw/tango_nand.c:	chip = &tchip->nand_chip;
+drivers/mtd/nand/raw/tango_nand.c:	ecc = &chip->ecc;
+drivers/mtd/nand/raw/tango_nand.c:	chip->legacy.read_byte = tango_read_byte;
+drivers/mtd/nand/raw/tango_nand.c:	chip->legacy.write_buf = tango_write_buf;
+drivers/mtd/nand/raw/tango_nand.c:	chip->legacy.read_buf = tango_read_buf;
+drivers/mtd/nand/raw/tango_nand.c:	chip->legacy.select_chip = tango_select_chip;
+drivers/mtd/nand/raw/tango_nand.c:	chip->legacy.cmd_ctrl = tango_cmd_ctrl;
+drivers/mtd/nand/raw/tango_nand.c:	chip->legacy.dev_ready = tango_dev_ready;
+drivers/mtd/nand/raw/tango_nand.c:	chip->options = NAND_USE_BOUNCE_BUFFER |
+drivers/mtd/nand/raw/tango_nand.c:	chip->controller = &nfc->hw;
+drivers/mtd/nand/raw/tango_nand.c:	tchip->base = nfc->pbus_base + (cs * 256);
+drivers/mtd/nand/raw/tango_nand.c:	tchip->xfer_cfg = XFER_CFG(cs, 1, ecc->steps, METADATA_SIZE);
+drivers/mtd/nand/raw/tango_nand.c:	tchip->pkt_0_cfg = PKT_CFG(ecc->size + METADATA_SIZE, ecc->strength);
+drivers/mtd/nand/raw/tango_nand.c:	tchip->pkt_n_cfg = PKT_CFG(ecc->size, ecc->strength);
+drivers/mtd/nand/raw/tango_nand.c:	tchip->bb_cfg = BB_CFG(mtd->writesize, BBM_SIZE);
+drivers/mtd/nand/raw/tegra_nand.c:	int bytes_per_step = DIV_ROUND_UP(BITS_PER_STEP_RS * chip->ecc.strength,
+drivers/mtd/nand/raw/tegra_nand.c:	oobregion->length = round_up(bytes_per_step * chip->ecc.steps, 4);
+drivers/mtd/nand/raw/tegra_nand.c:	int bytes_per_step = DIV_ROUND_UP(BITS_PER_STEP_BCH * chip->ecc.strength,
+drivers/mtd/nand/raw/tegra_nand.c:	oobregion->length = round_up(bytes_per_step * chip->ecc.steps, 4);
+drivers/mtd/nand/raw/tegra_nand.c:	struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
+drivers/mtd/nand/raw/tegra_nand.c:	struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
+drivers/mtd/nand/raw/tegra_nand.c:	if (chip->ecc.algo == NAND_ECC_BCH && enable)
+drivers/mtd/nand/raw/tegra_nand.c:	struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
+drivers/mtd/nand/raw/tegra_nand.c:	tegra_nand_select_target(chip, chip->cur_cs);
+drivers/mtd/nand/raw/tegra_nand.c:	if (chip->options & NAND_ROW_ADDR_3) {
+drivers/mtd/nand/raw/tegra_nand.c:	void *oob_buf = oob_required ? chip->oob_poi : NULL;
+drivers/mtd/nand/raw/tegra_nand.c:	void *oob_buf = oob_required ? chip->oob_poi : NULL;
+drivers/mtd/nand/raw/tegra_nand.c:	return tegra_nand_page_xfer(mtd, chip, NULL, chip->oob_poi,
+drivers/mtd/nand/raw/tegra_nand.c:	return tegra_nand_page_xfer(mtd, chip, NULL, chip->oob_poi,
+drivers/mtd/nand/raw/tegra_nand.c:	struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
+drivers/mtd/nand/raw/tegra_nand.c:	void *oob_buf = oob_required ? chip->oob_poi : NULL;
+drivers/mtd/nand/raw/tegra_nand.c:		if (fail_sec_flag ^ GENMASK(chip->ecc.steps - 1, 0)) {
+drivers/mtd/nand/raw/tegra_nand.c:		for_each_set_bit(bit, &fail_sec_flag, chip->ecc.steps) {
+drivers/mtd/nand/raw/tegra_nand.c:			u8 *data = buf + (chip->ecc.size * bit);
+drivers/mtd/nand/raw/tegra_nand.c:			u8 *oob = chip->oob_poi + nand->ecc.offset +
+drivers/mtd/nand/raw/tegra_nand.c:				  (chip->ecc.bytes * bit);
+drivers/mtd/nand/raw/tegra_nand.c:			ret = nand_check_erased_ecc_chunk(data, chip->ecc.size,
+drivers/mtd/nand/raw/tegra_nand.c:							  oob, chip->ecc.bytes,
+drivers/mtd/nand/raw/tegra_nand.c:							  chip->ecc.strength);
+drivers/mtd/nand/raw/tegra_nand.c:	struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
+drivers/mtd/nand/raw/tegra_nand.c:	void *oob_buf = oob_required ? chip->oob_poi : NULL;
+drivers/mtd/nand/raw/tegra_nand.c:	struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
+drivers/mtd/nand/raw/tegra_nand.c:	bool maximize = chip->ecc.options & NAND_ECC_MAXIMIZE;
+drivers/mtd/nand/raw/tegra_nand.c:			if (strength_sel < chip->base.eccreq.strength)
+drivers/mtd/nand/raw/tegra_nand.c:		bytes_per_page = round_up(bytes_per_step * chip->ecc.steps, 4);
+drivers/mtd/nand/raw/tegra_nand.c:	switch (chip->ecc.algo) {
+drivers/mtd/nand/raw/tegra_nand.c:		if (chip->options & NAND_IS_BOOT_MEDIUM) {
+drivers/mtd/nand/raw/tegra_nand.c:		if (chip->options & NAND_IS_BOOT_MEDIUM) {
+drivers/mtd/nand/raw/tegra_nand.c:	struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
+drivers/mtd/nand/raw/tegra_nand.c:	if (chip->bbt_options & NAND_BBT_USE_FLASH)
+drivers/mtd/nand/raw/tegra_nand.c:		chip->bbt_options |= NAND_BBT_NO_OOB;
+drivers/mtd/nand/raw/tegra_nand.c:	chip->ecc.mode = NAND_ECC_HW;
+drivers/mtd/nand/raw/tegra_nand.c:	chip->ecc.size = 512;
+drivers/mtd/nand/raw/tegra_nand.c:	chip->ecc.steps = mtd->writesize / chip->ecc.size;
+drivers/mtd/nand/raw/tegra_nand.c:	if (chip->base.eccreq.step_size != 512) {
+drivers/mtd/nand/raw/tegra_nand.c:			chip->base.eccreq.step_size);
+drivers/mtd/nand/raw/tegra_nand.c:	chip->ecc.read_page = tegra_nand_read_page_hwecc;
+drivers/mtd/nand/raw/tegra_nand.c:	chip->ecc.write_page = tegra_nand_write_page_hwecc;
+drivers/mtd/nand/raw/tegra_nand.c:	chip->ecc.read_page_raw = tegra_nand_read_page_raw;
+drivers/mtd/nand/raw/tegra_nand.c:	chip->ecc.write_page_raw = tegra_nand_write_page_raw;
+drivers/mtd/nand/raw/tegra_nand.c:	chip->ecc.read_oob = tegra_nand_read_oob;
+drivers/mtd/nand/raw/tegra_nand.c:	chip->ecc.write_oob = tegra_nand_write_oob;
+drivers/mtd/nand/raw/tegra_nand.c:	if (chip->options & NAND_BUSWIDTH_16)
+drivers/mtd/nand/raw/tegra_nand.c:	if (chip->ecc.algo == NAND_ECC_UNKNOWN) {
+drivers/mtd/nand/raw/tegra_nand.c:			chip->ecc.algo = NAND_ECC_RS;
+drivers/mtd/nand/raw/tegra_nand.c:			chip->ecc.algo = NAND_ECC_BCH;
+drivers/mtd/nand/raw/tegra_nand.c:	if (chip->ecc.algo == NAND_ECC_BCH && mtd->writesize < 2048) {
+drivers/mtd/nand/raw/tegra_nand.c:	if (!chip->ecc.strength) {
+drivers/mtd/nand/raw/tegra_nand.c:				chip->base.eccreq.strength);
+drivers/mtd/nand/raw/tegra_nand.c:		chip->ecc.strength = ret;
+drivers/mtd/nand/raw/tegra_nand.c:	switch (chip->ecc.algo) {
+drivers/mtd/nand/raw/tegra_nand.c:		bits_per_step = BITS_PER_STEP_RS * chip->ecc.strength;
+drivers/mtd/nand/raw/tegra_nand.c:		switch (chip->ecc.strength) {
+drivers/mtd/nand/raw/tegra_nand.c:				chip->ecc.strength);
+drivers/mtd/nand/raw/tegra_nand.c:		bits_per_step = BITS_PER_STEP_BCH * chip->ecc.strength;
+drivers/mtd/nand/raw/tegra_nand.c:		switch (chip->ecc.strength) {
+drivers/mtd/nand/raw/tegra_nand.c:				chip->ecc.strength);
+drivers/mtd/nand/raw/tegra_nand.c:		 chip->ecc.algo == NAND_ECC_BCH ? "BCH" : "RS",
+drivers/mtd/nand/raw/tegra_nand.c:		 chip->ecc.strength);
+drivers/mtd/nand/raw/tegra_nand.c:	chip->ecc.bytes = DIV_ROUND_UP(bits_per_step, BITS_PER_BYTE);
+drivers/mtd/nand/raw/tegra_nand.c:	chip->controller = &ctrl->controller;
+drivers/mtd/nand/raw/tegra_nand.c:	chip->options = NAND_NO_SUBPAGE_WRITE | NAND_USE_BOUNCE_BUFFER;
+drivers/mtd/nand/raw/tmio_nand.c:		tmio_iowrite8(cmd, chip->legacy.IO_ADDR_W);
+drivers/mtd/nand/raw/tmio_nand.c:	nand_chip->legacy.IO_ADDR_R = tmio->fcr;
+drivers/mtd/nand/raw/tmio_nand.c:	nand_chip->legacy.IO_ADDR_W = tmio->fcr;
+drivers/mtd/nand/raw/tmio_nand.c:	nand_chip->legacy.cmd_ctrl = tmio_nand_hwcontrol;
+drivers/mtd/nand/raw/tmio_nand.c:	nand_chip->legacy.dev_ready = tmio_nand_dev_ready;
+drivers/mtd/nand/raw/tmio_nand.c:	nand_chip->legacy.read_byte = tmio_nand_read_byte;
+drivers/mtd/nand/raw/tmio_nand.c:	nand_chip->legacy.write_buf = tmio_nand_write_buf;
+drivers/mtd/nand/raw/tmio_nand.c:	nand_chip->legacy.read_buf = tmio_nand_read_buf;
+drivers/mtd/nand/raw/tmio_nand.c:	nand_chip->ecc.mode = NAND_ECC_HW;
+drivers/mtd/nand/raw/tmio_nand.c:	nand_chip->ecc.size = 512;
+drivers/mtd/nand/raw/tmio_nand.c:	nand_chip->ecc.bytes = 6;
+drivers/mtd/nand/raw/tmio_nand.c:	nand_chip->ecc.strength = 2;
+drivers/mtd/nand/raw/tmio_nand.c:	nand_chip->ecc.hwctl = tmio_nand_enable_hwecc;
+drivers/mtd/nand/raw/tmio_nand.c:	nand_chip->ecc.calculate = tmio_nand_calculate_ecc;
+drivers/mtd/nand/raw/tmio_nand.c:	nand_chip->ecc.correct = tmio_nand_correct_data;
+drivers/mtd/nand/raw/tmio_nand.c:		nand_chip->badblock_pattern = data->badblock_pattern;
+drivers/mtd/nand/raw/tmio_nand.c:	nand_chip->legacy.chip_delay = 15;
+drivers/mtd/nand/raw/tmio_nand.c:	nand_chip->legacy.waitfunc = tmio_nand_wait;
+drivers/mtd/nand/raw/txx9ndfmc.c:	for (eccbytes = chip->ecc.bytes; eccbytes > 0; eccbytes -= 3) {
+drivers/mtd/nand/raw/txx9ndfmc.c:	for (eccsize = chip->ecc.size; eccsize > 0; eccsize -= 256) {
+drivers/mtd/nand/raw/txx9ndfmc.c:		chip->ecc.size = 512;
+drivers/mtd/nand/raw/txx9ndfmc.c:		chip->ecc.bytes = 6;
+drivers/mtd/nand/raw/txx9ndfmc.c:		chip->ecc.size = 256;
+drivers/mtd/nand/raw/txx9ndfmc.c:		chip->ecc.bytes = 3;
+drivers/mtd/nand/raw/txx9ndfmc.c:		chip->legacy.read_byte = txx9ndfmc_read_byte;
+drivers/mtd/nand/raw/txx9ndfmc.c:		chip->legacy.read_buf = txx9ndfmc_read_buf;
+drivers/mtd/nand/raw/txx9ndfmc.c:		chip->legacy.write_buf = txx9ndfmc_write_buf;
+drivers/mtd/nand/raw/txx9ndfmc.c:		chip->legacy.cmd_ctrl = txx9ndfmc_cmd_ctrl;
+drivers/mtd/nand/raw/txx9ndfmc.c:		chip->legacy.dev_ready = txx9ndfmc_dev_ready;
+drivers/mtd/nand/raw/txx9ndfmc.c:		chip->ecc.calculate = txx9ndfmc_calculate_ecc;
+drivers/mtd/nand/raw/txx9ndfmc.c:		chip->ecc.correct = txx9ndfmc_correct_data;
+drivers/mtd/nand/raw/txx9ndfmc.c:		chip->ecc.hwctl = txx9ndfmc_enable_hwecc;
+drivers/mtd/nand/raw/txx9ndfmc.c:		chip->ecc.mode = NAND_ECC_HW;
+drivers/mtd/nand/raw/txx9ndfmc.c:		chip->ecc.strength = 1;
+drivers/mtd/nand/raw/txx9ndfmc.c:		chip->legacy.chip_delay = 100;
+drivers/mtd/nand/raw/txx9ndfmc.c:		chip->controller = &drvdata->controller;
+drivers/mtd/nand/raw/txx9ndfmc.c:			chip->options |= NAND_BUSWIDTH_16;
+drivers/mtd/nand/raw/vf610_nfc.c:	if (force8bit && (chip->options & NAND_BUSWIDTH_16))
+drivers/mtd/nand/raw/vf610_nfc.c:	if (force8bit && (chip->options & NAND_BUSWIDTH_16))
+drivers/mtd/nand/raw/vf610_nfc.c:	if (chip->options & NAND_ROW_ADDR_3) {
+drivers/mtd/nand/raw/vf610_nfc.c:	vf610_nfc_select_target(chip, chip->cur_cs);
+drivers/mtd/nand/raw/vf610_nfc.c:		vf610_nfc_rd_from_sram(chip->oob_poi,
+drivers/mtd/nand/raw/vf610_nfc.c:	stat = vf610_nfc_correct_data(chip, buf, chip->oob_poi, page);
+drivers/mtd/nand/raw/vf610_nfc.c:	vf610_nfc_select_target(chip, chip->cur_cs);
+drivers/mtd/nand/raw/vf610_nfc.c:		ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize,
+drivers/mtd/nand/raw/vf610_nfc.c:				      chip->oob_poi, mtd->oobsize);
+drivers/mtd/nand/raw/vf610_nfc.c:	if (chip->bbt_options & NAND_BBT_USE_FLASH)
+drivers/mtd/nand/raw/vf610_nfc.c:		chip->bbt_options |= NAND_BBT_NO_OOB;
+drivers/mtd/nand/raw/vf610_nfc.c:	if (chip->ecc.mode != NAND_ECC_HW)
+drivers/mtd/nand/raw/vf610_nfc.c:	if (chip->ecc.size != mtd->writesize) {
+drivers/mtd/nand/raw/vf610_nfc.c:	if (chip->ecc.strength == 32) {
+drivers/mtd/nand/raw/vf610_nfc.c:		chip->ecc.bytes = 60;
+drivers/mtd/nand/raw/vf610_nfc.c:	} else if (chip->ecc.strength == 24) {
+drivers/mtd/nand/raw/vf610_nfc.c:		chip->ecc.bytes = 45;
+drivers/mtd/nand/raw/vf610_nfc.c:	chip->ecc.read_page = vf610_nfc_read_page;
+drivers/mtd/nand/raw/vf610_nfc.c:	chip->ecc.write_page = vf610_nfc_write_page;
+drivers/mtd/nand/raw/vf610_nfc.c:	chip->ecc.read_page_raw = vf610_nfc_read_page_raw;
+drivers/mtd/nand/raw/vf610_nfc.c:	chip->ecc.write_page_raw = vf610_nfc_write_page_raw;
+drivers/mtd/nand/raw/vf610_nfc.c:	chip->ecc.read_oob = vf610_nfc_read_oob;
+drivers/mtd/nand/raw/vf610_nfc.c:	chip->ecc.write_oob = vf610_nfc_write_oob;
+drivers/mtd/nand/raw/vf610_nfc.c:	chip->ecc.size = PAGE_2K;
+drivers/mtd/nand/raw/vf610_nfc.c:	chip->options |= NAND_NO_SUBPAGE_WRITE;
+drivers/mtd/nand/raw/vf610_nfc.c:	chip->controller = &nfc->base;
+drivers/mtd/spi-nor/aspeed-smc.c:	return BIT(chip->controller->info->we0 + chip->cs);
+drivers/mtd/spi-nor/aspeed-smc.c:	struct aspeed_smc_controller *controller = chip->controller;
+drivers/mtd/spi-nor/aspeed-smc.c:	u32 ctl = chip->ctl_val[smc_base];
+drivers/mtd/spi-nor/aspeed-smc.c:	writel(ctl, chip->ctl);
+drivers/mtd/spi-nor/aspeed-smc.c:	writel(ctl, chip->ctl);
+drivers/mtd/spi-nor/aspeed-smc.c:	u32 ctl = chip->ctl_val[smc_read];
+drivers/mtd/spi-nor/aspeed-smc.c:	writel(ctl2, chip->ctl);	/* stop user CE control */
+drivers/mtd/spi-nor/aspeed-smc.c:	writel(ctl, chip->ctl);		/* default to fread or read mode */
+drivers/mtd/spi-nor/aspeed-smc.c:	mutex_lock(&chip->controller->mutex);
+drivers/mtd/spi-nor/aspeed-smc.c:	mutex_unlock(&chip->controller->mutex);
+drivers/mtd/spi-nor/aspeed-smc.c:	aspeed_smc_write_to_ahb(chip->ahb_base, &opcode, 1);
+drivers/mtd/spi-nor/aspeed-smc.c:	aspeed_smc_read_from_ahb(buf, chip->ahb_base, len);
+drivers/mtd/spi-nor/aspeed-smc.c:	aspeed_smc_write_to_ahb(chip->ahb_base, &opcode, 1);
+drivers/mtd/spi-nor/aspeed-smc.c:	aspeed_smc_write_to_ahb(chip->ahb_base, buf, len);
+drivers/mtd/spi-nor/aspeed-smc.c:		aspeed_smc_write_to_ahb(chip->ahb_base, &temp, 4);
+drivers/mtd/spi-nor/aspeed-smc.c:		aspeed_smc_write_to_ahb(chip->ahb_base, &cmd, 1);
+drivers/mtd/spi-nor/aspeed-smc.c:		aspeed_smc_write_to_ahb(chip->ahb_base, &temp, 4);
+drivers/mtd/spi-nor/aspeed-smc.c:	for (i = 0; i < chip->nor.read_dummy / 8; i++)
+drivers/mtd/spi-nor/aspeed-smc.c:		aspeed_smc_write_to_ahb(chip->ahb_base, &dummy, sizeof(dummy));
+drivers/mtd/spi-nor/aspeed-smc.c:	aspeed_smc_read_from_ahb(read_buf, chip->ahb_base, len);
+drivers/mtd/spi-nor/aspeed-smc.c:	aspeed_smc_write_to_ahb(chip->ahb_base, write_buf, len);
+drivers/mtd/spi-nor/aspeed-smc.c:			mtd_device_unregister(&chip->nor.mtd);
+drivers/mtd/spi-nor/aspeed-smc.c:	struct aspeed_smc_controller *controller = chip->controller;
+drivers/mtd/spi-nor/aspeed-smc.c:		reg = readl(SEGMENT_ADDR_REG(controller, chip->cs));
+drivers/mtd/spi-nor/aspeed-smc.c:	struct aspeed_smc_controller *controller = chip->controller;
+drivers/mtd/spi-nor/aspeed-smc.c:		dev_warn(chip->nor.dev, "CE%d window resized to %dMB",
+drivers/mtd/spi-nor/aspeed-smc.c:		dev_err(chip->nor.dev, "CE%d window invalid", cs);
+drivers/mtd/spi-nor/aspeed-smc.c:	dev_info(chip->nor.dev, "CE%d window [ 0x%.8x - 0x%.8x ] %dMB",
+drivers/mtd/spi-nor/aspeed-smc.c:	struct aspeed_smc_controller *controller = chip->controller;
+drivers/mtd/spi-nor/aspeed-smc.c:	u32 size = chip->nor.mtd.size;
+drivers/mtd/spi-nor/aspeed-smc.c:	if (chip->cs == 0 && controller->info == &spi_2500_info &&
+drivers/mtd/spi-nor/aspeed-smc.c:		dev_info(chip->nor.dev,
+drivers/mtd/spi-nor/aspeed-smc.c:			 chip->cs, size >> 20);
+drivers/mtd/spi-nor/aspeed-smc.c:	if (chip->cs) {
+drivers/mtd/spi-nor/aspeed-smc.c:		u32 prev = readl(SEGMENT_ADDR_REG(controller, chip->cs - 1));
+drivers/mtd/spi-nor/aspeed-smc.c:	size = chip_set_segment(chip, chip->cs, start, size);
+drivers/mtd/spi-nor/aspeed-smc.c:	chip->ahb_base = controller->ahb_base + (start - ahb_base_phy);
+drivers/mtd/spi-nor/aspeed-smc.c:	if (chip->cs < controller->info->nce - 1)
+drivers/mtd/spi-nor/aspeed-smc.c:		chip_set_segment(chip, chip->cs + 1, start + size, 0);
+drivers/mtd/spi-nor/aspeed-smc.c:	if (size < chip->nor.mtd.size)
+drivers/mtd/spi-nor/aspeed-smc.c:		dev_warn(chip->nor.dev,
+drivers/mtd/spi-nor/aspeed-smc.c:			 chip->cs, (u32)chip->nor.mtd.size >> 20);
+drivers/mtd/spi-nor/aspeed-smc.c:	struct aspeed_smc_controller *controller = chip->controller;
+drivers/mtd/spi-nor/aspeed-smc.c:	struct aspeed_smc_controller *controller = chip->controller;
+drivers/mtd/spi-nor/aspeed-smc.c:	chip->type = type;
+drivers/mtd/spi-nor/aspeed-smc.c:	reg &= ~(3 << (chip->cs * 2));
+drivers/mtd/spi-nor/aspeed-smc.c:	reg |= chip->type << (chip->cs * 2);
+drivers/mtd/spi-nor/aspeed-smc.c:	struct aspeed_smc_controller *controller = chip->controller;
+drivers/mtd/spi-nor/aspeed-smc.c:	reg |= 1 << chip->cs;
+drivers/mtd/spi-nor/aspeed-smc.c:	chip->ctl_val[smc_base] |= CONTROL_IO_ADDRESS_4B;
+drivers/mtd/spi-nor/aspeed-smc.c:	chip->ctl_val[smc_read] |= CONTROL_IO_ADDRESS_4B;
+drivers/mtd/spi-nor/aspeed-smc.c:	struct aspeed_smc_controller *controller = chip->controller;
+drivers/mtd/spi-nor/aspeed-smc.c:	chip->ahb_base = aspeed_smc_chip_base(chip, res);
+drivers/mtd/spi-nor/aspeed-smc.c:	if (!chip->ahb_base) {
+drivers/mtd/spi-nor/aspeed-smc.c:		dev_warn(chip->nor.dev, "CE%d window closed", chip->cs);
+drivers/mtd/spi-nor/aspeed-smc.c:	reg = readl(chip->ctl);
+drivers/mtd/spi-nor/aspeed-smc.c:	chip->ctl_val[smc_base] = base_reg;
+drivers/mtd/spi-nor/aspeed-smc.c:		chip->ctl_val[smc_read] = reg;
+drivers/mtd/spi-nor/aspeed-smc.c:		chip->ctl_val[smc_read] = chip->ctl_val[smc_base] |
+drivers/mtd/spi-nor/aspeed-smc.c:		chip->ctl_val[smc_read]);
+drivers/mtd/spi-nor/aspeed-smc.c:	struct aspeed_smc_controller *controller = chip->controller;
+drivers/mtd/spi-nor/aspeed-smc.c:	if (chip->nor.addr_width == 4 && info->set_4b)
+drivers/mtd/spi-nor/aspeed-smc.c:	chip->ahb_window_size = aspeed_smc_chip_set_segment(chip);
+drivers/mtd/spi-nor/aspeed-smc.c:	chip->ctl_val[smc_write] = chip->ctl_val[smc_base] |
+drivers/mtd/spi-nor/aspeed-smc.c:		chip->nor.program_opcode << CONTROL_COMMAND_SHIFT |
+drivers/mtd/spi-nor/aspeed-smc.c:		chip->ctl_val[smc_write]);
+drivers/mtd/spi-nor/aspeed-smc.c:	if (chip->nor.read_proto == SNOR_PROTO_1_1_1) {
+drivers/mtd/spi-nor/aspeed-smc.c:		if (chip->nor.read_dummy == 0)
+drivers/mtd/spi-nor/aspeed-smc.c:		dev_err(chip->nor.dev, "unsupported SPI read mode\n");
+drivers/mtd/spi-nor/aspeed-smc.c:	chip->ctl_val[smc_read] |= cmd |
+drivers/mtd/spi-nor/aspeed-smc.c:		CONTROL_IO_DUMMY_SET(chip->nor.read_dummy / 8);
+drivers/mtd/spi-nor/aspeed-smc.c:		chip->ctl_val[smc_read]);
+drivers/mtd/spi-nor/aspeed-smc.c:		chip->controller = controller;
+drivers/mtd/spi-nor/aspeed-smc.c:		chip->ctl = controller->regs + info->ctl0 + cs * 4;
+drivers/mtd/spi-nor/aspeed-smc.c:		chip->cs = cs;
+drivers/mtd/spi-nor/aspeed-smc.c:		nor = &chip->nor;
+drivers/mux/adg792a.c:	struct i2c_client *i2c = to_i2c_client(mux->chip->dev.parent);
+drivers/mux/adg792a.c:	if (mux->chip->controllers == 1) {
+drivers/mux/adg792a.c:	mux_chip->ops = &adg792a_ops;
+drivers/mux/adg792a.c:					     mux_chip->controllers);
+drivers/mux/adg792a.c:	for (i = 0; i < mux_chip->controllers; ++i) {
+drivers/mux/adg792a.c:		struct mux_control *mux = &mux_chip->mux[i];
+drivers/mux/adgs1408.c:	struct spi_device *spi = to_spi_device(mux->chip->dev.parent);
+drivers/mux/adgs1408.c:	mux_chip->ops = &adgs1408_ops;
+drivers/mux/adgs1408.c:	mux = mux_chip->mux;
+drivers/mux/core.c:	ida_simple_remove(&mux_ida, mux_chip->id);
+drivers/mux/core.c: * the number of valid mux states in the mux_chip->mux[N].states members and
+drivers/mux/core.c: * the desired idle state in the returned mux_chip->mux[N].idle_state members.
+drivers/mux/core.c: * provide a pointer to the operations struct in the mux_chip->ops member
+drivers/mux/core.c:			   controllers * sizeof(*mux_chip->mux) +
+drivers/mux/core.c:	mux_chip->mux = (struct mux_control *)(mux_chip + 1);
+drivers/mux/core.c:	mux_chip->dev.class = &mux_class;
+drivers/mux/core.c:	mux_chip->dev.type = &mux_type;
+drivers/mux/core.c:	mux_chip->dev.parent = dev;
+drivers/mux/core.c:	mux_chip->dev.of_node = dev->of_node;
+drivers/mux/core.c:	dev_set_drvdata(&mux_chip->dev, mux_chip);
+drivers/mux/core.c:	mux_chip->id = ida_simple_get(&mux_ida, 0, 0, GFP_KERNEL);
+drivers/mux/core.c:	if (mux_chip->id < 0) {
+drivers/mux/core.c:		int err = mux_chip->id;
+drivers/mux/core.c:	dev_set_name(&mux_chip->dev, "muxchip%d", mux_chip->id);
+drivers/mux/core.c:	mux_chip->controllers = controllers;
+drivers/mux/core.c:		struct mux_control *mux = &mux_chip->mux[i];
+drivers/mux/core.c:	device_initialize(&mux_chip->dev);
+drivers/mux/core.c:	int ret = mux->chip->ops->set(mux, state);
+drivers/mux/core.c:	for (i = 0; i < mux_chip->controllers; ++i) {
+drivers/mux/core.c:		struct mux_control *mux = &mux_chip->mux[i];
+drivers/mux/core.c:			dev_err(&mux_chip->dev, "unable to set idle state\n");
+drivers/mux/core.c:	ret = device_add(&mux_chip->dev);
+drivers/mux/core.c:		dev_err(&mux_chip->dev,
+drivers/mux/core.c:	device_del(&mux_chip->dev);
+drivers/mux/core.c:	put_device(&mux_chip->dev);
+drivers/mux/core.c:	    (!args.args_count && (mux_chip->controllers > 1))) {
+drivers/mux/core.c:		put_device(&mux_chip->dev);
+drivers/mux/core.c:	if (controller >= mux_chip->controllers) {
+drivers/mux/core.c:		put_device(&mux_chip->dev);
+drivers/mux/core.c:	return &mux_chip->mux[controller];
+drivers/mux/core.c:	put_device(&mux->chip->dev);
+drivers/mux/gpio.c:	mux_chip->ops = &mux_gpio_ops;
+drivers/mux/gpio.c:	mux_chip->mux->states = 1 << pins;
+drivers/mux/gpio.c:		if (idle_state < 0 || idle_state >= mux_chip->mux->states) {
+drivers/mux/gpio.c:		mux_chip->mux->idle_state = idle_state;
+drivers/mux/gpio.c:		 mux_chip->mux->states);
+drivers/mux/mmio.c:		struct mux_control *mux = &mux_chip->mux[i];
+drivers/mux/mmio.c:	mux_chip->ops = &mux_mmio_ops;
+drivers/net/dsa/b53/b53_common.c:		if (chip->chip_id == dev->chip_id) {
+drivers/net/dsa/b53/b53_common.c:				dev->enabled_ports = chip->enabled_ports;
+drivers/net/dsa/b53/b53_common.c:			dev->name = chip->dev_name;
+drivers/net/dsa/b53/b53_common.c:			dev->duplex_reg = chip->duplex_reg;
+drivers/net/dsa/b53/b53_common.c:			dev->vta_regs[0] = chip->vta_regs[0];
+drivers/net/dsa/b53/b53_common.c:			dev->vta_regs[1] = chip->vta_regs[1];
+drivers/net/dsa/b53/b53_common.c:			dev->vta_regs[2] = chip->vta_regs[2];
+drivers/net/dsa/b53/b53_common.c:			dev->jumbo_pm_reg = chip->jumbo_pm_reg;
+drivers/net/dsa/b53/b53_common.c:			dev->cpu_port = chip->cpu_port;
+drivers/net/dsa/b53/b53_common.c:			dev->num_vlans = chip->vlans;
+drivers/net/dsa/b53/b53_common.c:			dev->num_arl_entries = chip->arl_entries;
+drivers/net/dsa/lan9303-core.c:		ret = lan9303_read(chip->regmap, offset, &reg);
+drivers/net/dsa/lan9303-core.c:			dev_err(chip->dev, "%s failed to read offset %d: %d\n",
+drivers/net/dsa/lan9303-core.c:	ret = lan9303_read(chip->regmap, LAN9303_VIRT_PHY_BASE + regnum, &val);
+drivers/net/dsa/lan9303-core.c:	return regmap_write(chip->regmap, LAN9303_VIRT_PHY_BASE + regnum, val);
+drivers/net/dsa/lan9303-core.c:	mutex_lock(&chip->indirect_mutex);
+drivers/net/dsa/lan9303-core.c:	ret = regmap_write(chip->regmap, LAN9303_PMI_ACCESS, val);
+drivers/net/dsa/lan9303-core.c:	ret = lan9303_read(chip->regmap, LAN9303_PMI_DATA, &val);
+drivers/net/dsa/lan9303-core.c:	mutex_unlock(&chip->indirect_mutex);
+drivers/net/dsa/lan9303-core.c:	mutex_unlock(&chip->indirect_mutex);
+drivers/net/dsa/lan9303-core.c:	mutex_lock(&chip->indirect_mutex);
+drivers/net/dsa/lan9303-core.c:	ret = regmap_write(chip->regmap, LAN9303_PMI_DATA, val);
+drivers/net/dsa/lan9303-core.c:	ret = regmap_write(chip->regmap, LAN9303_PMI_ACCESS, reg);
+drivers/net/dsa/lan9303-core.c:	mutex_unlock(&chip->indirect_mutex);
+drivers/net/dsa/lan9303-core.c:	mutex_lock(&chip->indirect_mutex);
+drivers/net/dsa/lan9303-core.c:	ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_DATA, val);
+drivers/net/dsa/lan9303-core.c:		dev_err(chip->dev, "Failed to write csr data reg: %d\n", ret);
+drivers/net/dsa/lan9303-core.c:	ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_CMD, reg);
+drivers/net/dsa/lan9303-core.c:		dev_err(chip->dev, "Failed to write csr command reg: %d\n",
+drivers/net/dsa/lan9303-core.c:	mutex_unlock(&chip->indirect_mutex);
+drivers/net/dsa/lan9303-core.c:	mutex_lock(&chip->indirect_mutex);
+drivers/net/dsa/lan9303-core.c:	ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_CMD, reg);
+drivers/net/dsa/lan9303-core.c:		dev_err(chip->dev, "Failed to write csr command reg: %d\n",
+drivers/net/dsa/lan9303-core.c:	ret = lan9303_read(chip->regmap, LAN9303_SWITCH_CSR_DATA, val);
+drivers/net/dsa/lan9303-core.c:		dev_err(chip->dev, "Failed to read csr data reg: %d\n", ret);
+drivers/net/dsa/lan9303-core.c:	mutex_unlock(&chip->indirect_mutex);
+drivers/net/dsa/lan9303-core.c:	/* Calculate chip->phy_addr_base:
+drivers/net/dsa/lan9303-core.c:	reg = chip->ops->phy_read(chip, 3, MII_LAN911X_SPECIAL_MODES);
+drivers/net/dsa/lan9303-core.c:		dev_err(chip->dev, "Failed to detect phy config: %d\n", reg);
+drivers/net/dsa/lan9303-core.c:	chip->phy_addr_base = reg != 0 && reg != 0xffff;
+drivers/net/dsa/lan9303-core.c:	dev_dbg(chip->dev, "Phy setup '%s' detected\n",
+drivers/net/dsa/lan9303-core.c:		chip->phy_addr_base ? "1-2-3" : "0-1-2");
+drivers/net/dsa/lan9303-core.c:	struct lan9303_alr_cache_entry *entr = chip->alr_cache;
+drivers/net/dsa/lan9303-core.c:	struct lan9303_alr_cache_entry *entr = chip->alr_cache;
+drivers/net/dsa/lan9303-core.c:	mutex_lock(&chip->alr_mutex);
+drivers/net/dsa/lan9303-core.c:	mutex_unlock(&chip->alr_mutex);
+drivers/net/dsa/lan9303-core.c:	dev_dbg(chip->dev, "%s(%pM, %d)\n", __func__, mac, port_map);
+drivers/net/dsa/lan9303-core.c:	mutex_lock(&chip->alr_mutex);
+drivers/net/dsa/lan9303-core.c:			mutex_unlock(&chip->alr_mutex);
+drivers/net/dsa/lan9303-core.c:	mutex_unlock(&chip->alr_mutex);
+drivers/net/dsa/lan9303-core.c:	mutex_lock(&chip->alr_mutex);
+drivers/net/dsa/lan9303-core.c:	mutex_unlock(&chip->alr_mutex);
+drivers/net/dsa/lan9303-core.c:				 chip->swe_port_state);
+drivers/net/dsa/lan9303-core.c:	if (!chip->reset_gpio)
+drivers/net/dsa/lan9303-core.c:	if (chip->reset_duration != 0)
+drivers/net/dsa/lan9303-core.c:		msleep(chip->reset_duration);
+drivers/net/dsa/lan9303-core.c:	gpiod_set_value_cansleep(chip->reset_gpio, 0);
+drivers/net/dsa/lan9303-core.c:	ret = lan9303_read(chip->regmap, LAN9303_CHIP_REV, &reg);
+drivers/net/dsa/lan9303-core.c:		dev_err(chip->dev, "failed to read chip revision register: %d\n",
+drivers/net/dsa/lan9303-core.c:		if (!chip->reset_gpio) {
+drivers/net/dsa/lan9303-core.c:			dev_dbg(chip->dev,
+drivers/net/dsa/lan9303-core.c:		dev_err(chip->dev, "expecting LAN9303 chip, but found: %X\n",
+drivers/net/dsa/lan9303-core.c:		dev_warn(chip->dev, "failed to disable switching %d\n", ret);
+drivers/net/dsa/lan9303-core.c:	dev_info(chip->dev, "Found LAN9303 rev. %u\n", reg & 0xffff);
+drivers/net/dsa/lan9303-core.c:		dev_err(chip->dev,
+drivers/net/dsa/lan9303-core.c:		dev_err(chip->dev, "port 0 is not the CPU port\n");
+drivers/net/dsa/lan9303-core.c:		dev_err(chip->dev, "failed to setup port tagging %d\n", ret);
+drivers/net/dsa/lan9303-core.c:		dev_err(chip->dev, "failed to separate ports %d\n", ret);
+drivers/net/dsa/lan9303-core.c:		dev_err(chip->dev, "failed to re-enable switching %d\n", ret);
+drivers/net/dsa/lan9303-core.c:		dev_err(chip->dev, "failed to setup IGMP trap %d\n", ret);
+drivers/net/dsa/lan9303-core.c:			dev_warn(chip->dev, "Reading status port %d reg %u failed\n",
+drivers/net/dsa/lan9303-core.c:	int phy_base = chip->phy_addr_base;
+drivers/net/dsa/lan9303-core.c:	return chip->ops->phy_read(chip, phy, regnum);
+drivers/net/dsa/lan9303-core.c:	int phy_base = chip->phy_addr_base;
+drivers/net/dsa/lan9303-core.c:	return chip->ops->phy_write(chip, phy, regnum, val);
+drivers/net/dsa/lan9303-core.c:	if (port == chip->phy_addr_base) {
+drivers/net/dsa/lan9303-core.c:		lan9303_read(chip->regmap, LAN9303_VIRT_SPECIAL_CTRL, &ctl);
+drivers/net/dsa/lan9303-core.c:		res =  regmap_write(chip->regmap,
+drivers/net/dsa/lan9303-core.c:	lan9303_phy_write(ds, chip->phy_addr_base + port, MII_BMCR, BMCR_PDOWN);
+drivers/net/dsa/lan9303-core.c:	dev_dbg(chip->dev, "%s(port %d)\n", __func__, port);
+drivers/net/dsa/lan9303-core.c:		chip->is_bridged = true;  /* unleash stp_state_set() */
+drivers/net/dsa/lan9303-core.c:	dev_dbg(chip->dev, "%s(port %d)\n", __func__, port);
+drivers/net/dsa/lan9303-core.c:	if (chip->is_bridged) {
+drivers/net/dsa/lan9303-core.c:		chip->is_bridged = false;
+drivers/net/dsa/lan9303-core.c:	dev_dbg(chip->dev, "%s(port %d, state %d)\n",
+drivers/net/dsa/lan9303-core.c:		dev_err(chip->dev, "unknown stp state: port %d, state %d\n",
+drivers/net/dsa/lan9303-core.c:	chip->swe_port_state = (chip->swe_port_state & ~portmask) | portstate;
+drivers/net/dsa/lan9303-core.c:	if (chip->is_bridged)
+drivers/net/dsa/lan9303-core.c:					 chip->swe_port_state);
+drivers/net/dsa/lan9303-core.c:	dev_dbg(chip->dev, "%s(%d)\n", __func__, port);
+drivers/net/dsa/lan9303-core.c:	dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, addr, vid);
+drivers/net/dsa/lan9303-core.c:	dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, addr, vid);
+drivers/net/dsa/lan9303-core.c:	dev_dbg(chip->dev, "%s(%d)\n", __func__, port);
+drivers/net/dsa/lan9303-core.c:	dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, mdb->addr,
+drivers/net/dsa/lan9303-core.c:	dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, mdb->addr,
+drivers/net/dsa/lan9303-core.c:	dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, mdb->addr,
+drivers/net/dsa/lan9303-core.c:	chip->ds = devm_kzalloc(chip->dev, sizeof(*chip->ds), GFP_KERNEL);
+drivers/net/dsa/lan9303-core.c:	if (!chip->ds)
+drivers/net/dsa/lan9303-core.c:	chip->ds->dev = chip->dev;
+drivers/net/dsa/lan9303-core.c:	chip->ds->num_ports = LAN9303_NUM_PORTS;
+drivers/net/dsa/lan9303-core.c:	chip->ds->priv = chip;
+drivers/net/dsa/lan9303-core.c:	chip->ds->ops = &lan9303_switch_ops;
+drivers/net/dsa/lan9303-core.c:	base = chip->phy_addr_base;
+drivers/net/dsa/lan9303-core.c:	chip->ds->phys_mii_mask = GENMASK(LAN9303_NUM_PORTS - 1 + base, base);
+drivers/net/dsa/lan9303-core.c:	return dsa_register_switch(chip->ds);
+drivers/net/dsa/lan9303-core.c:	chip->reset_gpio = devm_gpiod_get_optional(chip->dev, "reset",
+drivers/net/dsa/lan9303-core.c:	if (IS_ERR(chip->reset_gpio))
+drivers/net/dsa/lan9303-core.c:		return PTR_ERR(chip->reset_gpio);
+drivers/net/dsa/lan9303-core.c:	if (!chip->reset_gpio) {
+drivers/net/dsa/lan9303-core.c:		dev_dbg(chip->dev, "No reset GPIO defined\n");
+drivers/net/dsa/lan9303-core.c:	chip->reset_duration = 200;
+drivers/net/dsa/lan9303-core.c:				     &chip->reset_duration);
+drivers/net/dsa/lan9303-core.c:		dev_dbg(chip->dev, "reset duration defaults to 200 ms\n");
+drivers/net/dsa/lan9303-core.c:	if (chip->reset_duration > 1000)
+drivers/net/dsa/lan9303-core.c:		chip->reset_duration = 1000;
+drivers/net/dsa/lan9303-core.c:	mutex_init(&chip->indirect_mutex);
+drivers/net/dsa/lan9303-core.c:	mutex_init(&chip->alr_mutex);
+drivers/net/dsa/lan9303-core.c:		dev_dbg(chip->dev, "Failed to register switch: %d\n", ret);
+drivers/net/dsa/lan9303-core.c:		dev_warn(chip->dev, "shutting down failed\n");
+drivers/net/dsa/lan9303-core.c:	dsa_unregister_switch(chip->ds);
+drivers/net/dsa/lan9303-core.c:	gpiod_set_value_cansleep(chip->reset_gpio, 1);
+drivers/net/dsa/lan9303-core.c:	gpiod_unexport(chip->reset_gpio);
+drivers/net/dsa/lan9303_mdio.c:	struct lan9303_mdio *sw_dev = dev_get_drvdata(chip->dev);
+drivers/net/dsa/lan9303_mdio.c:	struct lan9303_mdio *sw_dev = dev_get_drvdata(chip->dev);
+drivers/net/dsa/microchip/ksz8795.c:#include <linux/platform_data/microchip-ksz.h>
+drivers/net/dsa/microchip/ksz8795.c:		if (dev->chip_id == chip->chip_id) {
+drivers/net/dsa/microchip/ksz8795.c:			dev->name = chip->dev_name;
+drivers/net/dsa/microchip/ksz8795.c:			dev->num_vlans = chip->num_vlans;
+drivers/net/dsa/microchip/ksz8795.c:			dev->num_alus = chip->num_alus;
+drivers/net/dsa/microchip/ksz8795.c:			dev->num_statics = chip->num_statics;
+drivers/net/dsa/microchip/ksz8795.c:			dev->port_cnt = chip->port_cnt;
+drivers/net/dsa/microchip/ksz8795.c:			dev->cpu_ports = chip->cpu_ports;
+drivers/net/dsa/microchip/ksz9477.c:#include <linux/platform_data/microchip-ksz.h>
+drivers/net/dsa/microchip/ksz9477.c:		if (dev->chip_id == chip->chip_id) {
+drivers/net/dsa/microchip/ksz9477.c:			dev->name = chip->dev_name;
+drivers/net/dsa/microchip/ksz9477.c:			dev->num_vlans = chip->num_vlans;
+drivers/net/dsa/microchip/ksz9477.c:			dev->num_alus = chip->num_alus;
+drivers/net/dsa/microchip/ksz9477.c:			dev->num_statics = chip->num_statics;
+drivers/net/dsa/microchip/ksz9477.c:			dev->port_cnt = chip->port_cnt;
+drivers/net/dsa/microchip/ksz9477.c:			dev->cpu_ports = chip->cpu_ports;
+drivers/net/dsa/microchip/ksz9477.c:			dev->phy_errata_9477 = chip->phy_errata_9477;
+drivers/net/dsa/microchip/ksz_common.c:#include <linux/platform_data/microchip-ksz.h>
+drivers/net/dsa/mv88e6xxx/chip.c:	if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
+drivers/net/dsa/mv88e6xxx/chip.c:		dev_err(chip->dev, "Switch registers lock not held!\n");
+drivers/net/dsa/mv88e6xxx/chip.c:	dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
+drivers/net/dsa/mv88e6xxx/chip.c:	dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
+drivers/net/dsa/mv88e6xxx/chip.c:	dev_err(chip->dev, "Timeout while waiting for switch\n");
+drivers/net/dsa/mv88e6xxx/chip.c:	mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
+drivers/net/dsa/mv88e6xxx/chip.c:	chip->g1_irq.masked |= (1 << n);
+drivers/net/dsa/mv88e6xxx/chip.c:	chip->g1_irq.masked &= ~(1 << n);
+drivers/net/dsa/mv88e6xxx/chip.c:		for (n = 0; n < chip->g1_irq.nirqs; ++n) {
+drivers/net/dsa/mv88e6xxx/chip.c:				sub_irq = irq_find_mapping(chip->g1_irq.domain,
+drivers/net/dsa/mv88e6xxx/chip.c:		ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
+drivers/net/dsa/mv88e6xxx/chip.c:	u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
+drivers/net/dsa/mv88e6xxx/chip.c:	reg |= (~chip->g1_irq.masked & mask);
+drivers/net/dsa/mv88e6xxx/chip.c:	irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
+drivers/net/dsa/mv88e6xxx/chip.c:	mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
+drivers/net/dsa/mv88e6xxx/chip.c:	for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
+drivers/net/dsa/mv88e6xxx/chip.c:		virq = irq_find_mapping(chip->g1_irq.domain, irq);
+drivers/net/dsa/mv88e6xxx/chip.c:	irq_domain_remove(chip->g1_irq.domain);
+drivers/net/dsa/mv88e6xxx/chip.c:	free_irq(chip->irq, chip);
+drivers/net/dsa/mv88e6xxx/chip.c:	chip->g1_irq.nirqs = chip->info->g1_irqs;
+drivers/net/dsa/mv88e6xxx/chip.c:	chip->g1_irq.domain = irq_domain_add_simple(
+drivers/net/dsa/mv88e6xxx/chip.c:		NULL, chip->g1_irq.nirqs, 0,
+drivers/net/dsa/mv88e6xxx/chip.c:	if (!chip->g1_irq.domain)
+drivers/net/dsa/mv88e6xxx/chip.c:	for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
+drivers/net/dsa/mv88e6xxx/chip.c:		irq_create_mapping(chip->g1_irq.domain, irq);
+drivers/net/dsa/mv88e6xxx/chip.c:	chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
+drivers/net/dsa/mv88e6xxx/chip.c:	chip->g1_irq.masked = ~0;
+drivers/net/dsa/mv88e6xxx/chip.c:	mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
+drivers/net/dsa/mv88e6xxx/chip.c:	mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
+drivers/net/dsa/mv88e6xxx/chip.c:		virq = irq_find_mapping(chip->g1_irq.domain, irq);
+drivers/net/dsa/mv88e6xxx/chip.c:	irq_domain_remove(chip->g1_irq.domain);
+drivers/net/dsa/mv88e6xxx/chip.c:	irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
+drivers/net/dsa/mv88e6xxx/chip.c:	err = request_threaded_irq(chip->irq, NULL,
+drivers/net/dsa/mv88e6xxx/chip.c:				   dev_name(chip->dev), chip);
+drivers/net/dsa/mv88e6xxx/chip.c:	kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
+drivers/net/dsa/mv88e6xxx/chip.c:	kthread_init_delayed_work(&chip->irq_poll_work,
+drivers/net/dsa/mv88e6xxx/chip.c:	chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
+drivers/net/dsa/mv88e6xxx/chip.c:	if (IS_ERR(chip->kworker))
+drivers/net/dsa/mv88e6xxx/chip.c:		return PTR_ERR(chip->kworker);
+drivers/net/dsa/mv88e6xxx/chip.c:	kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
+drivers/net/dsa/mv88e6xxx/chip.c:	kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
+drivers/net/dsa/mv88e6xxx/chip.c:	kthread_destroy_worker(chip->kworker);
+drivers/net/dsa/mv88e6xxx/chip.c:	if (!chip->info->ops->port_set_link)
+drivers/net/dsa/mv88e6xxx/chip.c:	if (!chip->info->ops->port_link_state)
+drivers/net/dsa/mv88e6xxx/chip.c:	err = chip->info->ops->port_link_state(chip, port, &state);
+drivers/net/dsa/mv88e6xxx/chip.c:	err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->ops->port_set_speed) {
+drivers/net/dsa/mv88e6xxx/chip.c:		err = chip->info->ops->port_set_speed(chip, port, speed);
+drivers/net/dsa/mv88e6xxx/chip.c:	if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode)
+drivers/net/dsa/mv88e6xxx/chip.c:		mode = chip->info->ops->port_max_speed_mode(port);
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->ops->port_set_pause) {
+drivers/net/dsa/mv88e6xxx/chip.c:		err = chip->info->ops->port_set_pause(chip, port, pause);
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->ops->port_set_duplex) {
+drivers/net/dsa/mv88e6xxx/chip.c:		err = chip->info->ops->port_set_duplex(chip, port, duplex);
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->ops->port_set_rgmii_delay) {
+drivers/net/dsa/mv88e6xxx/chip.c:		err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->ops->port_set_cmode) {
+drivers/net/dsa/mv88e6xxx/chip.c:		err = chip->info->ops->port_set_cmode(chip, port, mode);
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->ops->port_set_link(chip, port, link))
+drivers/net/dsa/mv88e6xxx/chip.c:		dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
+drivers/net/dsa/mv88e6xxx/chip.c:	return port < chip->info->num_internal_phys;
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->ops->phylink_validate)
+drivers/net/dsa/mv88e6xxx/chip.c:		chip->info->ops->phylink_validate(chip, port, mask, state);
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->ops->port_link_state)
+drivers/net/dsa/mv88e6xxx/chip.c:		err = chip->info->ops->port_link_state(chip, port, state);
+drivers/net/dsa/mv88e6xxx/chip.c:	err = chip->info->ops->port_set_link(chip, port, link);
+drivers/net/dsa/mv88e6xxx/chip.c:		dev_err(chip->dev, "p%d: failed to force MAC link\n", port);
+drivers/net/dsa/mv88e6xxx/chip.c:	if (!chip->info->ops->stats_snapshot)
+drivers/net/dsa/mv88e6xxx/chip.c:	return chip->info->ops->stats_snapshot(chip, port);
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->ops->stats_get_strings)
+drivers/net/dsa/mv88e6xxx/chip.c:		count = chip->info->ops->stats_get_strings(chip, data);
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->ops->serdes_get_strings) {
+drivers/net/dsa/mv88e6xxx/chip.c:		count = chip->info->ops->serdes_get_strings(chip, port, data);
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->ops->stats_get_sset_count)
+drivers/net/dsa/mv88e6xxx/chip.c:		count = chip->info->ops->stats_get_sset_count(chip);
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->ops->serdes_get_sset_count)
+drivers/net/dsa/mv88e6xxx/chip.c:		serdes_count = chip->info->ops->serdes_get_sset_count(chip,
+drivers/net/dsa/mv88e6xxx/chip.c:	*data++ = chip->ports[port].atu_member_violation;
+drivers/net/dsa/mv88e6xxx/chip.c:	*data++ = chip->ports[port].atu_miss_violation;
+drivers/net/dsa/mv88e6xxx/chip.c:	*data++ = chip->ports[port].atu_full_violation;
+drivers/net/dsa/mv88e6xxx/chip.c:	*data++ = chip->ports[port].vtu_member_violation;
+drivers/net/dsa/mv88e6xxx/chip.c:	*data++ = chip->ports[port].vtu_miss_violation;
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->ops->stats_get_stats)
+drivers/net/dsa/mv88e6xxx/chip.c:		count = chip->info->ops->stats_get_stats(chip, port, data);
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->ops->serdes_get_stats) {
+drivers/net/dsa/mv88e6xxx/chip.c:		count = chip->info->ops->serdes_get_stats(chip, port, data);
+drivers/net/dsa/mv88e6xxx/chip.c:	regs->version = chip->info->prod_num;
+drivers/net/dsa/mv88e6xxx/chip.c:	struct dsa_switch *ds = chip->ds;
+drivers/net/dsa/mv88e6xxx/chip.c:	u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->ops->ieee_pri_map) {
+drivers/net/dsa/mv88e6xxx/chip.c:		err = chip->info->ops->ieee_pri_map(chip);
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->ops->ip_pri_map) {
+drivers/net/dsa/mv88e6xxx/chip.c:		err = chip->info->ops->ip_pri_map(chip);
+drivers/net/dsa/mv88e6xxx/chip.c:	struct dsa_switch *ds = chip->ds;
+drivers/net/dsa/mv88e6xxx/chip.c:	if (!chip->info->global2_addr)
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->ops->set_cascade_port) {
+drivers/net/dsa/mv88e6xxx/chip.c:		err = chip->info->ops->set_cascade_port(chip, port);
+drivers/net/dsa/mv88e6xxx/chip.c:	err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->global2_addr)
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->ops->rmu_disable)
+drivers/net/dsa/mv88e6xxx/chip.c:		return chip->info->ops->rmu_disable(chip);
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->ops->pot_clear)
+drivers/net/dsa/mv88e6xxx/chip.c:		return chip->info->ops->pot_clear(chip);
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->ops->mgmt_rsvd2cpu)
+drivers/net/dsa/mv88e6xxx/chip.c:		return chip->info->ops->mgmt_rsvd2cpu(chip);
+drivers/net/dsa/mv88e6xxx/chip.c:	if (!chip->info->ops->irl_init_all)
+drivers/net/dsa/mv88e6xxx/chip.c:		err = chip->info->ops->irl_init_all(chip, port);
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->ops->set_switch_mac) {
+drivers/net/dsa/mv88e6xxx/chip.c:		return chip->info->ops->set_switch_mac(chip, addr);
+drivers/net/dsa/mv88e6xxx/chip.c:	if (dev != chip->ds->index)
+drivers/net/dsa/mv88e6xxx/chip.c:	if (!chip->info->max_vid)
+drivers/net/dsa/mv88e6xxx/chip.c:	if (!chip->info->ops->vtu_getnext)
+drivers/net/dsa/mv88e6xxx/chip.c:	return chip->info->ops->vtu_getnext(chip, entry);
+drivers/net/dsa/mv88e6xxx/chip.c:	if (!chip->info->ops->vtu_loadpurge)
+drivers/net/dsa/mv88e6xxx/chip.c:	return chip->info->ops->vtu_loadpurge(chip, entry);
+drivers/net/dsa/mv88e6xxx/chip.c:	vlan.vid = chip->info->max_vid;
+drivers/net/dsa/mv88e6xxx/chip.c:	} while (vlan.vid < chip->info->max_vid);
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->ops->atu_get_hash)
+drivers/net/dsa/mv88e6xxx/chip.c:		return chip->info->ops->atu_get_hash(chip, hash);
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->ops->atu_set_hash)
+drivers/net/dsa/mv88e6xxx/chip.c:		return chip->info->ops->atu_set_hash(chip, hash);
+drivers/net/dsa/mv88e6xxx/chip.c:	if (!chip->info->max_vid)
+drivers/net/dsa/mv88e6xxx/chip.c:	if (!chip->info->max_vid)
+drivers/net/dsa/mv88e6xxx/chip.c:	if (!chip->info->ops->port_set_policy)
+drivers/net/dsa/mv88e6xxx/chip.c:		idr_for_each_entry(&chip->policies, policy, id)
+drivers/net/dsa/mv88e6xxx/chip.c:	return chip->info->ops->port_set_policy(chip, port, mapping, action);
+drivers/net/dsa/mv88e6xxx/chip.c:	idr_for_each_entry(&chip->policies, policy, id) {
+drivers/net/dsa/mv88e6xxx/chip.c:	policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL);
+drivers/net/dsa/mv88e6xxx/chip.c:	err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff,
+drivers/net/dsa/mv88e6xxx/chip.c:		devm_kfree(chip->dev, policy);
+drivers/net/dsa/mv88e6xxx/chip.c:		idr_remove(&chip->policies, fs->location);
+drivers/net/dsa/mv88e6xxx/chip.c:		devm_kfree(chip->dev, policy);
+drivers/net/dsa/mv88e6xxx/chip.c:		idr_for_each_entry(&chip->policies, policy, id)
+drivers/net/dsa/mv88e6xxx/chip.c:		policy = idr_find(&chip->policies, fs->location);
+drivers/net/dsa/mv88e6xxx/chip.c:		idr_for_each_entry(&chip->policies, policy, id)
+drivers/net/dsa/mv88e6xxx/chip.c:		policy = idr_remove(&chip->policies, fs->location);
+drivers/net/dsa/mv88e6xxx/chip.c:			devm_kfree(chip->dev, policy);
+drivers/net/dsa/mv88e6xxx/chip.c:		dev_info(chip->dev, "p%d: already a member of VLAN %d\n",
+drivers/net/dsa/mv88e6xxx/chip.c:	if (!chip->info->max_vid)
+drivers/net/dsa/mv88e6xxx/chip.c:	if (!chip->info->max_vid)
+drivers/net/dsa/mv88e6xxx/chip.c:	vlan.vid = chip->info->max_vid;
+drivers/net/dsa/mv88e6xxx/chip.c:	} while (vlan.vid < chip->info->max_vid);
+drivers/net/dsa/mv88e6xxx/chip.c:	struct dsa_switch *ds = chip->ds;
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->ops->reset)
+drivers/net/dsa/mv88e6xxx/chip.c:		return chip->info->ops->reset(chip);
+drivers/net/dsa/mv88e6xxx/chip.c:	struct gpio_desc *gpiod = chip->reset;
+drivers/net/dsa/mv88e6xxx/chip.c:	if (!chip->info->ops->port_set_frame_mode)
+drivers/net/dsa/mv88e6xxx/chip.c:	err = chip->info->ops->port_set_frame_mode(chip, port, frame);
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->ops->port_set_ether_type)
+drivers/net/dsa/mv88e6xxx/chip.c:		return chip->info->ops->port_set_ether_type(chip, port, etype);
+drivers/net/dsa/mv88e6xxx/chip.c:	if (dsa_is_dsa_port(chip->ds, port))
+drivers/net/dsa/mv88e6xxx/chip.c:	if (dsa_is_user_port(chip->ds, port))
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
+drivers/net/dsa/mv88e6xxx/chip.c:	bool message = dsa_is_dsa_port(chip->ds, port);
+drivers/net/dsa/mv88e6xxx/chip.c:	struct dsa_switch *ds = chip->ds;
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->ops->port_set_egress_floods)
+drivers/net/dsa/mv88e6xxx/chip.c:		return chip->info->ops->port_set_egress_floods(chip, port,
+drivers/net/dsa/mv88e6xxx/chip.c:	struct mv88e6xxx_port *dev_id = &chip->ports[port];
+drivers/net/dsa/mv88e6xxx/chip.c:	struct mv88e6xxx_port *dev_id = &chip->ports[port];
+drivers/net/dsa/mv88e6xxx/chip.c:	struct dsa_switch *ds = chip->ds;
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->ops->port_set_upstream_port) {
+drivers/net/dsa/mv88e6xxx/chip.c:		err = chip->info->ops->port_set_upstream_port(chip, port,
+drivers/net/dsa/mv88e6xxx/chip.c:		if (chip->info->ops->set_cpu_port) {
+drivers/net/dsa/mv88e6xxx/chip.c:			err = chip->info->ops->set_cpu_port(chip,
+drivers/net/dsa/mv88e6xxx/chip.c:		if (chip->info->ops->set_egress_port) {
+drivers/net/dsa/mv88e6xxx/chip.c:			err = chip->info->ops->set_egress_port(chip,
+drivers/net/dsa/mv88e6xxx/chip.c:			err = chip->info->ops->set_egress_port(chip,
+drivers/net/dsa/mv88e6xxx/chip.c:	struct dsa_switch *ds = chip->ds;
+drivers/net/dsa/mv88e6xxx/chip.c:	chip->ports[port].chip = chip;
+drivers/net/dsa/mv88e6xxx/chip.c:	chip->ports[port].port = port;
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->ops->port_set_jumbo_size) {
+drivers/net/dsa/mv88e6xxx/chip.c:		err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->ops->port_pause_limit) {
+drivers/net/dsa/mv88e6xxx/chip.c:		err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->ops->port_disable_learn_limit) {
+drivers/net/dsa/mv88e6xxx/chip.c:		err = chip->info->ops->port_disable_learn_limit(chip, port);
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->ops->port_disable_pri_override) {
+drivers/net/dsa/mv88e6xxx/chip.c:		err = chip->info->ops->port_disable_pri_override(chip, port);
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->ops->port_tag_remap) {
+drivers/net/dsa/mv88e6xxx/chip.c:		err = chip->info->ops->port_tag_remap(chip, port);
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->ops->port_egress_rate_limiting) {
+drivers/net/dsa/mv88e6xxx/chip.c:		err = chip->info->ops->port_egress_rate_limiting(chip, port);
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->ops->port_setup_message_port) {
+drivers/net/dsa/mv88e6xxx/chip.c:		err = chip->info->ops->port_setup_message_port(chip, port);
+drivers/net/dsa/mv88e6xxx/chip.c:		dev_err(chip->dev, "failed to power off SERDES\n");
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->ops->stats_set_histogram) {
+drivers/net/dsa/mv88e6xxx/chip.c:		err = chip->info->ops->stats_set_histogram(chip);
+drivers/net/dsa/mv88e6xxx/chip.c:			dev_err(chip->dev,
+drivers/net/dsa/mv88e6xxx/chip.c:		dev_err(chip->dev, "failed to set ATU stats kind/bin\n");
+drivers/net/dsa/mv88e6xxx/chip.c:		dev_err(chip->dev, "failed to perform ATU get next\n");
+drivers/net/dsa/mv88e6xxx/chip.c:		dev_err(chip->dev, "failed to get ATU stats\n");
+drivers/net/dsa/mv88e6xxx/chip.c:	chip->ds = ds;
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->ops->setup_errata) {
+drivers/net/dsa/mv88e6xxx/chip.c:		err = chip->info->ops->setup_errata(chip);
+drivers/net/dsa/mv88e6xxx/chip.c:		if (chip->info->ops->port_get_cmode) {
+drivers/net/dsa/mv88e6xxx/chip.c:			err = chip->info->ops->port_get_cmode(chip, i, &cmode);
+drivers/net/dsa/mv88e6xxx/chip.c:			chip->ports[i].cmode = cmode;
+drivers/net/dsa/mv88e6xxx/chip.c:			dev_err(chip->dev, "port %d is invalid\n", i);
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->ptp_support) {
+drivers/net/dsa/mv88e6xxx/chip.c:	if (!chip->info->ops->phy_read)
+drivers/net/dsa/mv88e6xxx/chip.c:	err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
+drivers/net/dsa/mv88e6xxx/chip.c:		if (chip->info->family != MV88E6XXX_FAMILY_6165)
+drivers/net/dsa/mv88e6xxx/chip.c:	if (!chip->info->ops->phy_write)
+drivers/net/dsa/mv88e6xxx/chip.c:	err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
+drivers/net/dsa/mv88e6xxx/chip.c:	bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
+drivers/net/dsa/mv88e6xxx/chip.c:	bus->parent = chip->dev;
+drivers/net/dsa/mv88e6xxx/chip.c:		dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
+drivers/net/dsa/mv88e6xxx/chip.c:		list_add_tail(&mdio_bus->list, &chip->mdios);
+drivers/net/dsa/mv88e6xxx/chip.c:		list_add(&mdio_bus->list, &chip->mdios);
+drivers/net/dsa/mv88e6xxx/chip.c:	list_for_each_entry(mdio_bus, &chip->mdios, list) {
+drivers/net/dsa/mv88e6xxx/chip.c:	return chip->eeprom_len;
+drivers/net/dsa/mv88e6xxx/chip.c:	if (!chip->info->ops->get_eeprom)
+drivers/net/dsa/mv88e6xxx/chip.c:	err = chip->info->ops->get_eeprom(chip, eeprom, data);
+drivers/net/dsa/mv88e6xxx/chip.c:	if (!chip->info->ops->set_eeprom)
+drivers/net/dsa/mv88e6xxx/chip.c:	err = chip->info->ops->set_eeprom(chip, eeprom, data);
+drivers/net/dsa/mv88e6xxx/chip.c:	chip->info = info;
+drivers/net/dsa/mv88e6xxx/chip.c:	dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
+drivers/net/dsa/mv88e6xxx/chip.c:		 chip->info->prod_num, chip->info->name, rev);
+drivers/net/dsa/mv88e6xxx/chip.c:	chip->dev = dev;
+drivers/net/dsa/mv88e6xxx/chip.c:	mutex_init(&chip->reg_lock);
+drivers/net/dsa/mv88e6xxx/chip.c:	INIT_LIST_HEAD(&chip->mdios);
+drivers/net/dsa/mv88e6xxx/chip.c:	idr_init(&chip->policies);
+drivers/net/dsa/mv88e6xxx/chip.c:	return chip->info->tag_protocol;
+drivers/net/dsa/mv88e6xxx/chip.c:	if (!chip->info->ops->set_egress_port)
+drivers/net/dsa/mv88e6xxx/chip.c:	mutex_lock(&chip->reg_lock);
+drivers/net/dsa/mv88e6xxx/chip.c:	if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) !=
+drivers/net/dsa/mv88e6xxx/chip.c:					 chip->ports[i].mirror_ingress :
+drivers/net/dsa/mv88e6xxx/chip.c:					 chip->ports[i].mirror_egress;
+drivers/net/dsa/mv88e6xxx/chip.c:		err = chip->info->ops->set_egress_port(chip,
+drivers/net/dsa/mv88e6xxx/chip.c:	mutex_unlock(&chip->reg_lock);
+drivers/net/dsa/mv88e6xxx/chip.c:	mutex_lock(&chip->reg_lock);
+drivers/net/dsa/mv88e6xxx/chip.c:				 chip->ports[i].mirror_ingress :
+drivers/net/dsa/mv88e6xxx/chip.c:				 chip->ports[i].mirror_egress;
+drivers/net/dsa/mv88e6xxx/chip.c:		if (chip->info->ops->set_egress_port(chip,
+drivers/net/dsa/mv88e6xxx/chip.c:	mutex_unlock(&chip->reg_lock);
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->ops->port_set_egress_floods)
+drivers/net/dsa/mv88e6xxx/chip.c:		err = chip->info->ops->port_set_egress_floods(chip, port,
+drivers/net/dsa/mv88e6xxx/chip.c:	struct device *dev = chip->dev;
+drivers/net/dsa/mv88e6xxx/chip.c:	ds->ageing_time_min = chip->info->age_time_coeff;
+drivers/net/dsa/mv88e6xxx/chip.c:	ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
+drivers/net/dsa/mv88e6xxx/chip.c:	dsa_unregister_switch(chip->ds);
+drivers/net/dsa/mv88e6xxx/chip.c:	chip->info = compat_info;
+drivers/net/dsa/mv88e6xxx/chip.c:	chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
+drivers/net/dsa/mv88e6xxx/chip.c:	if (IS_ERR(chip->reset)) {
+drivers/net/dsa/mv88e6xxx/chip.c:		err = PTR_ERR(chip->reset);
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->reset)
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->ops->get_eeprom) {
+drivers/net/dsa/mv88e6xxx/chip.c:					     &chip->eeprom_len);
+drivers/net/dsa/mv88e6xxx/chip.c:			chip->eeprom_len = pdata->eeprom_len;
+drivers/net/dsa/mv88e6xxx/chip.c:		chip->irq = of_irq_get(np, 0);
+drivers/net/dsa/mv88e6xxx/chip.c:		if (chip->irq == -EPROBE_DEFER) {
+drivers/net/dsa/mv88e6xxx/chip.c:			err = chip->irq;
+drivers/net/dsa/mv88e6xxx/chip.c:		chip->irq = pdata->irq;
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->irq > 0)
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->g2_irqs > 0) {
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->g2_irqs > 0)
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->irq > 0)
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->ptp_support) {
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->info->g2_irqs > 0)
+drivers/net/dsa/mv88e6xxx/chip.c:	if (chip->irq > 0)
+drivers/net/dsa/mv88e6xxx/chip.h:	return chip->info->pvt;
+drivers/net/dsa/mv88e6xxx/chip.h:	return chip->info->num_databases;
+drivers/net/dsa/mv88e6xxx/chip.h:	return chip->info->num_macs;
+drivers/net/dsa/mv88e6xxx/chip.h:	return chip->info->num_ports;
+drivers/net/dsa/mv88e6xxx/chip.h:	return chip->info->num_gpio;
+drivers/net/dsa/mv88e6xxx/chip.h:	return (chip->info->invalid_port_mask & BIT(port)) != 0;
+drivers/net/dsa/mv88e6xxx/chip.h:	mutex_lock(&chip->reg_lock);
+drivers/net/dsa/mv88e6xxx/chip.h:	mutex_unlock(&chip->reg_lock);
+drivers/net/dsa/mv88e6xxx/global1.c:	int addr = chip->info->global1_addr;
+drivers/net/dsa/mv88e6xxx/global1.c:	int addr = chip->info->global1_addr;
+drivers/net/dsa/mv88e6xxx/global1.c:	return mv88e6xxx_wait_bit(chip, chip->info->global1_addr, reg,
+drivers/net/dsa/mv88e6xxx/global1.c:	return mv88e6xxx_wait_mask(chip, chip->info->global1_addr, reg,
+drivers/net/dsa/mv88e6xxx/global1.c:		dest_port_chip = &chip->ingress_dest_port;
+drivers/net/dsa/mv88e6xxx/global1.c:		dest_port_chip = &chip->egress_dest_port;
+drivers/net/dsa/mv88e6xxx/global1.c:		dest_port_chip = &chip->ingress_dest_port;
+drivers/net/dsa/mv88e6xxx/global1.c:		dest_port_chip = &chip->egress_dest_port;
+drivers/net/dsa/mv88e6xxx/global1_atu.c:	const unsigned int coeff = chip->info->age_time_coeff;
+drivers/net/dsa/mv88e6xxx/global1_atu.c:	dev_dbg(chip->dev, "AgeTime set to 0x%02x (%d ms)\n", age_time,
+drivers/net/dsa/mv88e6xxx/global1_atu.c:	if (!chip->info->atu_move_port_mask)
+drivers/net/dsa/mv88e6xxx/global1_atu.c:	mask = chip->info->atu_move_port_mask;
+drivers/net/dsa/mv88e6xxx/global1_atu.c:	int to_port = chip->info->atu_move_port_mask;
+drivers/net/dsa/mv88e6xxx/global1_atu.c:		dev_err_ratelimited(chip->dev,
+drivers/net/dsa/mv88e6xxx/global1_atu.c:		dev_err_ratelimited(chip->dev,
+drivers/net/dsa/mv88e6xxx/global1_atu.c:		chip->ports[spid].atu_member_violation++;
+drivers/net/dsa/mv88e6xxx/global1_atu.c:		dev_err_ratelimited(chip->dev,
+drivers/net/dsa/mv88e6xxx/global1_atu.c:		chip->ports[spid].atu_miss_violation++;
+drivers/net/dsa/mv88e6xxx/global1_atu.c:		dev_err_ratelimited(chip->dev,
+drivers/net/dsa/mv88e6xxx/global1_atu.c:		chip->ports[spid].atu_full_violation++;
+drivers/net/dsa/mv88e6xxx/global1_atu.c:	dev_err(chip->dev, "ATU problem: error %d while handling interrupt\n",
+drivers/net/dsa/mv88e6xxx/global1_atu.c:	chip->atu_prob_irq = irq_find_mapping(chip->g1_irq.domain,
+drivers/net/dsa/mv88e6xxx/global1_atu.c:	if (chip->atu_prob_irq < 0)
+drivers/net/dsa/mv88e6xxx/global1_atu.c:		return chip->atu_prob_irq;
+drivers/net/dsa/mv88e6xxx/global1_atu.c:	err = request_threaded_irq(chip->atu_prob_irq, NULL,
+drivers/net/dsa/mv88e6xxx/global1_atu.c:		irq_dispose_mapping(chip->atu_prob_irq);
+drivers/net/dsa/mv88e6xxx/global1_atu.c:	free_irq(chip->atu_prob_irq, chip);
+drivers/net/dsa/mv88e6xxx/global1_atu.c:	irq_dispose_mapping(chip->atu_prob_irq);
+drivers/net/dsa/mv88e6xxx/global1_vtu.c:		dev_err_ratelimited(chip->dev, "VTU member violation for vid %d, source port %d\n",
+drivers/net/dsa/mv88e6xxx/global1_vtu.c:		chip->ports[spid].vtu_member_violation++;
+drivers/net/dsa/mv88e6xxx/global1_vtu.c:		dev_dbg_ratelimited(chip->dev, "VTU miss violation for vid %d, source port %d\n",
+drivers/net/dsa/mv88e6xxx/global1_vtu.c:		chip->ports[spid].vtu_miss_violation++;
+drivers/net/dsa/mv88e6xxx/global1_vtu.c:	dev_err(chip->dev, "VTU problem: error %d while handling interrupt\n",
+drivers/net/dsa/mv88e6xxx/global1_vtu.c:	chip->vtu_prob_irq = irq_find_mapping(chip->g1_irq.domain,
+drivers/net/dsa/mv88e6xxx/global1_vtu.c:	if (chip->vtu_prob_irq < 0)
+drivers/net/dsa/mv88e6xxx/global1_vtu.c:		return chip->vtu_prob_irq;
+drivers/net/dsa/mv88e6xxx/global1_vtu.c:	err = request_threaded_irq(chip->vtu_prob_irq, NULL,
+drivers/net/dsa/mv88e6xxx/global1_vtu.c:		irq_dispose_mapping(chip->vtu_prob_irq);
+drivers/net/dsa/mv88e6xxx/global1_vtu.c:	free_irq(chip->vtu_prob_irq, chip);
+drivers/net/dsa/mv88e6xxx/global1_vtu.c:	irq_dispose_mapping(chip->vtu_prob_irq);
+drivers/net/dsa/mv88e6xxx/global2.c:	return mv88e6xxx_read(chip, chip->info->global2_addr, reg, val);
+drivers/net/dsa/mv88e6xxx/global2.c:	return mv88e6xxx_write(chip, chip->info->global2_addr, reg, val);
+drivers/net/dsa/mv88e6xxx/global2.c:	return mv88e6xxx_wait_bit(chip, chip->info->global2_addr, reg,
+drivers/net/dsa/mv88e6xxx/global2.c:	dev_info(chip->dev, "Watchdog event: 0x%04x", reg);
+drivers/net/dsa/mv88e6xxx/global2.c:	dev_info(chip->dev, "Watchdog event: 0x%04x",
+drivers/net/dsa/mv88e6xxx/global2.c:	dev_info(chip->dev, "Watchdog history: 0x%04x",
+drivers/net/dsa/mv88e6xxx/global2.c:	if (chip->info->ops->reset)
+drivers/net/dsa/mv88e6xxx/global2.c:		chip->info->ops->reset(chip);
+drivers/net/dsa/mv88e6xxx/global2.c:	if (chip->info->ops->watchdog_ops->irq_action)
+drivers/net/dsa/mv88e6xxx/global2.c:		ret = chip->info->ops->watchdog_ops->irq_action(chip, irq);
+drivers/net/dsa/mv88e6xxx/global2.c:	if (chip->info->ops->watchdog_ops->irq_free)
+drivers/net/dsa/mv88e6xxx/global2.c:		chip->info->ops->watchdog_ops->irq_free(chip);
+drivers/net/dsa/mv88e6xxx/global2.c:	free_irq(chip->watchdog_irq, chip);
+drivers/net/dsa/mv88e6xxx/global2.c:	irq_dispose_mapping(chip->watchdog_irq);
+drivers/net/dsa/mv88e6xxx/global2.c:	chip->watchdog_irq = irq_find_mapping(chip->g2_irq.domain,
+drivers/net/dsa/mv88e6xxx/global2.c:	if (chip->watchdog_irq < 0)
+drivers/net/dsa/mv88e6xxx/global2.c:		return chip->watchdog_irq;
+drivers/net/dsa/mv88e6xxx/global2.c:	err = request_threaded_irq(chip->watchdog_irq, NULL,
+drivers/net/dsa/mv88e6xxx/global2.c:	if (chip->info->ops->watchdog_ops->irq_setup)
+drivers/net/dsa/mv88e6xxx/global2.c:		err = chip->info->ops->watchdog_ops->irq_setup(chip);
+drivers/net/dsa/mv88e6xxx/global2.c:	chip->g2_irq.masked |= (1 << n);
+drivers/net/dsa/mv88e6xxx/global2.c:	chip->g2_irq.masked &= ~(1 << n);
+drivers/net/dsa/mv88e6xxx/global2.c:			sub_irq = irq_find_mapping(chip->g2_irq.domain, n);
+drivers/net/dsa/mv88e6xxx/global2.c:	err = mv88e6xxx_g2_int_mask(chip, ~chip->g2_irq.masked);
+drivers/net/dsa/mv88e6xxx/global2.c:		dev_err(chip->dev, "failed to mask interrupts\n");
+drivers/net/dsa/mv88e6xxx/global2.c:	irq_set_chip_and_handler(irq, &chip->g2_irq.chip, handle_level_irq);
+drivers/net/dsa/mv88e6xxx/global2.c:	free_irq(chip->device_irq, chip);
+drivers/net/dsa/mv88e6xxx/global2.c:	irq_dispose_mapping(chip->device_irq);
+drivers/net/dsa/mv88e6xxx/global2.c:		virq = irq_find_mapping(chip->g2_irq.domain, irq);
+drivers/net/dsa/mv88e6xxx/global2.c:	irq_domain_remove(chip->g2_irq.domain);
+drivers/net/dsa/mv88e6xxx/global2.c:	chip->g2_irq.domain = irq_domain_add_simple(
+drivers/net/dsa/mv88e6xxx/global2.c:		chip->dev->of_node, 16, 0, &mv88e6xxx_g2_irq_domain_ops, chip);
+drivers/net/dsa/mv88e6xxx/global2.c:	if (!chip->g2_irq.domain)
+drivers/net/dsa/mv88e6xxx/global2.c:		irq_create_mapping(chip->g2_irq.domain, irq);
+drivers/net/dsa/mv88e6xxx/global2.c:	chip->g2_irq.chip = mv88e6xxx_g2_irq_chip;
+drivers/net/dsa/mv88e6xxx/global2.c:	chip->g2_irq.masked = ~0;
+drivers/net/dsa/mv88e6xxx/global2.c:	chip->device_irq = irq_find_mapping(chip->g1_irq.domain,
+drivers/net/dsa/mv88e6xxx/global2.c:	if (chip->device_irq < 0) {
+drivers/net/dsa/mv88e6xxx/global2.c:		err = chip->device_irq;
+drivers/net/dsa/mv88e6xxx/global2.c:	err = request_threaded_irq(chip->device_irq, NULL,
+drivers/net/dsa/mv88e6xxx/global2.c:		virq = irq_find_mapping(chip->g2_irq.domain, irq);
+drivers/net/dsa/mv88e6xxx/global2.c:	irq_domain_remove(chip->g2_irq.domain);
+drivers/net/dsa/mv88e6xxx/global2.c:	for (phy = 0; phy < chip->info->num_internal_phys; phy++) {
+drivers/net/dsa/mv88e6xxx/global2.c:		irq = irq_find_mapping(chip->g2_irq.domain, phy);
+drivers/net/dsa/mv88e6xxx/global2.c:		bus->irq[chip->info->phy_base_addr + phy] = irq;
+drivers/net/dsa/mv88e6xxx/global2.c:	for (phy = 0; phy < chip->info->num_internal_phys; phy++)
+drivers/net/dsa/mv88e6xxx/global2.h:	if (chip->info->global2_addr) {
+drivers/net/dsa/mv88e6xxx/global2.h:		dev_err(chip->dev, "this chip requires CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 enabled\n");
+drivers/net/dsa/mv88e6xxx/global2_scratch.c:		chip->gpio_data[offset] |= mask;
+drivers/net/dsa/mv88e6xxx/global2_scratch.c:		chip->gpio_data[offset] &= ~mask;
+drivers/net/dsa/mv88e6xxx/global2_scratch.c:	return mv88e6xxx_g2_scratch_write(chip, reg, chip->gpio_data[offset]);
+drivers/net/dsa/mv88e6xxx/hwtstamp.c:	if (!chip->info->ops->avb_ops->port_ptp_read)
+drivers/net/dsa/mv88e6xxx/hwtstamp.c:	return chip->info->ops->avb_ops->port_ptp_read(chip, port, addr,
+drivers/net/dsa/mv88e6xxx/hwtstamp.c:	if (!chip->info->ops->avb_ops->port_ptp_write)
+drivers/net/dsa/mv88e6xxx/hwtstamp.c:	return chip->info->ops->avb_ops->port_ptp_write(chip, port, addr,
+drivers/net/dsa/mv88e6xxx/hwtstamp.c:	if (!chip->info->ops->avb_ops->ptp_write)
+drivers/net/dsa/mv88e6xxx/hwtstamp.c:	return chip->info->ops->avb_ops->ptp_write(chip, addr, data);
+drivers/net/dsa/mv88e6xxx/hwtstamp.c:	if (!chip->info->ops->avb_ops->ptp_read)
+drivers/net/dsa/mv88e6xxx/hwtstamp.c:	return chip->info->ops->avb_ops->ptp_read(chip, addr, data, 1);
+drivers/net/dsa/mv88e6xxx/hwtstamp.c:	ptp_ops = chip->info->ops->ptp_ops;
+drivers/net/dsa/mv88e6xxx/hwtstamp.c:	if (!chip->info->ptp_support)
+drivers/net/dsa/mv88e6xxx/hwtstamp.c:	info->phc_index = ptp_clock_index(chip->ptp_clock);
+drivers/net/dsa/mv88e6xxx/hwtstamp.c:	const struct mv88e6xxx_ptp_ops *ptp_ops = chip->info->ops->ptp_ops;
+drivers/net/dsa/mv88e6xxx/hwtstamp.c:	struct mv88e6xxx_port_hwtstamp *ps = &chip->port_hwtstamp[port];
+drivers/net/dsa/mv88e6xxx/hwtstamp.c:		dev_dbg(chip->dev, "Unsupported rx_filter %d\n",
+drivers/net/dsa/mv88e6xxx/hwtstamp.c:		chip->enable_count += 1;
+drivers/net/dsa/mv88e6xxx/hwtstamp.c:		if (chip->enable_count == 1 && ptp_ops->global_enable)
+drivers/net/dsa/mv88e6xxx/hwtstamp.c:		chip->enable_count -= 1;
+drivers/net/dsa/mv88e6xxx/hwtstamp.c:		if (chip->enable_count == 0 && ptp_ops->global_disable)
+drivers/net/dsa/mv88e6xxx/hwtstamp.c:	struct mv88e6xxx_port_hwtstamp *ps = &chip->port_hwtstamp[port];
+drivers/net/dsa/mv88e6xxx/hwtstamp.c:	if (!chip->info->ptp_support)
+drivers/net/dsa/mv88e6xxx/hwtstamp.c:	struct mv88e6xxx_port_hwtstamp *ps = &chip->port_hwtstamp[port];
+drivers/net/dsa/mv88e6xxx/hwtstamp.c:	if (!chip->info->ptp_support)
+drivers/net/dsa/mv88e6xxx/hwtstamp.c:	struct mv88e6xxx_port_hwtstamp *ps = &chip->port_hwtstamp[port];
+drivers/net/dsa/mv88e6xxx/hwtstamp.c:	if (!chip->info->ptp_support)
+drivers/net/dsa/mv88e6xxx/hwtstamp.c:			ns = timecounter_cyc2time(&chip->tstamp_tc, ns);
+drivers/net/dsa/mv88e6xxx/hwtstamp.c:	const struct mv88e6xxx_ptp_ops *ptp_ops = chip->info->ops->ptp_ops;
+drivers/net/dsa/mv88e6xxx/hwtstamp.c:	ps = &chip->port_hwtstamp[port];
+drivers/net/dsa/mv88e6xxx/hwtstamp.c:	ptp_schedule_worker(chip->ptp_clock, 0);
+drivers/net/dsa/mv88e6xxx/hwtstamp.c:	const struct mv88e6xxx_ptp_ops *ptp_ops = chip->info->ops->ptp_ops;
+drivers/net/dsa/mv88e6xxx/hwtstamp.c:			dev_warn(chip->dev, "p%d: clearing tx timestamp hang\n",
+drivers/net/dsa/mv88e6xxx/hwtstamp.c:		dev_warn(chip->dev, "p%d: tx timestamp overrun\n", ps->port_id);
+drivers/net/dsa/mv88e6xxx/hwtstamp.c:		dev_warn(chip->dev, "p%d: unexpected seq. id\n", ps->port_id);
+drivers/net/dsa/mv88e6xxx/hwtstamp.c:	ns = timecounter_cyc2time(&chip->tstamp_tc, time_raw);
+drivers/net/dsa/mv88e6xxx/hwtstamp.c:	dev_dbg(chip->dev,
+drivers/net/dsa/mv88e6xxx/hwtstamp.c:	struct dsa_switch *ds = chip->ds;
+drivers/net/dsa/mv88e6xxx/hwtstamp.c:		ps = &chip->port_hwtstamp[i];
+drivers/net/dsa/mv88e6xxx/hwtstamp.c:	struct mv88e6xxx_port_hwtstamp *ps = &chip->port_hwtstamp[port];
+drivers/net/dsa/mv88e6xxx/hwtstamp.c:	ptp_schedule_worker(chip->ptp_clock, 0);
+drivers/net/dsa/mv88e6xxx/hwtstamp.c:	const struct mv88e6xxx_ptp_ops *ptp_ops = chip->info->ops->ptp_ops;
+drivers/net/dsa/mv88e6xxx/hwtstamp.c:	struct mv88e6xxx_port_hwtstamp *ps = &chip->port_hwtstamp[port];
+drivers/net/dsa/mv88e6xxx/hwtstamp.c:	const struct mv88e6xxx_ptp_ops *ptp_ops = chip->info->ops->ptp_ops;
+drivers/net/dsa/mv88e6xxx/hwtstamp.c:	if (chip->info->family == MV88E6XXX_FAMILY_6341) {
+drivers/net/dsa/mv88e6xxx/phy.c:	if (!chip->info->ops->phy_read)
+drivers/net/dsa/mv88e6xxx/phy.c:	return chip->info->ops->phy_read(chip, bus, addr, reg, val);
+drivers/net/dsa/mv88e6xxx/phy.c:	if (!chip->info->ops->phy_write)
+drivers/net/dsa/mv88e6xxx/phy.c:	return chip->info->ops->phy_write(chip, bus, addr, reg, val);
+drivers/net/dsa/mv88e6xxx/phy.c:		dev_err(chip->dev,
+drivers/net/dsa/mv88e6xxx/phy.c:	if (!chip->info->ops->ppu_disable)
+drivers/net/dsa/mv88e6xxx/phy.c:	return chip->info->ops->ppu_disable(chip);
+drivers/net/dsa/mv88e6xxx/phy.c:	if (!chip->info->ops->ppu_enable)
+drivers/net/dsa/mv88e6xxx/phy.c:	return chip->info->ops->ppu_enable(chip);
+drivers/net/dsa/mv88e6xxx/phy.c:	if (mutex_trylock(&chip->ppu_mutex)) {
+drivers/net/dsa/mv88e6xxx/phy.c:			chip->ppu_disabled = 0;
+drivers/net/dsa/mv88e6xxx/phy.c:		mutex_unlock(&chip->ppu_mutex);
+drivers/net/dsa/mv88e6xxx/phy.c:	schedule_work(&chip->ppu_work);
+drivers/net/dsa/mv88e6xxx/phy.c:	mutex_lock(&chip->ppu_mutex);
+drivers/net/dsa/mv88e6xxx/phy.c:	if (!chip->ppu_disabled) {
+drivers/net/dsa/mv88e6xxx/phy.c:			mutex_unlock(&chip->ppu_mutex);
+drivers/net/dsa/mv88e6xxx/phy.c:		chip->ppu_disabled = 1;
+drivers/net/dsa/mv88e6xxx/phy.c:		del_timer(&chip->ppu_timer);
+drivers/net/dsa/mv88e6xxx/phy.c:	mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
+drivers/net/dsa/mv88e6xxx/phy.c:	mutex_unlock(&chip->ppu_mutex);
+drivers/net/dsa/mv88e6xxx/phy.c:	mutex_init(&chip->ppu_mutex);
+drivers/net/dsa/mv88e6xxx/phy.c:	INIT_WORK(&chip->ppu_work, mv88e6xxx_phy_ppu_reenable_work);
+drivers/net/dsa/mv88e6xxx/phy.c:	timer_setup(&chip->ppu_timer, mv88e6xxx_phy_ppu_reenable_timer, 0);
+drivers/net/dsa/mv88e6xxx/phy.c:	del_timer_sync(&chip->ppu_timer);
+drivers/net/dsa/mv88e6xxx/phy.c:	if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable)
+drivers/net/dsa/mv88e6xxx/phy.c:	if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable)
+drivers/net/dsa/mv88e6xxx/port.c:	int addr = chip->info->port_base_addr + port;
+drivers/net/dsa/mv88e6xxx/port.c:	int addr = chip->info->port_base_addr + port;
+drivers/net/dsa/mv88e6xxx/port.c:	dev_dbg(chip->dev, "p%d: delay RXCLK %s, TXCLK %s\n", port,
+drivers/net/dsa/mv88e6xxx/port.c:	dev_dbg(chip->dev, "p%d: %s link %s\n", port,
+drivers/net/dsa/mv88e6xxx/port.c:	dev_dbg(chip->dev, "p%d: %s %s duplex\n", port,
+drivers/net/dsa/mv88e6xxx/port.c:		dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed);
+drivers/net/dsa/mv88e6xxx/port.c:		dev_dbg(chip->dev, "p%d: Speed unforced\n", port);
+drivers/net/dsa/mv88e6xxx/port.c:	if (cmode == chip->ports[port].cmode)
+drivers/net/dsa/mv88e6xxx/port.c:		if (chip->ports[port].serdes_irq) {
+drivers/net/dsa/mv88e6xxx/port.c:	chip->ports[port].cmode = 0;
+drivers/net/dsa/mv88e6xxx/port.c:		chip->ports[port].cmode = cmode;
+drivers/net/dsa/mv88e6xxx/port.c:		if (chip->ports[port].serdes_irq) {
+drivers/net/dsa/mv88e6xxx/port.c:	addr = chip->info->port_base_addr + port;
+drivers/net/dsa/mv88e6xxx/port.c:	switch (chip->ports[port].cmode) {
+drivers/net/dsa/mv88e6xxx/port.c:		u8 cmode = chip->ports[port].cmode;
+drivers/net/dsa/mv88e6xxx/port.c:	dev_dbg(chip->dev, "p%d: PortState set to %s\n", port,
+drivers/net/dsa/mv88e6xxx/port.c:	dev_dbg(chip->dev, "p%d: VLANTable set to %.3x\n", port, map);
+drivers/net/dsa/mv88e6xxx/port.c:	dev_dbg(chip->dev, "p%d: FID set to %u\n", port, fid);
+drivers/net/dsa/mv88e6xxx/port.c:	dev_dbg(chip->dev, "p%d: DefaultVID set to %u\n", port, pvid);
+drivers/net/dsa/mv88e6xxx/port.c:		mirror_port = &chip->ports[port].mirror_ingress;
+drivers/net/dsa/mv88e6xxx/port.c:		mirror_port = &chip->ports[port].mirror_egress;
+drivers/net/dsa/mv88e6xxx/port.c:	dev_dbg(chip->dev, "p%d: 802.1QMode set to %s\n", port,
+drivers/net/dsa/mv88e6xxx/ptp.c:	if (!chip->info->ops->avb_ops->tai_read)
+drivers/net/dsa/mv88e6xxx/ptp.c:	return chip->info->ops->avb_ops->tai_read(chip, addr, data, len);
+drivers/net/dsa/mv88e6xxx/ptp.c:	if (!chip->info->ops->avb_ops->tai_write)
+drivers/net/dsa/mv88e6xxx/ptp.c:	return chip->info->ops->avb_ops->tai_write(chip, addr, data);
+drivers/net/dsa/mv88e6xxx/ptp.c:	if (!chip->info->ops->gpio_ops)
+drivers/net/dsa/mv88e6xxx/ptp.c:	err = chip->info->ops->gpio_ops->set_dir(chip, pin, input);
+drivers/net/dsa/mv88e6xxx/ptp.c:	return chip->info->ops->gpio_ops->set_pctl(chip, pin, func);
+drivers/net/dsa/mv88e6xxx/ptp.c:	chip->evcap_config = MV88E6XXX_TAI_CFG_CAP_OVERWRITE |
+drivers/net/dsa/mv88e6xxx/ptp.c:		chip->evcap_config |= MV88E6XXX_TAI_CFG_EVREQ_FALLING;
+drivers/net/dsa/mv88e6xxx/ptp.c:	global_config = (chip->evcap_config | chip->trig_config);
+drivers/net/dsa/mv88e6xxx/ptp.c:		dev_err(chip->dev, "failed to read TAI status register\n");
+drivers/net/dsa/mv88e6xxx/ptp.c:		dev_warn(chip->dev, "missed event capture\n");
+drivers/net/dsa/mv88e6xxx/ptp.c:	ev.timestamp = timecounter_cyc2time(&chip->tstamp_tc, raw_ts);
+drivers/net/dsa/mv88e6xxx/ptp.c:	ptp_clock_event(chip->ptp_clock, &ev);
+drivers/net/dsa/mv88e6xxx/ptp.c:	schedule_delayed_work(&chip->tai_event_work, TAI_EVENT_WORK_INTERVAL);
+drivers/net/dsa/mv88e6xxx/ptp.c:	const struct mv88e6xxx_ptp_ops *ptp_ops = chip->info->ops->ptp_ops;
+drivers/net/dsa/mv88e6xxx/ptp.c:	timecounter_read(&chip->tstamp_tc);
+drivers/net/dsa/mv88e6xxx/ptp.c:	chip->tstamp_cc.mult = neg_adj ? mult - diff : mult + diff;
+drivers/net/dsa/mv88e6xxx/ptp.c:	timecounter_adjtime(&chip->tstamp_tc, delta);
+drivers/net/dsa/mv88e6xxx/ptp.c:	ns = timecounter_read(&chip->tstamp_tc);
+drivers/net/dsa/mv88e6xxx/ptp.c:	timecounter_init(&chip->tstamp_tc, &chip->tstamp_cc, ns);
+drivers/net/dsa/mv88e6xxx/ptp.c:	pin = ptp_find_pin(chip->ptp_clock, PTP_PF_EXTTS, rq->extts.index);
+drivers/net/dsa/mv88e6xxx/ptp.c:		schedule_delayed_work(&chip->tai_event_work,
+drivers/net/dsa/mv88e6xxx/ptp.c:		cancel_delayed_work_sync(&chip->tai_event_work);
+drivers/net/dsa/mv88e6xxx/ptp.c:	if (chip->info->ops->ptp_ops->clock_read)
+drivers/net/dsa/mv88e6xxx/ptp.c:		return chip->info->ops->ptp_ops->clock_read(cc);
+drivers/net/dsa/mv88e6xxx/ptp.c:	mv88e6xxx_ptp_gettime(&chip->ptp_clock_info, &ts);
+drivers/net/dsa/mv88e6xxx/ptp.c:	schedule_delayed_work(&chip->overflow_work,
+drivers/net/dsa/mv88e6xxx/ptp.c:	const struct mv88e6xxx_ptp_ops *ptp_ops = chip->info->ops->ptp_ops;
+drivers/net/dsa/mv88e6xxx/ptp.c:	memset(&chip->tstamp_cc, 0, sizeof(chip->tstamp_cc));
+drivers/net/dsa/mv88e6xxx/ptp.c:	chip->tstamp_cc.read	= mv88e6xxx_ptp_clock_read;
+drivers/net/dsa/mv88e6xxx/ptp.c:	chip->tstamp_cc.mask	= CYCLECOUNTER_MASK(32);
+drivers/net/dsa/mv88e6xxx/ptp.c:	chip->tstamp_cc.mult	= ptp_ops->cc_mult;
+drivers/net/dsa/mv88e6xxx/ptp.c:	chip->tstamp_cc.shift	= ptp_ops->cc_shift;
+drivers/net/dsa/mv88e6xxx/ptp.c:	timecounter_init(&chip->tstamp_tc, &chip->tstamp_cc,
+drivers/net/dsa/mv88e6xxx/ptp.c:	INIT_DELAYED_WORK(&chip->overflow_work, mv88e6xxx_ptp_overflow_check);
+drivers/net/dsa/mv88e6xxx/ptp.c:		INIT_DELAYED_WORK(&chip->tai_event_work, ptp_ops->event_work);
+drivers/net/dsa/mv88e6xxx/ptp.c:	chip->ptp_clock_info.owner = THIS_MODULE;
+drivers/net/dsa/mv88e6xxx/ptp.c:	snprintf(chip->ptp_clock_info.name, sizeof(chip->ptp_clock_info.name),
+drivers/net/dsa/mv88e6xxx/ptp.c:		 "%s", dev_name(chip->dev));
+drivers/net/dsa/mv88e6xxx/ptp.c:	chip->ptp_clock_info.n_ext_ts	= ptp_ops->n_ext_ts;
+drivers/net/dsa/mv88e6xxx/ptp.c:	chip->ptp_clock_info.n_per_out	= 0;
+drivers/net/dsa/mv88e6xxx/ptp.c:	chip->ptp_clock_info.n_pins	= mv88e6xxx_num_gpio(chip);
+drivers/net/dsa/mv88e6xxx/ptp.c:	chip->ptp_clock_info.pps	= 0;
+drivers/net/dsa/mv88e6xxx/ptp.c:	for (i = 0; i < chip->ptp_clock_info.n_pins; ++i) {
+drivers/net/dsa/mv88e6xxx/ptp.c:		struct ptp_pin_desc *ppd = &chip->pin_config[i];
+drivers/net/dsa/mv88e6xxx/ptp.c:	chip->ptp_clock_info.pin_config = chip->pin_config;
+drivers/net/dsa/mv88e6xxx/ptp.c:	chip->ptp_clock_info.max_adj    = MV88E6XXX_MAX_ADJ_PPB;
+drivers/net/dsa/mv88e6xxx/ptp.c:	chip->ptp_clock_info.adjfine	= mv88e6xxx_ptp_adjfine;
+drivers/net/dsa/mv88e6xxx/ptp.c:	chip->ptp_clock_info.adjtime	= mv88e6xxx_ptp_adjtime;
+drivers/net/dsa/mv88e6xxx/ptp.c:	chip->ptp_clock_info.gettime64	= mv88e6xxx_ptp_gettime;
+drivers/net/dsa/mv88e6xxx/ptp.c:	chip->ptp_clock_info.settime64	= mv88e6xxx_ptp_settime;
+drivers/net/dsa/mv88e6xxx/ptp.c:	chip->ptp_clock_info.enable	= ptp_ops->ptp_enable;
+drivers/net/dsa/mv88e6xxx/ptp.c:	chip->ptp_clock_info.verify	= ptp_ops->ptp_verify;
+drivers/net/dsa/mv88e6xxx/ptp.c:	chip->ptp_clock_info.do_aux_work = mv88e6xxx_hwtstamp_work;
+drivers/net/dsa/mv88e6xxx/ptp.c:	chip->ptp_clock = ptp_clock_register(&chip->ptp_clock_info, chip->dev);
+drivers/net/dsa/mv88e6xxx/ptp.c:	if (IS_ERR(chip->ptp_clock))
+drivers/net/dsa/mv88e6xxx/ptp.c:		return PTR_ERR(chip->ptp_clock);
+drivers/net/dsa/mv88e6xxx/ptp.c:	schedule_delayed_work(&chip->overflow_work,
+drivers/net/dsa/mv88e6xxx/ptp.c:	if (chip->ptp_clock) {
+drivers/net/dsa/mv88e6xxx/ptp.c:		cancel_delayed_work_sync(&chip->overflow_work);
+drivers/net/dsa/mv88e6xxx/ptp.c:		if (chip->info->ops->ptp_ops->event_work)
+drivers/net/dsa/mv88e6xxx/ptp.c:			cancel_delayed_work_sync(&chip->tai_event_work);
+drivers/net/dsa/mv88e6xxx/ptp.c:		ptp_clock_unregister(chip->ptp_clock);
+drivers/net/dsa/mv88e6xxx/ptp.c:		chip->ptp_clock = NULL;
+drivers/net/dsa/mv88e6xxx/serdes.c:	u8 cmode = chip->ports[port].cmode;
+drivers/net/dsa/mv88e6xxx/serdes.c:		dev_err(chip->dev, "failed to read statistic\n");
+drivers/net/dsa/mv88e6xxx/serdes.c:			dev_err(chip->dev, "failed to read statistic\n");
+drivers/net/dsa/mv88e6xxx/serdes.c:	struct mv88e6xxx_port *mv88e6xxx_port = &chip->ports[port];
+drivers/net/dsa/mv88e6xxx/serdes.c:	struct dsa_switch *ds = chip->ds;
+drivers/net/dsa/mv88e6xxx/serdes.c:	return irq_find_mapping(chip->g2_irq.domain, MV88E6352_SERDES_IRQ);
+drivers/net/dsa/mv88e6xxx/serdes.c:	u8 cmode = chip->ports[port].cmode;
+drivers/net/dsa/mv88e6xxx/serdes.c:	u8 cmode = chip->ports[port].cmode;
+drivers/net/dsa/mv88e6xxx/serdes.c:	u8 cmode_port = chip->ports[port].cmode;
+drivers/net/dsa/mv88e6xxx/serdes.c:	u8 cmode_port10 = chip->ports[10].cmode;
+drivers/net/dsa/mv88e6xxx/serdes.c:	u8 cmode_port9 = chip->ports[9].cmode;
+drivers/net/dsa/mv88e6xxx/serdes.c:	u8 cmode = chip->ports[port].cmode;
+drivers/net/dsa/mv88e6xxx/serdes.c:	u8 cmode = chip->ports[port].cmode;
+drivers/net/dsa/mv88e6xxx/serdes.c:	struct dsa_switch *ds = chip->ds;
+drivers/net/dsa/mv88e6xxx/serdes.c:		dev_err(chip->dev, "can't read SGMII PHY status: %d\n", err);
+drivers/net/dsa/mv88e6xxx/serdes.c:			dev_err(chip->dev, "invalid PHY speed\n");
+drivers/net/dsa/mv88e6xxx/serdes.c:		dev_err(chip->dev, "can't propagate PHY settings to MAC: %d\n",
+drivers/net/dsa/mv88e6xxx/serdes.c:	u8 cmode = chip->ports[port].cmode;
+drivers/net/dsa/mv88e6xxx/serdes.c:	u8 cmode = chip->ports[port].cmode;
+drivers/net/dsa/mv88e6xxx/serdes.c:	return irq_find_mapping(chip->g2_irq.domain, port);
+drivers/net/dsa/mv88e6xxx/serdes.h:	if (!chip->info->ops->serdes_get_lane)
+drivers/net/dsa/mv88e6xxx/serdes.h:	return chip->info->ops->serdes_get_lane(chip, port);
+drivers/net/dsa/mv88e6xxx/serdes.h:	if (!chip->info->ops->serdes_power)
+drivers/net/dsa/mv88e6xxx/serdes.h:	return chip->info->ops->serdes_power(chip, port, lane, true);
+drivers/net/dsa/mv88e6xxx/serdes.h:	if (!chip->info->ops->serdes_power)
+drivers/net/dsa/mv88e6xxx/serdes.h:	return chip->info->ops->serdes_power(chip, port, lane, false);
+drivers/net/dsa/mv88e6xxx/serdes.h:	if (!chip->info->ops->serdes_irq_mapping)
+drivers/net/dsa/mv88e6xxx/serdes.h:	return chip->info->ops->serdes_irq_mapping(chip, port);
+drivers/net/dsa/mv88e6xxx/serdes.h:	if (!chip->info->ops->serdes_irq_enable)
+drivers/net/dsa/mv88e6xxx/serdes.h:	return chip->info->ops->serdes_irq_enable(chip, port, lane, true);
+drivers/net/dsa/mv88e6xxx/serdes.h:	if (!chip->info->ops->serdes_irq_enable)
+drivers/net/dsa/mv88e6xxx/serdes.h:	return chip->info->ops->serdes_irq_enable(chip, port, lane, false);
+drivers/net/dsa/mv88e6xxx/serdes.h:	if (!chip->info->ops->serdes_irq_status)
+drivers/net/dsa/mv88e6xxx/serdes.h:	return chip->info->ops->serdes_irq_status(chip, port, lane);
+drivers/net/dsa/mv88e6xxx/smi.c:	ret = mdiobus_read_nested(chip->bus, dev, reg);
+drivers/net/dsa/mv88e6xxx/smi.c:	ret = mdiobus_write_nested(chip->bus, dev, reg, data);
+drivers/net/dsa/mv88e6xxx/smi.c:	return mv88e6xxx_smi_direct_read(chip, chip->sw_addr + dev, reg, data);
+drivers/net/dsa/mv88e6xxx/smi.c:	return mv88e6xxx_smi_direct_write(chip, chip->sw_addr + dev, reg, data);
+drivers/net/dsa/mv88e6xxx/smi.c:	err = mv88e6xxx_smi_direct_wait(chip, chip->sw_addr,
+drivers/net/dsa/mv88e6xxx/smi.c:	err = mv88e6xxx_smi_direct_write(chip, chip->sw_addr,
+drivers/net/dsa/mv88e6xxx/smi.c:	err = mv88e6xxx_smi_direct_wait(chip, chip->sw_addr,
+drivers/net/dsa/mv88e6xxx/smi.c:	return mv88e6xxx_smi_direct_read(chip, chip->sw_addr,
+drivers/net/dsa/mv88e6xxx/smi.c:	err = mv88e6xxx_smi_direct_wait(chip, chip->sw_addr,
+drivers/net/dsa/mv88e6xxx/smi.c:	err = mv88e6xxx_smi_direct_write(chip, chip->sw_addr,
+drivers/net/dsa/mv88e6xxx/smi.c:	err = mv88e6xxx_smi_direct_write(chip, chip->sw_addr,
+drivers/net/dsa/mv88e6xxx/smi.c:	return mv88e6xxx_smi_direct_wait(chip, chip->sw_addr,
+drivers/net/dsa/mv88e6xxx/smi.c:	if (chip->info->dual_chip)
+drivers/net/dsa/mv88e6xxx/smi.c:		chip->smi_ops = &mv88e6xxx_smi_dual_direct_ops;
+drivers/net/dsa/mv88e6xxx/smi.c:		chip->smi_ops = &mv88e6xxx_smi_direct_ops;
+drivers/net/dsa/mv88e6xxx/smi.c:	else if (chip->info->multi_chip)
+drivers/net/dsa/mv88e6xxx/smi.c:		chip->smi_ops = &mv88e6xxx_smi_indirect_ops;
+drivers/net/dsa/mv88e6xxx/smi.c:	chip->bus = bus;
+drivers/net/dsa/mv88e6xxx/smi.c:	chip->sw_addr = sw_addr;
+drivers/net/dsa/mv88e6xxx/smi.h:	if (chip->smi_ops && chip->smi_ops->read)
+drivers/net/dsa/mv88e6xxx/smi.h:		return chip->smi_ops->read(chip, dev, reg, data);
+drivers/net/dsa/mv88e6xxx/smi.h:	if (chip->smi_ops && chip->smi_ops->write)
+drivers/net/dsa/mv88e6xxx/smi.h:		return chip->smi_ops->write(chip, dev, reg, data);
+drivers/net/ethernet/3com/typhoon.c:	/* The chip-specific entries in the device structure. */
+drivers/net/ethernet/8390/axnet_cs.c:  This is the chip-specific code for many 8390-based ethernet adaptors.
+drivers/net/ethernet/8390/lib8390.c:  This is the chip-specific code for many 8390-based ethernet adaptors.
+drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c: * bnx2x_func_init_cmn_chip - performs HW init at chip-common stage
+drivers/net/ethernet/broadcom/tg3.c:	 * chip-internal interrupt pending events.
+drivers/net/ethernet/broadcom/tg3.c:	 * chip-internal interrupt pending events.
+drivers/net/ethernet/broadcom/tg3.c:	 * chip-internal interrupt pending events.
+drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c:	/* Initiate chip-wide soft reset */
+drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c:/* 10Gb/s-BT PHY Support. chip-external 10Gb/s-BT PHYs are complex chips
+drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c:/* Handle updating of chip-external 10Gb/s-BT PHY firmware.  This needs to
+drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c:	/* If this is a 10Gb/s-BT adapter make sure the chip-external
+drivers/net/ethernet/dec/tulip/winbond-840.c:	/* The chip-specific entries in the device structure. */
+drivers/net/ethernet/dlink/sundance.c:	/* The chip-specific entries in the device structure. */
+drivers/net/ethernet/intel/ixgbe/ixgbe_type.h:#define IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK	0xFF01 /* int chip-wide mask */
+drivers/net/ethernet/intel/ixgbe/ixgbe_type.h:#define IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG	0xFC01 /* int chip-wide mask */
+drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c:	/* Enable chip-wide vendor alarm */
+drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp.h: * @ports.index:	chip-wide first channel index
+drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c: * @idx:	NFP chip-wide port index
+drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c: * @idx:	NFP chip-wide port index
+drivers/net/ethernet/netronome/nfp/nfpcore/nfp_nsp_eth.c: * @idx:	NFP chip-wide port index
+drivers/net/ethernet/smsc/smc9194.c: .    Attempt to allocate memory for a packet, if chip-memory is not
+drivers/net/ethernet/smsc/smc9194.c: . chip-memory.
+drivers/net/ethernet/via/via-rhine.c:	/* The chip-specific entries in the device structure. */
+drivers/net/phy/microchip.c:#include <dt-bindings/net/microchip-lan78xx.h>
+drivers/net/phy/spi_ks8995.c:	result <<= ks->chip->addr_width + ks->chip->addr_shift;
+drivers/net/phy/spi_ks8995.c:	result |= address << ks->chip->addr_shift;
+drivers/net/phy/spi_ks8995.c:	if (id0 != ks->chip->family_id) {
+drivers/net/phy/spi_ks8995.c:			ks->chip->family_id, id0);
+drivers/net/phy/spi_ks8995.c:	switch (ks->chip->family_id) {
+drivers/net/phy/spi_ks8995.c:		    (get_chip_id(id1) == ks->chip->chip_id)) {
+drivers/net/phy/spi_ks8995.c:			    (ks->chip->chip_id == KSZ8864_CHIP_ID)) {
+drivers/net/phy/spi_ks8995.c:		if (get_chip_id(id1) == ks->chip->chip_id) {
+drivers/net/phy/spi_ks8995.c:	ks->regs_attr.size = ks->chip->regs_size;
+drivers/net/phy/spi_ks8995.c:		 ks->chip->name, ks->chip->chip_id, ks->revision_id);
+drivers/net/usb/cdc_subset.c: * well tends to require chip-specific vendor requests.  Also, Windows
+drivers/net/usb/sr9700.c:MODULE_DESCRIPTION("SR9700 one chip USB 1.1 USB to Ethernet device from http://www.corechip-sz.com/");
+drivers/net/usb/sr9800.c:MODULE_DESCRIPTION("SR9800 USB 2.0 USB2NET Dev : http://www.corechip-sz.com");
+drivers/net/wireless/ath/ath10k/core.c:			  "bus=%s,bmi-chip-id=%d,bmi-board-id=%d%s",
+drivers/net/wireless/ath/ath10k/core.c:			  "bus=%s,bmi-chip-id=%d,bmi-eboard-id=%d",
+drivers/net/wireless/ath/ath10k/pci.c:		if (supp_chip->dev_id == dev_id &&
+drivers/net/wireless/ath/ath10k/pci.c:		    supp_chip->rev_id == rev_id)
+drivers/net/wireless/ath/ath5k/initvals.c: * ath5k_hw_write_initvals() - Write initial chip-specific register dump
+drivers/net/wireless/ath/ath5k/initvals.c: * Write initial chip-specific register dump, to get the chipset on a
+drivers/net/wireless/ath/ath5k/phy.c:	/* Bank Modifications (chip-specific) */
+drivers/net/wireless/ath/ath9k/ar9003_phy.c:		/* disable IRQ, disable chip-reset for BB panic */
+drivers/net/wireless/ath/ath9k/ar9003_phy.c:	/* enable IRQ, disable chip-reset for BB watchdog */
+drivers/net/wireless/broadcom/b43/main.c:	 * the chip-internal counter. */
+drivers/net/wireless/broadcom/b43legacy/main.c:	 * the chip-internal counter. */
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:	return core->chip->ops->read32(core->chip->ctx, core->pub.base + reg);
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:	core->chip->ops->write32(core->chip->ctx, core->pub.base + reg, val);
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:	switch (sr->chip->pub.chip) {
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:		if (sr->chip->pub.chiprev < 2)
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:	core = brcmf_chip_get_core(&chip->pub, id);
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:		val = chip->ops->read32(chip->ctx, cpu->wrapbase + BCMA_IOCTL);
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:	pub = &chip->pub;
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:	cc = list_first_entry(&chip->cores, struct brcmf_core_priv, list);
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:	pub->cc_caps = chip->ops->read32(chip->ctx,
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:	pub->cc_caps_ext = chip->ops->read32(chip->ctx,
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:		val = chip->ops->read32(chip->ctx,
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:	if (chip->ops->setup)
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:		ret = chip->ops->setup(chip->ctx, pub);
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:	INIT_LIST_HEAD(&chip->cores);
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:	chip->num_cores = 0;
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:	chip->ops = ops;
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:	chip->ctx = ctx;
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:	return &chip->pub;
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:	brcmf_chip_detach(&chip->pub);
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:	list_for_each_entry_safe(core, tmp, &chip->cores, list) {
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:	list_for_each_entry(core, &chip->cores, list)
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:	cc = list_first_entry(&chip->cores, struct brcmf_core_priv, list);
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:	return core->chip->iscoreup(core);
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:	core->chip->coredisable(core, prereset, reset);
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:	core->chip->resetcore(core, prereset, reset, postreset);
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:	core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_80211);
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:	core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_INTERNAL_MEM);
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:	if (chip->pub.chip == BRCM_CC_43430_CHIP_ID) {
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:	core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_INTERNAL_MEM);
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:	chip->ops->activate(chip->ctx, &chip->pub, 0);
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:	core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CM3);
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:	core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_80211);
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:	chip->ops->activate(chip->ctx, &chip->pub, rstvec);
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:	core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CR4);
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:	core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_80211);
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:	chip->ops->activate(chip->ctx, &chip->pub, rstvec);
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:	core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CA7);
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:		chip->ops->write32(chip->ctx, addr, 3);
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:		reg = chip->ops->read32(chip->ctx, addr);
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:		reg = chip->ops->read32(chip->ctx, addr);
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:		reg = chip->ops->read32(chip->ctx, addr);
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:		reg = chip->ops->read32(chip->ctx, addr);
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:		reg = chip->ops->read32(chip->ctx, addr);
+drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c:		reg = chip->ops->read32(chip->ctx, addr);
+drivers/net/wireless/broadcom/brcm80211/brcmsmac/aiutils.c:/* 43224 chip-specific ChipControl register bits */
+drivers/net/wireless/broadcom/brcm80211/brcmsmac/aiutils.c:/* 4331 chip-specific ChipControl register bits */
+drivers/net/wireless/broadcom/brcm80211/brcmsmac/aiutils.c:/* 4319 chip-specific ChipStatus register bits */
+drivers/net/wireless/broadcom/brcm80211/brcmsmac/aiutils.c:/* 4336 chip-specific ChipStatus register bits */
+drivers/net/wireless/broadcom/brcm80211/brcmsmac/aiutils.c:/* 4313 chip-specific ChipStatus register bits */
+drivers/net/wireless/realtek/rtw88/bf.c:	chip->ops->config_bfee(rtwdev, rtwvif, bfee, false);
+drivers/net/wireless/realtek/rtw88/bf.c:	if (!(chip->band & RTW_BAND_5G))
+drivers/net/wireless/realtek/rtw88/bf.c:		if (bfinfo->bfer_mu_cnt >= chip->bfer_mu_max_num) {
+drivers/net/wireless/realtek/rtw88/bf.c:		chip->ops->config_bfee(rtwdev, rtwvif, bfee, true);
+drivers/net/wireless/realtek/rtw88/bf.c:		if (bfinfo->bfer_su_cnt >= chip->bfer_su_max_num) {
+drivers/net/wireless/realtek/rtw88/bf.c:		for (i = 0; i < chip->bfer_su_max_num; i++) {
+drivers/net/wireless/realtek/rtw88/bf.c:		chip->ops->config_bfee(rtwdev, rtwvif, bfee, true);
+drivers/net/wireless/realtek/rtw88/coex.c:	u8 tol = chip->rssi_tolerance;
+drivers/net/wireless/realtek/rtw88/coex.c:	if (!chip->scbd_support)
+drivers/net/wireless/realtek/rtw88/coex.c:	if (!chip->scbd_support)
+drivers/net/wireless/realtek/rtw88/coex.c:	if (!chip->new_scbd10_def && (bitpos & COEX_SCBD_FIX2M)) {
+drivers/net/wireless/realtek/rtw88/coex.c:	if (!chip->scbd_support)
+drivers/net/wireless/realtek/rtw88/coex.c:	if (coex_rfe->wlg_at_btg && chip->scbd_support &&
+drivers/net/wireless/realtek/rtw88/coex.c:	if (chip->scbd_support) {
+drivers/net/wireless/realtek/rtw88/coex.c:		rssi_step = chip->wl_rssi_step[i];
+drivers/net/wireless/realtek/rtw88/coex.c:		rssi_step = chip->bt_rssi_step[i];
+drivers/net/wireless/realtek/rtw88/coex.c:		rssi_step = chip->wl_rssi_step[i];
+drivers/net/wireless/realtek/rtw88/coex.c:			bw = chip->bt_afh_span_bw40;
+drivers/net/wireless/realtek/rtw88/coex.c:			bw = chip->bt_afh_span_bw20;
+drivers/net/wireless/realtek/rtw88/coex.c:	} else if (chip->afh_5g_num > 1) {
+drivers/net/wireless/realtek/rtw88/coex.c:		for (i = 0; i < chip->afh_5g_num; i++) {
+drivers/net/wireless/realtek/rtw88/coex.c:			if (center_chan == chip->afh_5g[i].wl_5g_ch) {
+drivers/net/wireless/realtek/rtw88/coex.c:				center_chan = chip->afh_5g[i].bt_skip_ch;
+drivers/net/wireless/realtek/rtw88/coex.c:				bw = chip->afh_5g[i].bt_skip_span;
+drivers/net/wireless/realtek/rtw88/coex.c:		if (type < chip->table_sant_num)
+drivers/net/wireless/realtek/rtw88/coex.c:					   chip->table_sant[type].bt,
+drivers/net/wireless/realtek/rtw88/coex.c:					   chip->table_sant[type].wl);
+drivers/net/wireless/realtek/rtw88/coex.c:		if (type < chip->table_nsant_num)
+drivers/net/wireless/realtek/rtw88/coex.c:					   chip->table_nsant[type].bt,
+drivers/net/wireless/realtek/rtw88/coex.c:					   chip->table_nsant[type].wl);
+drivers/net/wireless/realtek/rtw88/coex.c:		if (chip->pstdma_type == COEX_PSTDMA_FORCE_LPSOFF)
+drivers/net/wireless/realtek/rtw88/coex.c:		if (type < chip->tdma_sant_num)
+drivers/net/wireless/realtek/rtw88/coex.c:					  chip->tdma_sant[type].para[0],
+drivers/net/wireless/realtek/rtw88/coex.c:					  chip->tdma_sant[type].para[1],
+drivers/net/wireless/realtek/rtw88/coex.c:					  chip->tdma_sant[type].para[2],
+drivers/net/wireless/realtek/rtw88/coex.c:					  chip->tdma_sant[type].para[3],
+drivers/net/wireless/realtek/rtw88/coex.c:					  chip->tdma_sant[type].para[4]);
+drivers/net/wireless/realtek/rtw88/coex.c:		if (n < chip->tdma_nsant_num)
+drivers/net/wireless/realtek/rtw88/coex.c:					  chip->tdma_nsant[n].para[0],
+drivers/net/wireless/realtek/rtw88/coex.c:					  chip->tdma_nsant[n].para[1],
+drivers/net/wireless/realtek/rtw88/coex.c:					  chip->tdma_nsant[n].para[2],
+drivers/net/wireless/realtek/rtw88/coex.c:					  chip->tdma_nsant[n].para[3],
+drivers/net/wireless/realtek/rtw88/coex.c:					  chip->tdma_nsant[n].para[4]);
+drivers/net/wireless/realtek/rtw88/coex.c:	rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
+drivers/net/wireless/realtek/rtw88/coex.c:	if (level > chip->wl_rf_para_num - 1)
+drivers/net/wireless/realtek/rtw88/coex.c:		level = chip->wl_rf_para_num - 1;
+drivers/net/wireless/realtek/rtw88/coex.c:		rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_tx[level]);
+drivers/net/wireless/realtek/rtw88/coex.c:		rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[level]);
+drivers/net/wireless/realtek/rtw88/coex.c:	rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
+drivers/net/wireless/realtek/rtw88/coex.c:	rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
+drivers/net/wireless/realtek/rtw88/coex.c:	rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
+drivers/net/wireless/realtek/rtw88/coex.c:	rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
+drivers/net/wireless/realtek/rtw88/coex.c:	rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
+drivers/net/wireless/realtek/rtw88/coex.c:	rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
+drivers/net/wireless/realtek/rtw88/coex.c:	rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
+drivers/net/wireless/realtek/rtw88/coex.c:	rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
+drivers/net/wireless/realtek/rtw88/coex.c:	rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
+drivers/net/wireless/realtek/rtw88/coex.c:	rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
+drivers/net/wireless/realtek/rtw88/coex.c:	rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
+drivers/net/wireless/realtek/rtw88/coex.c:	rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
+drivers/net/wireless/realtek/rtw88/coex.c:	rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
+drivers/net/wireless/realtek/rtw88/coex.c:	rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
+drivers/net/wireless/realtek/rtw88/coex.c:	rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
+drivers/net/wireless/realtek/rtw88/coex.c:	rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
+drivers/net/wireless/realtek/rtw88/coex.c:	rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
+drivers/net/wireless/realtek/rtw88/coex.c:	rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
+drivers/net/wireless/realtek/rtw88/coex.c:	if (chip->bt_rssi_type == COEX_BTRSSI_RATIO) {
+drivers/net/wireless/realtek/rtw88/coex.h:	chip->ops->coex_set_init(rtwdev);
+drivers/net/wireless/realtek/rtw88/coex.h:	if (!chip->ops->coex_set_ant_switch)
+drivers/net/wireless/realtek/rtw88/coex.h:	chip->ops->coex_set_ant_switch(rtwdev, ctrl_type, pos_type);
+drivers/net/wireless/realtek/rtw88/coex.h:	chip->ops->coex_set_gnt_fix(rtwdev);
+drivers/net/wireless/realtek/rtw88/coex.h:	chip->ops->coex_set_gnt_debug(rtwdev);
+drivers/net/wireless/realtek/rtw88/coex.h:	chip->ops->coex_set_rfe_type(rtwdev);
+drivers/net/wireless/realtek/rtw88/coex.h:	chip->ops->coex_set_wl_tx_power(rtwdev, wl_pwr);
+drivers/net/wireless/realtek/rtw88/coex.h:	chip->ops->coex_set_wl_rx_gain(rtwdev, low_gain);
+drivers/net/wireless/realtek/rtw88/debug.c:	u8 page_size = rtwdev->chip->page_size;
+drivers/net/wireless/realtek/rtw88/debug.c:	if (rtwdev->chip->id == RTW_CHIP_TYPE_8822C) {
+drivers/net/wireless/realtek/rtw88/efuse.c:	chip->ops->cfg_ldo25(rtwdev, false);
+drivers/net/wireless/realtek/rtw88/efuse.c:	ret = chip->ops->read_efuse(rtwdev, log_map);
+drivers/net/wireless/realtek/rtw88/fw.c:	size = chip->tx_pkt_desc_sz + sizeof(*dpk_hdr);
+drivers/net/wireless/realtek/rtw88/fw.c:	skb_reserve(skb, chip->tx_pkt_desc_sz);
+drivers/net/wireless/realtek/rtw88/fw.c:	size = chip->tx_pkt_desc_sz + sizeof(*pg_info_hdr);
+drivers/net/wireless/realtek/rtw88/fw.c:	skb_reserve(skb, chip->tx_pkt_desc_sz);
+drivers/net/wireless/realtek/rtw88/fw.c:	pkt_desc = skb_push(skb, chip->tx_pkt_desc_sz);
+drivers/net/wireless/realtek/rtw88/fw.c:	memset(pkt_desc, 0, chip->tx_pkt_desc_sz);
+drivers/net/wireless/realtek/rtw88/fw.c:	pg_size = rtwdev->chip->page_size;
+drivers/net/wireless/realtek/rtw88/fw.c:	page_size = chip->page_size;
+drivers/net/wireless/realtek/rtw88/fw.c:	tx_desc_sz = chip->tx_pkt_desc_sz;
+drivers/net/wireless/realtek/rtw88/hci.h:	val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask);
+drivers/net/wireless/realtek/rtw88/hci.h:	rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data);
+drivers/net/wireless/realtek/rtw88/mac.c:	pwr_seq = pwr_on ? chip->pwr_on_seq : chip->pwr_off_seq;
+drivers/net/wireless/realtek/rtw88/mac.c:	u8 sys_func_en = rtwdev->chip->sys_func_en;
+drivers/net/wireless/realtek/rtw88/mac.c:	u32 desc_size = chip->tx_pkt_desc_sz;
+drivers/net/wireless/realtek/rtw88/mac.c:		rqpn = &chip->rqpn_table[1];
+drivers/net/wireless/realtek/rtw88/mac.c:			rqpn = &chip->rqpn_table[2];
+drivers/net/wireless/realtek/rtw88/mac.c:			rqpn = &chip->rqpn_table[3];
+drivers/net/wireless/realtek/rtw88/mac.c:			rqpn = &chip->rqpn_table[4];
+drivers/net/wireless/realtek/rtw88/mac.c:	u8 csi_buf_pg_num = chip->csi_buf_pg_num;
+drivers/net/wireless/realtek/rtw88/mac.c:	fifo->txff_pg_num = chip->txff_size >> 7;
+drivers/net/wireless/realtek/rtw88/mac.c:		pg_tbl = &chip->page_table[1];
+drivers/net/wireless/realtek/rtw88/mac.c:			pg_tbl = &chip->page_table[2];
+drivers/net/wireless/realtek/rtw88/mac.c:			pg_tbl = &chip->page_table[3];
+drivers/net/wireless/realtek/rtw88/mac.c:			pg_tbl = &chip->page_table[4];
+drivers/net/wireless/realtek/rtw88/mac.c:	rtw_write32(rtwdev, REG_RXFF_BNDY, chip->rxff_size - C2H_PKT_BUF - 1);
+drivers/net/wireless/realtek/rtw88/mac.c:	ret = chip->ops->mac_init(rtwdev);
+drivers/net/wireless/realtek/rtw88/mac80211.c:			chip->ops->phy_calibration(rtwdev);
+drivers/net/wireless/realtek/rtw88/mac80211.c:		chip->ops->set_gid_table(rtwdev, vif, conf);
+drivers/net/wireless/realtek/rtw88/main.c:	chip->ops->cfg_csi_rate(rtwdev, rtwdev->dm_info.min_rssi,
+drivers/net/wireless/realtek/rtw88/main.c:	chip->ops->set_channel(rtwdev, center_chan, bandwidth, primary_chan_idx);
+drivers/net/wireless/realtek/rtw88/main.c:	chip->ops->phy_set_param(rtwdev);
+drivers/net/wireless/realtek/rtw88/main.c:	if (chip->band & RTW_BAND_2G) {
+drivers/net/wireless/realtek/rtw88/main.c:		if (chip->ht_supported)
+drivers/net/wireless/realtek/rtw88/main.c:	if (chip->band & RTW_BAND_5G) {
+drivers/net/wireless/realtek/rtw88/main.c:		if (chip->ht_supported)
+drivers/net/wireless/realtek/rtw88/main.c:		if (chip->vht_supported)
+drivers/net/wireless/realtek/rtw88/main.c:	efuse->physical_size = chip->phy_efuse_size;
+drivers/net/wireless/realtek/rtw88/main.c:	efuse->logical_size = chip->log_efuse_size;
+drivers/net/wireless/realtek/rtw88/main.c:	efuse->protect_size = chip->ptct_efuse_size;
+drivers/net/wireless/realtek/rtw88/main.c:	if (!(BIT(rtw_fw_lps_deep_mode) & chip->lps_deep_mode_supported))
+drivers/net/wireless/realtek/rtw88/main.c:	ret = rtw_load_firmware(rtwdev, rtwdev->chip->fw_name);
+drivers/net/wireless/realtek/rtw88/main.c:	max_tx_headroom = rtwdev->chip->tx_pkt_desc_sz;
+drivers/net/wireless/realtek/rtw88/pci.c:	tx_desc_size = chip->tx_buf_desc_sz;
+drivers/net/wireless/realtek/rtw88/pci.c:	rx_desc_size = chip->rx_buf_desc_sz;
+drivers/net/wireless/realtek/rtw88/pci.c:	u32 desc_sz = chip->rx_buf_desc_sz;
+drivers/net/wireless/realtek/rtw88/pci.c:	u32 tx_pkt_desc_sz = chip->tx_pkt_desc_sz;
+drivers/net/wireless/realtek/rtw88/pci.c:	u32 tx_buf_desc_sz = chip->tx_buf_desc_sz;
+drivers/net/wireless/realtek/rtw88/pci.c:	pkt_desc = skb_push(skb, chip->tx_pkt_desc_sz);
+drivers/net/wireless/realtek/rtw88/pci.c:	tx_pkt_desc_sz = rtwdev->chip->tx_pkt_desc_sz;
+drivers/net/wireless/realtek/rtw88/pci.c:	tx_pkt_desc_sz = rtwdev->chip->tx_pkt_desc_sz;
+drivers/net/wireless/realtek/rtw88/pci.c:		skb_pull(skb, rtwdev->chip->tx_pkt_desc_sz);
+drivers/net/wireless/realtek/rtw88/pci.c:	u32 pkt_desc_sz = chip->rx_pkt_desc_sz;
+drivers/net/wireless/realtek/rtw88/pci.c:	u32 buf_desc_sz = chip->rx_buf_desc_sz;
+drivers/net/wireless/realtek/rtw88/pci.c:		chip->ops->query_rx_desc(rtwdev, rx_desc, &pkt_stat, &rx_status);
+drivers/net/wireless/realtek/rtw88/pci.c:	for (i = 0; i < chip->intf_table->n_gen1_para; i++) {
+drivers/net/wireless/realtek/rtw88/pci.c:		para = &chip->intf_table->gen1_para[i];
+drivers/net/wireless/realtek/rtw88/pci.c:	for (i = 0; i < chip->intf_table->n_gen2_para; i++) {
+drivers/net/wireless/realtek/rtw88/pci.c:		para = &chip->intf_table->gen2_para[i];
+drivers/net/wireless/realtek/rtw88/phy.c:	addr = chip->dig[0].addr;
+drivers/net/wireless/realtek/rtw88/phy.c:	mask = chip->dig[0].mask;
+drivers/net/wireless/realtek/rtw88/phy.c:		addr = chip->dig[path].addr;
+drivers/net/wireless/realtek/rtw88/phy.c:		mask = chip->dig[path].mask;
+drivers/net/wireless/realtek/rtw88/phy.c:	chip->ops->false_alarm_statistics(rtwdev);
+drivers/net/wireless/realtek/rtw88/phy.c:	if (chip->ops->dpk_track)
+drivers/net/wireless/realtek/rtw88/phy.c:		chip->ops->dpk_track(rtwdev);
+drivers/net/wireless/realtek/rtw88/phy.c:	if (chip->ops->cck_pd_set)
+drivers/net/wireless/realtek/rtw88/phy.c:		chip->ops->cck_pd_set(rtwdev, level);
+drivers/net/wireless/realtek/rtw88/phy.c:	rtwdev->chip->ops->pwr_track(rtwdev);
+drivers/net/wireless/realtek/rtw88/phy.c:	const u32 *base_addr = chip->rf_base_addr;
+drivers/net/wireless/realtek/rtw88/phy.c:	u32 *sipi_addr = chip->rf_sipi_addr;
+drivers/net/wireless/realtek/rtw88/phy.c:	const u32 *base_addr = chip->rf_base_addr;
+drivers/net/wireless/realtek/rtw88/phy.c:	if (rtwdev->chip->is_pwr_by_rate_dec)
+drivers/net/wireless/realtek/rtw88/phy.c:	u8 max_power_index = rtwdev->chip->max_power_index;
+drivers/net/wireless/realtek/rtw88/phy.c:	u8 max_power_index = rtwdev->chip->max_power_index;
+drivers/net/wireless/realtek/rtw88/phy.c:	if (!chip->rfk_init_tbl)
+drivers/net/wireless/realtek/rtw88/phy.c:	rtw_load_table(rtwdev, chip->rfk_init_tbl);
+drivers/net/wireless/realtek/rtw88/phy.c:	rtw_load_table(rtwdev, chip->mac_tbl);
+drivers/net/wireless/realtek/rtw88/phy.c:	rtw_load_table(rtwdev, chip->bb_tbl);
+drivers/net/wireless/realtek/rtw88/phy.c:	rtw_load_table(rtwdev, chip->agc_tbl);
+drivers/net/wireless/realtek/rtw88/phy.c:		tbl = chip->rf_tbl[rf_path];
+drivers/net/wireless/realtek/rtw88/phy.c:	if (!chip->en_dis_dpd)
+drivers/net/wireless/realtek/rtw88/phy.c:	if (DIS_DPD_RATE ## _rate & chip->dpd_ratemask)			\
+drivers/net/wireless/realtek/rtw88/phy.c:		dpd_diff = -6 * chip->txgi_factor;			\
+drivers/net/wireless/realtek/rtw88/phy.c:	u8 factor = chip->txgi_factor;
+drivers/net/wireless/realtek/rtw88/phy.c:	u8 factor = chip->txgi_factor;
+drivers/net/wireless/realtek/rtw88/phy.c:	s8 power_limit = (s8)rtwdev->chip->max_power_index;
+drivers/net/wireless/realtek/rtw88/phy.c:	return (s8)rtwdev->chip->max_power_index;
+drivers/net/wireless/realtek/rtw88/phy.c:	if (rtwdev->chip->en_dis_dpd)
+drivers/net/wireless/realtek/rtw88/phy.c:	if (tx_power > rtwdev->chip->max_power_index)
+drivers/net/wireless/realtek/rtw88/phy.c:		tx_power = rtwdev->chip->max_power_index;
+drivers/net/wireless/realtek/rtw88/phy.c:	chip->ops->set_tx_power_index(rtwdev);
+drivers/net/wireless/realtek/rtw88/phy.c:	s8 max_power_index = (s8)rtwdev->chip->max_power_index;
+drivers/net/wireless/realtek/rtw88/phy.c:	const struct rtw_pwr_track_tbl *tbl = rtwdev->chip->pwr_track_tbl;
+drivers/net/wireless/realtek/rtw88/phy.c:	if (delta_iqk >= rtwdev->chip->iqk_threshold) {
+drivers/net/wireless/realtek/rtw88/phy.h:	if (chip->rfe_defs_size == 0)
+drivers/net/wireless/realtek/rtw88/phy.h:	if (efuse->rfe_option < chip->rfe_defs_size)
+drivers/net/wireless/realtek/rtw88/phy.h:		rfe_def = &chip->rfe_defs[efuse->rfe_option];
+drivers/net/wireless/realtek/rtw88/rtw8822b.c:	u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz;
+drivers/net/wireless/realtek/rtw88/rtw8822b.c:	u8 max_pwr_idx = rtwdev->chip->max_power_index;
+drivers/net/wireless/realtek/rtw88/rtw8822c.c:	u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz;
+drivers/net/wireless/realtek/rtw88/tx.c:	pkt_info->offset = chip->tx_pkt_desc_sz;
+drivers/net/wireless/realtek/rtw88/tx.c:	pkt_info->offset = chip->tx_pkt_desc_sz;
+drivers/net/wireless/ti/wl1251/io.c:	 * a chip-specific register address, so look it up in the registers
+drivers/net/wireless/ti/wlcore/wlcore.h:	/* per-chip-family private structure */
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_init(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	zd_usb_init(&chip->usb, hw, intf);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	zd_rf_init(&chip->rf);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	ZD_ASSERT(!mutex_is_locked(&chip->mutex));
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	zd_usb_clear(&chip->usb);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	zd_rf_clear(&chip->rf);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_destroy(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	i += zd_usb_scnprint_id(&chip->usb, buffer+i, size-i);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	i += zd_rf_scnprint_id(&chip->rf, buffer+i, size-i);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	i += scnprintf(buffer+i, size-i, " pa%1x %c%c%c%c%c", chip->pa_type,
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:		chip->patch_cck_gain ? 'g' : '-',
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:		chip->patch_cr157 ? '7' : '-',
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:		chip->patch_6m_band_edge ? '6' : '-',
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:		chip->new_phy_layout ? 'N' : '-',
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:		chip->al2230s_bit ? 'S' : '-');
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	ZD_ASSERT(mutex_is_locked(&chip->mutex));
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	r = zd_usb_iowrite16v_async(&chip->usb, ioreqs16, count16);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	zd_usb_iowrite16v_async_start(&chip->usb);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:		zd_usb_iowrite16v_async_end(&chip->usb, 0);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	return zd_usb_iowrite16v_async_end(&chip->usb, 50 /* ms */);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	ZD_ASSERT(mutex_is_locked(&chip->mutex));
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	zd_usb_iowrite16v_async_start(&chip->usb);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:		r = zd_usb_iowrite16v_async(&chip->usb, &ioreqs[i], j);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:			zd_usb_iowrite16v_async_end(&chip->usb, 0);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	return zd_usb_iowrite16v_async_end(&chip->usb, 50 /* ms */);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	zd_usb_iowrite16v_async_start(&chip->usb);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:			zd_usb_iowrite16v_async_end(&chip->usb, 0);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	return zd_usb_iowrite16v_async_end(&chip->usb, 50 /* ms */);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_lock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_unlock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_lock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_unlock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_lock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_unlock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_lock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_unlock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_lock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_unlock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_lock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_unlock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	ZD_ASSERT(mutex_is_locked(&chip->mutex));
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	chip->pa_type = (value >> 16) & 0x0f;
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	chip->patch_cck_gain = (value >> 8) & 0x1;
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	chip->patch_cr157 = (value >> 13) & 0x1;
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	chip->patch_6m_band_edge = (value >> 21) & 0x1;
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	chip->new_phy_layout = (value >> 31) & 0x1;
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	chip->al2230s_bit = (value >> 7) & 0x1;
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	chip->link_led = ((value >> 4) & 1) ? LED1 : LED2;
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	chip->supports_tx_led = 1;
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:			chip->supports_tx_led = 0;
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:		chip->pa_type, chip->patch_cck_gain,
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:		chip->patch_cr157, chip->patch_6m_band_edge,
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:		chip->new_phy_layout,
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:		chip->link_led == LED1 ? 1 : 2,
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:		chip->supports_tx_led);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	chip->pa_type = 0;
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	chip->patch_cck_gain = 0;
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	chip->patch_cr157 = 0;
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	chip->patch_6m_band_edge = 0;
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	chip->new_phy_layout = 0;
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_lock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_unlock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_lock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_unlock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	ZD_ASSERT(mutex_is_locked(&chip->mutex));
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	return read_values(chip, chip->pwr_cal_values,
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	return read_values(chip, chip->pwr_int_values,
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:		r = read_values(chip, chip->ofdm_cal_values[i],
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	ZD_ASSERT(mutex_is_locked(&chip->mutex));
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	ZD_ASSERT(mutex_is_locked(&chip->mutex));
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	if (!chip->patch_cr157)
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	ZD_ASSERT(mutex_is_locked(&chip->mutex));
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	if (!chip->patch_6m_band_edge)
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	return zd_rf_patch_6m_band_edge(&chip->rf, channel);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	ZD_ASSERT(mutex_is_locked(&chip->mutex));
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	ZD_ASSERT(mutex_is_locked(&chip->mutex));
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	ZD_ASSERT(mutex_is_locked(&chip->mutex));
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	ZD_ASSERT(mutex_is_locked(&chip->mutex));
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_lock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_unlock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	ZD_ASSERT(mutex_is_locked(&chip->mutex));
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	return (zd_addr_t)((u16)chip->fw_regs_base + offset);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	ZD_ASSERT(mutex_is_locked(&chip->mutex));
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_lock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_unlock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_lock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_unlock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	ZD_ASSERT(mutex_is_locked(&chip->mutex));
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	r = zd_ioread16_locked(chip, (u16*)&chip->fw_regs_base,
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:		  (u16)chip->fw_regs_base);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	return zd_usb_read_fw(&chip->usb, E2P_MAC_ADDR_P1, addr,
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_lock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	r = zd_rf_init_hw(&chip->rf, rf_type);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_unlock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	u8 value = chip->pwr_int_values[channel - 1];
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	u8 value = chip->pwr_cal_values[channel-1];
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	ioreqs[0].value = chip->ofdm_cal_values[OFDM_36M_INDEX][channel-1];
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	ioreqs[1].value = chip->ofdm_cal_values[OFDM_48M_INDEX][channel-1];
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	ioreqs[2].value = chip->ofdm_cal_values[OFDM_54M_INDEX][channel-1];
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	if (!zd_rf_should_update_pwr_int(&chip->rf))
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	if (!chip->patch_cck_gain || !zd_rf_should_patch_cck_gain(&chip->rf))
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	ZD_ASSERT(mutex_is_locked(&chip->mutex));
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_lock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	r = zd_rf_set_channel(&chip->rf, channel);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_unlock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_lock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	channel = chip->rf.channel;
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_unlock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_lock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	other_led = chip->link_led == LED1 ? LED2 : LED1;
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:			ioreqs[1].value &= ~chip->link_led;
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:			ioreqs[1].value |= chip->link_led;
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:		ioreqs[1].value |= chip->link_led;
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_unlock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_lock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_unlock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_lock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	r = zd_switch_radio_on(&chip->rf);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_unlock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_lock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	r = zd_switch_radio_off(&chip->rf);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_unlock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_lock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	r = zd_usb_enable_int(&chip->usb);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_unlock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_lock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	zd_usb_disable_int(&chip->usb);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_unlock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_lock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	zd_usb_enable_tx(&chip->usb);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	r = zd_usb_enable_rx(&chip->usb);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	zd_tx_watchdog_enable(&chip->usb);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_unlock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_lock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	zd_tx_watchdog_disable(&chip->usb);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	zd_usb_disable_rx(&chip->usb);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	zd_usb_disable_tx(&chip->usb);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_unlock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	ZD_ASSERT(mutex_is_locked(&chip->mutex));
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_lock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.c:	mutex_unlock(&chip->mutex);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.h:	return chip->usb.is_zd1211b;
+drivers/net/wireless/zydas/zd1211rw/zd_chip.h:	ZD_ASSERT(mutex_is_locked(&chip->mutex));
+drivers/net/wireless/zydas/zd1211rw/zd_chip.h:	return zd_usb_ioread16v(&chip->usb, values, addresses, count);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.h:	ZD_ASSERT(mutex_is_locked(&chip->mutex));
+drivers/net/wireless/zydas/zd1211rw/zd_chip.h:	return zd_usb_ioread16(&chip->usb, value, addr);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.h:	ZD_ASSERT(mutex_is_locked(&chip->mutex));
+drivers/net/wireless/zydas/zd1211rw/zd_chip.h:	return zd_usb_iowrite16v(&chip->usb, &ioreq, 1);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.h:	ZD_ASSERT(mutex_is_locked(&chip->mutex));
+drivers/net/wireless/zydas/zd1211rw/zd_chip.h:	return zd_usb_rfwrite(&chip->usb, value, bits);
+drivers/net/wireless/zydas/zd1211rw/zd_chip.h:	return chip->rf.channel;
+drivers/net/wireless/zydas/zd1211rw/zd_mac.c:	struct zd_usb *usb = &chip->usb;
+drivers/net/wireless/zydas/zd1211rw/zd_rf.c:	ZD_ASSERT(mutex_is_locked(&chip->mutex));
+drivers/net/wireless/zydas/zd1211rw/zd_rf.c:	ZD_ASSERT(mutex_is_locked(&chip->mutex));
+drivers/net/wireless/zydas/zd1211rw/zd_rf.c:	ZD_ASSERT(mutex_is_locked(&chip->mutex));
+drivers/net/wireless/zydas/zd1211rw/zd_rf_al2230.c:	if (chip->new_phy_layout) {
+drivers/net/wireless/zydas/zd1211rw/zd_rf_al7230b.c:	if (chip->new_phy_layout) {
+drivers/net/wireless/zydas/zd1211rw/zd_rf_al7230b.c:	if (chip->new_phy_layout)
+drivers/net/wireless/zydas/zd1211rw/zd_rf_uw2453.c:	u8 int_value = chip->pwr_int_values[channel - 1];
+drivers/nvmem/Makefile:nvmem_rockchip_efuse-y		:= rockchip-efuse.o
+drivers/nvmem/Makefile:obj-$(CONFIG_ROCKCHIP_OTP)	+= nvmem-rockchip-otp.o
+drivers/nvmem/Makefile:nvmem-rockchip-otp-y		:= rockchip-otp.o
+drivers/nvmem/rockchip-efuse.c:	.name = "rockchip-efuse",
+drivers/nvmem/rockchip-efuse.c:		.compatible = "rockchip,rockchip-efuse",
+drivers/nvmem/rockchip-efuse.c:		.name = "rockchip-efuse",
+drivers/nvmem/rockchip-otp.c:	.name = "rockchip-otp",
+drivers/nvmem/rockchip-otp.c:		.name = "rockchip-otp",
+drivers/pci/controller/Makefile:obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o
+drivers/pci/controller/Makefile:obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o
+drivers/pci/controller/pci-aardvark.c:	irq_chip->name = devm_kasprintf(dev, GFP_KERNEL, "%s-irq",
+drivers/pci/controller/pci-aardvark.c:	if (!irq_chip->name) {
+drivers/pci/controller/pci-aardvark.c:	irq_chip->irq_mask = advk_pcie_irq_mask;
+drivers/pci/controller/pci-aardvark.c:	irq_chip->irq_mask_ack = advk_pcie_irq_mask;
+drivers/pci/controller/pci-aardvark.c:	irq_chip->irq_unmask = advk_pcie_irq_unmask;
+drivers/pci/controller/pci-hyperv.c:	return parent->chip->irq_set_affinity(parent, dest, force);
+drivers/pci/controller/pci-tegra.c:	mutex_lock(&chip->lock);
+drivers/pci/controller/pci-tegra.c:	msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR);
+drivers/pci/controller/pci-tegra.c:		set_bit(msi, chip->used);
+drivers/pci/controller/pci-tegra.c:	mutex_unlock(&chip->lock);
+drivers/pci/controller/pci-tegra.c:	struct device *dev = chip->chip.dev;
+drivers/pci/controller/pci-tegra.c:	mutex_lock(&chip->lock);
+drivers/pci/controller/pci-tegra.c:	if (!test_bit(irq, chip->used))
+drivers/pci/controller/pci-tegra.c:		clear_bit(irq, chip->used);
+drivers/pci/controller/pci-tegra.c:	mutex_unlock(&chip->lock);
+drivers/pci/controller/pcie-rcar.c:	mutex_lock(&chip->lock);
+drivers/pci/controller/pcie-rcar.c:	msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR);
+drivers/pci/controller/pcie-rcar.c:		set_bit(msi, chip->used);
+drivers/pci/controller/pcie-rcar.c:	mutex_unlock(&chip->lock);
+drivers/pci/controller/pcie-rcar.c:	mutex_lock(&chip->lock);
+drivers/pci/controller/pcie-rcar.c:	msi = bitmap_find_free_region(chip->used, INT_PCI_MSI_NR,
+drivers/pci/controller/pcie-rcar.c:	mutex_unlock(&chip->lock);
+drivers/pci/controller/pcie-rcar.c:	mutex_lock(&chip->lock);
+drivers/pci/controller/pcie-rcar.c:	clear_bit(irq, chip->used);
+drivers/pci/controller/pcie-rcar.c:	mutex_unlock(&chip->lock);
+drivers/pci/controller/pcie-rockchip-ep.c:	cpu_addr -= rockchip->mem_res->start;
+drivers/pci/controller/pcie-rockchip-ep.c:	struct device *dev = rockchip->dev;
+drivers/pci/controller/pcie-rockchip-ep.c:	rockchip->is_rc = false;
+drivers/pci/controller/pcie-rockchip-ep.c:	rockchip->dev = dev;
+drivers/pci/controller/pcie-rockchip-ep.c:	err = pci_epc_mem_init(epc, rockchip->mem_res->start,
+drivers/pci/controller/pcie-rockchip-ep.c:			       resource_size(rockchip->mem_res));
+drivers/pci/controller/pcie-rockchip-ep.c:		.name = "rockchip-pcie-ep",
+drivers/pci/controller/pcie-rockchip-host.c:	if (bus->number == rockchip->root_bus_nr && dev > 0)
+drivers/pci/controller/pcie-rockchip-host.c:	if (bus->primary == rockchip->root_bus_nr && dev > 0)
+drivers/pci/controller/pcie-rockchip-host.c:	if (rockchip->legacy_phy)
+drivers/pci/controller/pcie-rockchip-host.c:	addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + where;
+drivers/pci/controller/pcie-rockchip-host.c:	addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + offset;
+drivers/pci/controller/pcie-rockchip-host.c:	if (bus->parent->number == rockchip->root_bus_nr)
+drivers/pci/controller/pcie-rockchip-host.c:		*val = readl(rockchip->reg_base + busdev);
+drivers/pci/controller/pcie-rockchip-host.c:		*val = readw(rockchip->reg_base + busdev);
+drivers/pci/controller/pcie-rockchip-host.c:		*val = readb(rockchip->reg_base + busdev);
+drivers/pci/controller/pcie-rockchip-host.c:	if (bus->parent->number == rockchip->root_bus_nr)
+drivers/pci/controller/pcie-rockchip-host.c:		writel(val, rockchip->reg_base + busdev);
+drivers/pci/controller/pcie-rockchip-host.c:		writew(val, rockchip->reg_base + busdev);
+drivers/pci/controller/pcie-rockchip-host.c:		writeb(val, rockchip->reg_base + busdev);
+drivers/pci/controller/pcie-rockchip-host.c:	if (bus->number == rockchip->root_bus_nr)
+drivers/pci/controller/pcie-rockchip-host.c:	if (bus->number == rockchip->root_bus_nr)
+drivers/pci/controller/pcie-rockchip-host.c:	if (IS_ERR(rockchip->vpcie3v3))
+drivers/pci/controller/pcie-rockchip-host.c:	curr = regulator_get_current_limit(rockchip->vpcie3v3);
+drivers/pci/controller/pcie-rockchip-host.c:			dev_warn(rockchip->dev, "invalid power supply\n");
+drivers/pci/controller/pcie-rockchip-host.c:	struct device *dev = rockchip->dev;
+drivers/pci/controller/pcie-rockchip-host.c:	gpiod_set_value_cansleep(rockchip->ep_gpio, 0);
+drivers/pci/controller/pcie-rockchip-host.c:	gpiod_set_value_cansleep(rockchip->ep_gpio, 1);
+drivers/pci/controller/pcie-rockchip-host.c:	err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1,
+drivers/pci/controller/pcie-rockchip-host.c:	if (rockchip->link_gen == 2) {
+drivers/pci/controller/pcie-rockchip-host.c:		err = readl_poll_timeout(rockchip->apb_base + PCIE_CORE_CTRL,
+drivers/pci/controller/pcie-rockchip-host.c:	rockchip->lanes_map = rockchip_pcie_lane_map(rockchip);
+drivers/pci/controller/pcie-rockchip-host.c:		if (!(rockchip->lanes_map & BIT(i))) {
+drivers/pci/controller/pcie-rockchip-host.c:			phy_power_off(rockchip->phys[i]);
+drivers/pci/controller/pcie-rockchip-host.c:		phy_power_off(rockchip->phys[i]);
+drivers/pci/controller/pcie-rockchip-host.c:		phy_exit(rockchip->phys[i]);
+drivers/pci/controller/pcie-rockchip-host.c:	struct device *dev = rockchip->dev;
+drivers/pci/controller/pcie-rockchip-host.c:	struct device *dev = rockchip->dev;
+drivers/pci/controller/pcie-rockchip-host.c:	struct device *dev = rockchip->dev;
+drivers/pci/controller/pcie-rockchip-host.c:		virq = irq_find_mapping(rockchip->irq_domain, hwirq);
+drivers/pci/controller/pcie-rockchip-host.c:	struct device *dev = rockchip->dev;
+drivers/pci/controller/pcie-rockchip-host.c:	struct device *dev = rockchip->dev;
+drivers/pci/controller/pcie-rockchip-host.c:	rockchip->vpcie12v = devm_regulator_get_optional(dev, "vpcie12v");
+drivers/pci/controller/pcie-rockchip-host.c:	if (IS_ERR(rockchip->vpcie12v)) {
+drivers/pci/controller/pcie-rockchip-host.c:		if (PTR_ERR(rockchip->vpcie12v) != -ENODEV)
+drivers/pci/controller/pcie-rockchip-host.c:			return PTR_ERR(rockchip->vpcie12v);
+drivers/pci/controller/pcie-rockchip-host.c:	rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
+drivers/pci/controller/pcie-rockchip-host.c:	if (IS_ERR(rockchip->vpcie3v3)) {
+drivers/pci/controller/pcie-rockchip-host.c:		if (PTR_ERR(rockchip->vpcie3v3) != -ENODEV)
+drivers/pci/controller/pcie-rockchip-host.c:			return PTR_ERR(rockchip->vpcie3v3);
+drivers/pci/controller/pcie-rockchip-host.c:	rockchip->vpcie1v8 = devm_regulator_get(dev, "vpcie1v8");
+drivers/pci/controller/pcie-rockchip-host.c:	if (IS_ERR(rockchip->vpcie1v8))
+drivers/pci/controller/pcie-rockchip-host.c:		return PTR_ERR(rockchip->vpcie1v8);
+drivers/pci/controller/pcie-rockchip-host.c:	rockchip->vpcie0v9 = devm_regulator_get(dev, "vpcie0v9");
+drivers/pci/controller/pcie-rockchip-host.c:	if (IS_ERR(rockchip->vpcie0v9))
+drivers/pci/controller/pcie-rockchip-host.c:		return PTR_ERR(rockchip->vpcie0v9);
+drivers/pci/controller/pcie-rockchip-host.c:	struct device *dev = rockchip->dev;
+drivers/pci/controller/pcie-rockchip-host.c:	if (!IS_ERR(rockchip->vpcie12v)) {
+drivers/pci/controller/pcie-rockchip-host.c:		err = regulator_enable(rockchip->vpcie12v);
+drivers/pci/controller/pcie-rockchip-host.c:	if (!IS_ERR(rockchip->vpcie3v3)) {
+drivers/pci/controller/pcie-rockchip-host.c:		err = regulator_enable(rockchip->vpcie3v3);
+drivers/pci/controller/pcie-rockchip-host.c:	err = regulator_enable(rockchip->vpcie1v8);
+drivers/pci/controller/pcie-rockchip-host.c:	err = regulator_enable(rockchip->vpcie0v9);
+drivers/pci/controller/pcie-rockchip-host.c:	regulator_disable(rockchip->vpcie1v8);
+drivers/pci/controller/pcie-rockchip-host.c:	if (!IS_ERR(rockchip->vpcie3v3))
+drivers/pci/controller/pcie-rockchip-host.c:		regulator_disable(rockchip->vpcie3v3);
+drivers/pci/controller/pcie-rockchip-host.c:	if (!IS_ERR(rockchip->vpcie12v))
+drivers/pci/controller/pcie-rockchip-host.c:		regulator_disable(rockchip->vpcie12v);
+drivers/pci/controller/pcie-rockchip-host.c:	struct device *dev = rockchip->dev;
+drivers/pci/controller/pcie-rockchip-host.c:	rockchip->irq_domain = irq_domain_add_linear(intc, PCI_NUM_INTX,
+drivers/pci/controller/pcie-rockchip-host.c:	if (!rockchip->irq_domain) {
+drivers/pci/controller/pcie-rockchip-host.c:	struct device *dev = rockchip->dev;
+drivers/pci/controller/pcie-rockchip-host.c:	rockchip->msg_bus_addr = pci_addr;
+drivers/pci/controller/pcie-rockchip-host.c:	rockchip->msg_bus_addr += ((reg_no + offset) << 20);
+drivers/pci/controller/pcie-rockchip-host.c:	writel(0x0, rockchip->msg_region + PCIE_RC_SEND_PME_OFF);
+drivers/pci/controller/pcie-rockchip-host.c:	err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_DEBUG_OUT_0,
+drivers/pci/controller/pcie-rockchip-host.c:		dev_err(rockchip->dev, "PCIe link enter L2 timeout!\n");
+drivers/pci/controller/pcie-rockchip-host.c:	regulator_disable(rockchip->vpcie0v9);
+drivers/pci/controller/pcie-rockchip-host.c:	err = regulator_enable(rockchip->vpcie0v9);
+drivers/pci/controller/pcie-rockchip-host.c:	regulator_disable(rockchip->vpcie0v9);
+drivers/pci/controller/pcie-rockchip-host.c:	rockchip->dev = dev;
+drivers/pci/controller/pcie-rockchip-host.c:	rockchip->is_rc = true;
+drivers/pci/controller/pcie-rockchip-host.c:	rockchip->root_bus_nr = bus_res->start;
+drivers/pci/controller/pcie-rockchip-host.c:	rockchip->msg_region = devm_ioremap(dev, rockchip->msg_bus_addr, SZ_1M);
+drivers/pci/controller/pcie-rockchip-host.c:	if (!rockchip->msg_region) {
+drivers/pci/controller/pcie-rockchip-host.c:	rockchip->root_bus = bus;
+drivers/pci/controller/pcie-rockchip-host.c:	irq_domain_remove(rockchip->irq_domain);
+drivers/pci/controller/pcie-rockchip-host.c:	if (!IS_ERR(rockchip->vpcie12v))
+drivers/pci/controller/pcie-rockchip-host.c:		regulator_disable(rockchip->vpcie12v);
+drivers/pci/controller/pcie-rockchip-host.c:	if (!IS_ERR(rockchip->vpcie3v3))
+drivers/pci/controller/pcie-rockchip-host.c:		regulator_disable(rockchip->vpcie3v3);
+drivers/pci/controller/pcie-rockchip-host.c:	regulator_disable(rockchip->vpcie1v8);
+drivers/pci/controller/pcie-rockchip-host.c:	regulator_disable(rockchip->vpcie0v9);
+drivers/pci/controller/pcie-rockchip-host.c:	pci_stop_root_bus(rockchip->root_bus);
+drivers/pci/controller/pcie-rockchip-host.c:	pci_remove_root_bus(rockchip->root_bus);
+drivers/pci/controller/pcie-rockchip-host.c:	irq_domain_remove(rockchip->irq_domain);
+drivers/pci/controller/pcie-rockchip-host.c:	if (!IS_ERR(rockchip->vpcie12v))
+drivers/pci/controller/pcie-rockchip-host.c:		regulator_disable(rockchip->vpcie12v);
+drivers/pci/controller/pcie-rockchip-host.c:	if (!IS_ERR(rockchip->vpcie3v3))
+drivers/pci/controller/pcie-rockchip-host.c:		regulator_disable(rockchip->vpcie3v3);
+drivers/pci/controller/pcie-rockchip-host.c:	regulator_disable(rockchip->vpcie1v8);
+drivers/pci/controller/pcie-rockchip-host.c:	regulator_disable(rockchip->vpcie0v9);
+drivers/pci/controller/pcie-rockchip-host.c:		.name = "rockchip-pcie",
+drivers/pci/controller/pcie-rockchip.c:	struct device *dev = rockchip->dev;
+drivers/pci/controller/pcie-rockchip.c:	if (rockchip->is_rc) {
+drivers/pci/controller/pcie-rockchip.c:		rockchip->reg_base = devm_pci_remap_cfg_resource(dev, regs);
+drivers/pci/controller/pcie-rockchip.c:		if (IS_ERR(rockchip->reg_base))
+drivers/pci/controller/pcie-rockchip.c:			return PTR_ERR(rockchip->reg_base);
+drivers/pci/controller/pcie-rockchip.c:		rockchip->mem_res =
+drivers/pci/controller/pcie-rockchip.c:		if (!rockchip->mem_res)
+drivers/pci/controller/pcie-rockchip.c:	rockchip->apb_base = devm_ioremap_resource(dev, regs);
+drivers/pci/controller/pcie-rockchip.c:	if (IS_ERR(rockchip->apb_base))
+drivers/pci/controller/pcie-rockchip.c:		return PTR_ERR(rockchip->apb_base);
+drivers/pci/controller/pcie-rockchip.c:	rockchip->lanes = 1;
+drivers/pci/controller/pcie-rockchip.c:	err = of_property_read_u32(node, "num-lanes", &rockchip->lanes);
+drivers/pci/controller/pcie-rockchip.c:	if (!err && (rockchip->lanes == 0 ||
+drivers/pci/controller/pcie-rockchip.c:		     rockchip->lanes == 3 ||
+drivers/pci/controller/pcie-rockchip.c:		     rockchip->lanes > 4)) {
+drivers/pci/controller/pcie-rockchip.c:		rockchip->lanes = 1;
+drivers/pci/controller/pcie-rockchip.c:	rockchip->link_gen = of_pci_get_max_link_speed(node);
+drivers/pci/controller/pcie-rockchip.c:	if (rockchip->link_gen < 0 || rockchip->link_gen > 2)
+drivers/pci/controller/pcie-rockchip.c:		rockchip->link_gen = 2;
+drivers/pci/controller/pcie-rockchip.c:	rockchip->core_rst = devm_reset_control_get_exclusive(dev, "core");
+drivers/pci/controller/pcie-rockchip.c:	if (IS_ERR(rockchip->core_rst)) {
+drivers/pci/controller/pcie-rockchip.c:		if (PTR_ERR(rockchip->core_rst) != -EPROBE_DEFER)
+drivers/pci/controller/pcie-rockchip.c:		return PTR_ERR(rockchip->core_rst);
+drivers/pci/controller/pcie-rockchip.c:	rockchip->mgmt_rst = devm_reset_control_get_exclusive(dev, "mgmt");
+drivers/pci/controller/pcie-rockchip.c:	if (IS_ERR(rockchip->mgmt_rst)) {
+drivers/pci/controller/pcie-rockchip.c:		if (PTR_ERR(rockchip->mgmt_rst) != -EPROBE_DEFER)
+drivers/pci/controller/pcie-rockchip.c:		return PTR_ERR(rockchip->mgmt_rst);
+drivers/pci/controller/pcie-rockchip.c:	rockchip->mgmt_sticky_rst = devm_reset_control_get_exclusive(dev,
+drivers/pci/controller/pcie-rockchip.c:	if (IS_ERR(rockchip->mgmt_sticky_rst)) {
+drivers/pci/controller/pcie-rockchip.c:		if (PTR_ERR(rockchip->mgmt_sticky_rst) != -EPROBE_DEFER)
+drivers/pci/controller/pcie-rockchip.c:		return PTR_ERR(rockchip->mgmt_sticky_rst);
+drivers/pci/controller/pcie-rockchip.c:	rockchip->pipe_rst = devm_reset_control_get_exclusive(dev, "pipe");
+drivers/pci/controller/pcie-rockchip.c:	if (IS_ERR(rockchip->pipe_rst)) {
+drivers/pci/controller/pcie-rockchip.c:		if (PTR_ERR(rockchip->pipe_rst) != -EPROBE_DEFER)
+drivers/pci/controller/pcie-rockchip.c:		return PTR_ERR(rockchip->pipe_rst);
+drivers/pci/controller/pcie-rockchip.c:	rockchip->pm_rst = devm_reset_control_get_exclusive(dev, "pm");
+drivers/pci/controller/pcie-rockchip.c:	if (IS_ERR(rockchip->pm_rst)) {
+drivers/pci/controller/pcie-rockchip.c:		if (PTR_ERR(rockchip->pm_rst) != -EPROBE_DEFER)
+drivers/pci/controller/pcie-rockchip.c:		return PTR_ERR(rockchip->pm_rst);
+drivers/pci/controller/pcie-rockchip.c:	rockchip->pclk_rst = devm_reset_control_get_exclusive(dev, "pclk");
+drivers/pci/controller/pcie-rockchip.c:	if (IS_ERR(rockchip->pclk_rst)) {
+drivers/pci/controller/pcie-rockchip.c:		if (PTR_ERR(rockchip->pclk_rst) != -EPROBE_DEFER)
+drivers/pci/controller/pcie-rockchip.c:		return PTR_ERR(rockchip->pclk_rst);
+drivers/pci/controller/pcie-rockchip.c:	rockchip->aclk_rst = devm_reset_control_get_exclusive(dev, "aclk");
+drivers/pci/controller/pcie-rockchip.c:	if (IS_ERR(rockchip->aclk_rst)) {
+drivers/pci/controller/pcie-rockchip.c:		if (PTR_ERR(rockchip->aclk_rst) != -EPROBE_DEFER)
+drivers/pci/controller/pcie-rockchip.c:		return PTR_ERR(rockchip->aclk_rst);
+drivers/pci/controller/pcie-rockchip.c:	if (rockchip->is_rc) {
+drivers/pci/controller/pcie-rockchip.c:		rockchip->ep_gpio = devm_gpiod_get(dev, "ep", GPIOD_OUT_HIGH);
+drivers/pci/controller/pcie-rockchip.c:		if (IS_ERR(rockchip->ep_gpio)) {
+drivers/pci/controller/pcie-rockchip.c:			return PTR_ERR(rockchip->ep_gpio);
+drivers/pci/controller/pcie-rockchip.c:	rockchip->aclk_pcie = devm_clk_get(dev, "aclk");
+drivers/pci/controller/pcie-rockchip.c:	if (IS_ERR(rockchip->aclk_pcie)) {
+drivers/pci/controller/pcie-rockchip.c:		return PTR_ERR(rockchip->aclk_pcie);
+drivers/pci/controller/pcie-rockchip.c:	rockchip->aclk_perf_pcie = devm_clk_get(dev, "aclk-perf");
+drivers/pci/controller/pcie-rockchip.c:	if (IS_ERR(rockchip->aclk_perf_pcie)) {
+drivers/pci/controller/pcie-rockchip.c:		return PTR_ERR(rockchip->aclk_perf_pcie);
+drivers/pci/controller/pcie-rockchip.c:	rockchip->hclk_pcie = devm_clk_get(dev, "hclk");
+drivers/pci/controller/pcie-rockchip.c:	if (IS_ERR(rockchip->hclk_pcie)) {
+drivers/pci/controller/pcie-rockchip.c:		return PTR_ERR(rockchip->hclk_pcie);
+drivers/pci/controller/pcie-rockchip.c:	rockchip->clk_pcie_pm = devm_clk_get(dev, "pm");
+drivers/pci/controller/pcie-rockchip.c:	if (IS_ERR(rockchip->clk_pcie_pm)) {
+drivers/pci/controller/pcie-rockchip.c:		return PTR_ERR(rockchip->clk_pcie_pm);
+drivers/pci/controller/pcie-rockchip.c:	struct device *dev = rockchip->dev;
+drivers/pci/controller/pcie-rockchip.c:	err = reset_control_assert(rockchip->aclk_rst);
+drivers/pci/controller/pcie-rockchip.c:	err = reset_control_assert(rockchip->pclk_rst);
+drivers/pci/controller/pcie-rockchip.c:	err = reset_control_assert(rockchip->pm_rst);
+drivers/pci/controller/pcie-rockchip.c:		err = phy_init(rockchip->phys[i]);
+drivers/pci/controller/pcie-rockchip.c:	err = reset_control_assert(rockchip->core_rst);
+drivers/pci/controller/pcie-rockchip.c:	err = reset_control_assert(rockchip->mgmt_rst);
+drivers/pci/controller/pcie-rockchip.c:	err = reset_control_assert(rockchip->mgmt_sticky_rst);
+drivers/pci/controller/pcie-rockchip.c:	err = reset_control_assert(rockchip->pipe_rst);
+drivers/pci/controller/pcie-rockchip.c:	err = reset_control_deassert(rockchip->pm_rst);
+drivers/pci/controller/pcie-rockchip.c:	err = reset_control_deassert(rockchip->aclk_rst);
+drivers/pci/controller/pcie-rockchip.c:	err = reset_control_deassert(rockchip->pclk_rst);
+drivers/pci/controller/pcie-rockchip.c:	if (rockchip->link_gen == 2)
+drivers/pci/controller/pcie-rockchip.c:	       PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes);
+drivers/pci/controller/pcie-rockchip.c:	if (rockchip->is_rc)
+drivers/pci/controller/pcie-rockchip.c:		err = phy_power_on(rockchip->phys[i]);
+drivers/pci/controller/pcie-rockchip.c:	err = reset_control_deassert(rockchip->mgmt_sticky_rst);
+drivers/pci/controller/pcie-rockchip.c:	err = reset_control_deassert(rockchip->core_rst);
+drivers/pci/controller/pcie-rockchip.c:	err = reset_control_deassert(rockchip->mgmt_rst);
+drivers/pci/controller/pcie-rockchip.c:	err = reset_control_deassert(rockchip->pipe_rst);
+drivers/pci/controller/pcie-rockchip.c:		phy_power_off(rockchip->phys[i]);
+drivers/pci/controller/pcie-rockchip.c:		phy_exit(rockchip->phys[i]);
+drivers/pci/controller/pcie-rockchip.c:	struct device *dev = rockchip->dev;
+drivers/pci/controller/pcie-rockchip.c:		rockchip->legacy_phy = true;
+drivers/pci/controller/pcie-rockchip.c:		rockchip->phys[0] = phy;
+drivers/pci/controller/pcie-rockchip.c:		rockchip->phys[i] = phy;
+drivers/pci/controller/pcie-rockchip.c:		if (rockchip->lanes_map & BIT(i))
+drivers/pci/controller/pcie-rockchip.c:			phy_power_off(rockchip->phys[i]);
+drivers/pci/controller/pcie-rockchip.c:		phy_exit(rockchip->phys[i]);
+drivers/pci/controller/pcie-rockchip.c:	struct device *dev = rockchip->dev;
+drivers/pci/controller/pcie-rockchip.c:	err = clk_prepare_enable(rockchip->aclk_pcie);
+drivers/pci/controller/pcie-rockchip.c:	err = clk_prepare_enable(rockchip->aclk_perf_pcie);
+drivers/pci/controller/pcie-rockchip.c:	err = clk_prepare_enable(rockchip->hclk_pcie);
+drivers/pci/controller/pcie-rockchip.c:	err = clk_prepare_enable(rockchip->clk_pcie_pm);
+drivers/pci/controller/pcie-rockchip.c:	clk_disable_unprepare(rockchip->hclk_pcie);
+drivers/pci/controller/pcie-rockchip.c:	clk_disable_unprepare(rockchip->aclk_perf_pcie);
+drivers/pci/controller/pcie-rockchip.c:	clk_disable_unprepare(rockchip->aclk_pcie);
+drivers/pci/controller/pcie-rockchip.c:	clk_disable_unprepare(rockchip->clk_pcie_pm);
+drivers/pci/controller/pcie-rockchip.c:	clk_disable_unprepare(rockchip->hclk_pcie);
+drivers/pci/controller/pcie-rockchip.c:	clk_disable_unprepare(rockchip->aclk_perf_pcie);
+drivers/pci/controller/pcie-rockchip.c:	clk_disable_unprepare(rockchip->aclk_pcie);
+drivers/pci/controller/pcie-rockchip.h:	return readl(rockchip->apb_base + reg);
+drivers/pci/controller/pcie-rockchip.h:	writel(val, rockchip->apb_base + reg);
+drivers/pci/controller/vmd.c:	data->chip->irq_unmask(data);
+drivers/pci/controller/vmd.c:	data->chip->irq_mask(data);
+drivers/pci/msi.c:	if (!chip || !chip->setup_irq)
+drivers/pci/msi.c:	err = chip->setup_irq(chip, dev, desc);
+drivers/pci/msi.c:	if (!chip || !chip->teardown_irq)
+drivers/pci/msi.c:	chip->teardown_irq(chip, irq);
+drivers/pci/msi.c:	if (chip && chip->setup_irqs)
+drivers/pci/msi.c:		return chip->setup_irqs(chip, dev, nvec, type);
+drivers/pci/msi.c:	if (!chip->irq_write_msi_msg)
+drivers/pci/msi.c:		chip->irq_write_msi_msg = pci_msi_domain_write_msg;
+drivers/pci/msi.c:	if (!chip->irq_mask)
+drivers/pci/msi.c:		chip->irq_mask = pci_msi_mask_irq;
+drivers/pci/msi.c:	if (!chip->irq_unmask)
+drivers/pci/msi.c:		chip->irq_unmask = pci_msi_unmask_irq;
+drivers/pci/msi.c:	info->chip->flags |= IRQCHIP_ONESHOT_SAFE;
+drivers/pcmcia/at91_cf.c:	/* reserve chip-select regions */
+drivers/pcmcia/electra_cf.c:	/* reserve chip-select regions */
+drivers/phy/rockchip/Makefile:obj-$(CONFIG_PHY_ROCKCHIP_DP)		+= phy-rockchip-dp.o
+drivers/phy/rockchip/Makefile:obj-$(CONFIG_PHY_ROCKCHIP_EMMC)		+= phy-rockchip-emmc.o
+drivers/phy/rockchip/Makefile:obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY)	+= phy-rockchip-inno-dsidphy.o
+drivers/phy/rockchip/Makefile:obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI)	+= phy-rockchip-inno-hdmi.o
+drivers/phy/rockchip/Makefile:obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)	+= phy-rockchip-inno-usb2.o
+drivers/phy/rockchip/Makefile:obj-$(CONFIG_PHY_ROCKCHIP_PCIE)		+= phy-rockchip-pcie.o
+drivers/phy/rockchip/Makefile:obj-$(CONFIG_PHY_ROCKCHIP_TYPEC)	+= phy-rockchip-typec.o
+drivers/phy/rockchip/Makefile:obj-$(CONFIG_PHY_ROCKCHIP_USB)		+= phy-rockchip-usb.o
+drivers/phy/rockchip/phy-rockchip-dp.c:		.name	= "rockchip-dp-phy",
+drivers/phy/rockchip/phy-rockchip-emmc.c:		.name	= "rockchip-emmc-phy",
+drivers/phy/rockchip/phy-rockchip-inno-hdmi.c:	/* try to read the chip-version */
+drivers/phy/rockchip/phy-rockchip-inno-usb2.c:		.name	= "rockchip-usb2phy",
+drivers/phy/rockchip/phy-rockchip-pcie.c:		.name	= "rockchip-pcie-phy",
+drivers/phy/rockchip/phy-rockchip-typec.c:		.name	= "rockchip-typec-phy",
+drivers/phy/rockchip/phy-rockchip-usb.c:		.name	= "rockchip-usb-phy",
+drivers/pinctrl/actions/pinctrl-owl.c:	chip->base = -1;
+drivers/pinctrl/actions/pinctrl-owl.c:	chip->ngpio = pctrl->soc->ngpios;
+drivers/pinctrl/actions/pinctrl-owl.c:	chip->label = dev_name(pctrl->dev);
+drivers/pinctrl/actions/pinctrl-owl.c:	chip->parent = pctrl->dev;
+drivers/pinctrl/actions/pinctrl-owl.c:	chip->owner = THIS_MODULE;
+drivers/pinctrl/actions/pinctrl-owl.c:	chip->of_node = pctrl->dev->of_node;
+drivers/pinctrl/actions/pinctrl-owl.c:	pctrl->irq_chip.name = chip->of_node->name;
+drivers/pinctrl/actions/pinctrl-owl.c:	gpio_irq = &chip->irq;
+drivers/pinctrl/actions/pinctrl-owl.c:	gpio_irq->map = devm_kcalloc(pctrl->dev, chip->ngpio,
+drivers/pinctrl/bcm/pinctrl-bcm2835.c:	return pinctrl_gpio_direction_input(chip->base + offset);
+drivers/pinctrl/bcm/pinctrl-bcm2835.c:	return pinctrl_gpio_direction_output(chip->base + offset);
+drivers/pinctrl/bcm/pinctrl-bcm2835.c:		if (chip->irq.parents[i] == irq) {
+drivers/pinctrl/bcm/pinctrl-bcm2835.c:	int irq = irq_find_mapping(chip->irq.domain, offset);
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	val = readl(chip->base + offset);
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	writel(val, chip->base + offset);
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	return !!(readl(chip->base + offset) & BIT(shift));
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	for (i = 0; i < chip->num_banks; i++) {
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:		unsigned long val = readl(chip->base + (i * GPIO_BANK_SIZE) +
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:			writel(BIT(bit), chip->base + (i * GPIO_BANK_SIZE) +
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	writel(val, chip->base + offset);
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	raw_spin_lock_irqsave(&chip->lock, flags);
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	raw_spin_unlock_irqrestore(&chip->lock, flags);
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	raw_spin_lock_irqsave(&chip->lock, flags);
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	raw_spin_unlock_irqrestore(&chip->lock, flags);
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:		dev_err(chip->dev, "invalid GPIO IRQ type 0x%x\n",
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	raw_spin_lock_irqsave(&chip->lock, flags);
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	raw_spin_unlock_irqrestore(&chip->lock, flags);
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	dev_dbg(chip->dev,
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	if (!chip->pinmux_is_supported)
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	if (!chip->pinmux_is_supported)
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	raw_spin_lock_irqsave(&chip->lock, flags);
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	raw_spin_unlock_irqrestore(&chip->lock, flags);
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	dev_dbg(chip->dev, "gpio:%u set input\n", gpio);
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	raw_spin_lock_irqsave(&chip->lock, flags);
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	raw_spin_unlock_irqrestore(&chip->lock, flags);
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val);
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	return !(readl(chip->base + offset) & BIT(shift));
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	raw_spin_lock_irqsave(&chip->lock, flags);
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	raw_spin_unlock_irqrestore(&chip->lock, flags);
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val);
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	return !!(readl(chip->base + offset) & BIT(shift));
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	if (!chip->nr_pinconf_disable)
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	for (i = 0; i < chip->nr_pinconf_disable; i++)
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:		if (chip->pinconf_disable[i] == param)
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	chip->pinconf_disable = devm_kcalloc(chip->dev, nbits,
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:					     sizeof(*chip->pinconf_disable),
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	if (!chip->pinconf_disable)
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	chip->nr_pinconf_disable = nbits;
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:		chip->pinconf_disable[nbits++] = iproc_pinconf_disable_map[bit];
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	raw_spin_lock_irqsave(&chip->lock, flags);
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	if (chip->io_ctrl_type == IOCTRL_TYPE_CDRU) {
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:		base = chip->io_ctrl;
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	raw_spin_unlock_irqrestore(&chip->lock, flags);
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	dev_dbg(chip->dev, "gpio:%u set pullup:%d\n", gpio, pull_up);
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	raw_spin_lock_irqsave(&chip->lock, flags);
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	if (chip->io_ctrl_type == IOCTRL_TYPE_CDRU) {
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:		base = chip->io_ctrl;
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	raw_spin_unlock_irqrestore(&chip->lock, flags);
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	if (chip->io_ctrl) {
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:		base = chip->io_ctrl;
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:		base = chip->base;
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio,
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	raw_spin_lock_irqsave(&chip->lock, flags);
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:		offset = DRV_STRENGTH_OFFSET(gpio, i, chip->io_ctrl_type);
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	raw_spin_unlock_irqrestore(&chip->lock, flags);
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	if (chip->io_ctrl) {
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:		base = chip->io_ctrl;
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:		base = chip->base;
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	raw_spin_lock_irqsave(&chip->lock, flags);
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:		offset = DRV_STRENGTH_OFFSET(gpio, i, chip->io_ctrl_type);
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	raw_spin_unlock_irqrestore(&chip->lock, flags);
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:			dev_err(chip->dev, "invalid configuration\n");
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	struct pinctrl_desc *pctldesc = &chip->pctldesc;
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	struct gpio_chip *gc = &chip->gc;
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	pins = devm_kcalloc(chip->dev, gc->ngpio, sizeof(*pins), GFP_KERNEL);
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:		pins[i].name = devm_kasprintf(chip->dev, GFP_KERNEL,
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	pctldesc->name = dev_name(chip->dev);
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	chip->pctl = devm_pinctrl_register(chip->dev, pctldesc, chip);
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	if (IS_ERR(chip->pctl)) {
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:		dev_err(chip->dev, "unable to register pinctrl device\n");
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:		return PTR_ERR(chip->pctl);
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	chip->dev = dev;
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	chip->base = devm_platform_ioremap_resource(pdev, 0);
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	if (IS_ERR(chip->base)) {
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:		return PTR_ERR(chip->base);
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:		chip->io_ctrl = devm_ioremap_resource(dev, res);
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:		if (IS_ERR(chip->io_ctrl)) {
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:			return PTR_ERR(chip->io_ctrl);
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	chip->io_ctrl_type = io_ctrl_type;
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	raw_spin_lock_init(&chip->lock);
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	gc = &chip->gc;
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	chip->num_banks = (ngpios + NGPIOS_PER_BANK - 1) / NGPIOS_PER_BANK;
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:	chip->pinmux_is_supported = of_property_read_bool(dev->of_node,
+drivers/pinctrl/bcm/pinctrl-iproc-gpio.c:		irqc = &chip->irqchip;
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:		base_address = chip->io_ctrl;
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:		base_address = chip->base;
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:		return !!(readl(chip->io_ctrl + reg) & BIT(gpio));
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:		return !!(readl(chip->base + reg) & BIT(gpio));
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:	int_status = readl(chip->base + NSP_CHIP_A_INT_STATUS);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:		event = readl(chip->base + NSP_GPIO_EVENT_INT_MASK) &
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:			      readl(chip->base + NSP_GPIO_EVENT);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:		level = readl(chip->base + NSP_GPIO_DATA_IN) ^
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:			      readl(chip->base + NSP_GPIO_INT_POLARITY);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:		level &= readl(chip->base + NSP_GPIO_INT_MASK);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:			writel(BIT(bit), chip->base + NSP_GPIO_EVENT);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:	raw_spin_lock_irqsave(&chip->lock, flags);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:	raw_spin_unlock_irqrestore(&chip->lock, flags);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:	raw_spin_lock_irqsave(&chip->lock, flags);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:	raw_spin_unlock_irqrestore(&chip->lock, flags);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:	raw_spin_lock_irqsave(&chip->lock, flags);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:		dev_err(chip->dev, "invalid GPIO IRQ type 0x%x\n",
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:		raw_spin_unlock_irqrestore(&chip->lock, flags);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:	raw_spin_unlock_irqrestore(&chip->lock, flags);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:	dev_dbg(chip->dev, "gpio:%u level_low:%s falling:%s\n", gpio,
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:	raw_spin_lock_irqsave(&chip->lock, flags);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:	raw_spin_unlock_irqrestore(&chip->lock, flags);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:	dev_dbg(chip->dev, "gpio:%u set input\n", gpio);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:	raw_spin_lock_irqsave(&chip->lock, flags);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:	raw_spin_unlock_irqrestore(&chip->lock, flags);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:	dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:	raw_spin_lock_irqsave(&chip->lock, flags);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:	raw_spin_unlock_irqrestore(&chip->lock, flags);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:	raw_spin_lock_irqsave(&chip->lock, flags);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:	raw_spin_unlock_irqrestore(&chip->lock, flags);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:	dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:	return !!(readl(chip->base + NSP_GPIO_DATA_IN) & BIT(gpio));
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:	raw_spin_lock_irqsave(&chip->lock, flags);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:	raw_spin_unlock_irqrestore(&chip->lock, flags);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:	dev_dbg(chip->dev, "gpio:%u set pullup:%d pulldown: %d\n",
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:	raw_spin_lock_irqsave(&chip->lock, flags);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:	raw_spin_unlock_irqrestore(&chip->lock, flags);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:	dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio,
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:	raw_spin_lock_irqsave(&chip->lock, flags);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:		val = readl(chip->io_ctrl + offset);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:		writel(val, chip->io_ctrl + offset);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:	raw_spin_unlock_irqrestore(&chip->lock, flags);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:	raw_spin_lock_irqsave(&chip->lock, flags);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:		val = readl(chip->io_ctrl + offset) & BIT(shift);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:	raw_spin_unlock_irqrestore(&chip->lock, flags);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:			dev_err(chip->dev, "invalid configuration\n");
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:	struct pinctrl_desc *pctldesc = &chip->pctldesc;
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:	struct gpio_chip *gc = &chip->gc;
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:	pins = devm_kcalloc(chip->dev, gc->ngpio, sizeof(*pins), GFP_KERNEL);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:		pins[i].name = devm_kasprintf(chip->dev, GFP_KERNEL,
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:	pctldesc->name = dev_name(chip->dev);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:	chip->pctl = devm_pinctrl_register(chip->dev, pctldesc, chip);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:	if (IS_ERR(chip->pctl)) {
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:		dev_err(chip->dev, "unable to register pinctrl device\n");
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:		return PTR_ERR(chip->pctl);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:	chip->dev = dev;
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:	chip->base = devm_platform_ioremap_resource(pdev, 0);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:	if (IS_ERR(chip->base)) {
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:		return PTR_ERR(chip->base);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:	chip->io_ctrl = devm_platform_ioremap_resource(pdev, 1);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:	if (IS_ERR(chip->io_ctrl)) {
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:		return PTR_ERR(chip->io_ctrl);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:	raw_spin_lock_init(&chip->lock);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:	gc = &chip->gc;
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:		irqc = &chip->irqchip;
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:		val = readl(chip->base + NSP_CHIP_A_INT_MASK);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:		writel(val, (chip->base + NSP_CHIP_A_INT_MASK));
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:				       IRQF_SHARED, "gpio-a", &chip->gc);
+drivers/pinctrl/bcm/pinctrl-nsp-gpio.c:		girq = &chip->gc.irq;
+drivers/pinctrl/cirrus/pinctrl-lochnagar.c:		dev_err(chip->parent, "Failed to set %s value: %d\n",
+drivers/pinctrl/cirrus/pinctrl-lochnagar.c:	return pinctrl_gpio_direction_output(chip->base + offset);
+drivers/pinctrl/cirrus/pinctrl-madera-core.c:	return priv->chip->n_pin_groups + priv->chip->n_pins;
+drivers/pinctrl/cirrus/pinctrl-madera-core.c:	if (selector < priv->chip->n_pin_groups)
+drivers/pinctrl/cirrus/pinctrl-madera-core.c:		return priv->chip->pin_groups[selector].name;
+drivers/pinctrl/cirrus/pinctrl-madera-core.c:	selector -= priv->chip->n_pin_groups;
+drivers/pinctrl/cirrus/pinctrl-madera-core.c:	if (selector < priv->chip->n_pin_groups) {
+drivers/pinctrl/cirrus/pinctrl-madera-core.c:		*pins = priv->chip->pin_groups[selector].pins;
+drivers/pinctrl/cirrus/pinctrl-madera-core.c:		*num_pins = priv->chip->pin_groups[selector].n_pins;
+drivers/pinctrl/cirrus/pinctrl-madera-core.c:		selector -= priv->chip->n_pin_groups;
+drivers/pinctrl/cirrus/pinctrl-madera-core.c:	for (i = 0; i < chip->n_pin_groups; ++i) {
+drivers/pinctrl/cirrus/pinctrl-madera-core.c:		for (g_pin = 0; g_pin < chip->pin_groups[i].n_pins; ++g_pin) {
+drivers/pinctrl/cirrus/pinctrl-madera-core.c:			if (chip->pin_groups[i].pins[g_pin] == pin) {
+drivers/pinctrl/cirrus/pinctrl-madera-core.c:					   chip->pin_groups[i].name);
+drivers/pinctrl/cirrus/pinctrl-madera-core.c:		*num_groups = priv->chip->n_pins;
+drivers/pinctrl/cirrus/pinctrl-madera-core.c:	const struct madera_pin_groups *pin_group = priv->chip->pin_groups;
+drivers/pinctrl/cirrus/pinctrl-madera-core.c:	unsigned int n_chip_groups = priv->chip->n_pin_groups;
+drivers/pinctrl/cirrus/pinctrl-madera-core.c:		 * be offset by the number of chip-specific functions at the
+drivers/pinctrl/cirrus/pinctrl-madera-core.c:	unsigned int n_groups = priv->chip->n_pin_groups;
+drivers/pinctrl/cirrus/pinctrl-madera-core.c:		pin_group = &priv->chip->pin_groups[selector];
+drivers/pinctrl/cirrus/pinctrl-madera-core.c:	madera_pin_desc.npins = priv->chip->n_pins;
+drivers/pinctrl/cirrus/pinctrl-madera.h:	const struct madera_pin_chip *chip; /* chip-specific groups */
+drivers/pinctrl/core.c:			if (range->base + range->npins - 1 < chip->base ||
+drivers/pinctrl/core.c:			    range->base > chip->base + chip->ngpio - 1)
+drivers/pinctrl/intel/pinctrl-baytrail.c:	return pinctrl_gpio_direction_input(chip->base + offset);
+drivers/pinctrl/intel/pinctrl-baytrail.c:	int ret = pinctrl_gpio_direction_output(chip->base + offset);
+drivers/pinctrl/intel/pinctrl-baytrail.c:	chip->irq_eoi(data);
+drivers/pinctrl/intel/pinctrl-baytrail.c:			clear_bit(i, chip->irq.valid_mask);
+drivers/pinctrl/intel/pinctrl-cherryview.c:	return pinctrl_gpio_direction_input(chip->base + offset);
+drivers/pinctrl/intel/pinctrl-cherryview.c:	return pinctrl_gpio_direction_output(chip->base + offset);
+drivers/pinctrl/intel/pinctrl-cherryview.c:	chip->ngpio = community->pins[community->npins - 1].number + 1;
+drivers/pinctrl/intel/pinctrl-cherryview.c:	chip->label = dev_name(pctrl->dev);
+drivers/pinctrl/intel/pinctrl-cherryview.c:	chip->add_pin_ranges = chv_gpio_add_pin_ranges;
+drivers/pinctrl/intel/pinctrl-cherryview.c:	chip->parent = pctrl->dev;
+drivers/pinctrl/intel/pinctrl-cherryview.c:	chip->base = -1;
+drivers/pinctrl/intel/pinctrl-cherryview.c:	chip->irq.chip = &pctrl->irqchip;
+drivers/pinctrl/intel/pinctrl-cherryview.c:	chip->irq.init_hw = chv_gpio_irq_init_hw;
+drivers/pinctrl/intel/pinctrl-cherryview.c:	chip->irq.parent_handler = chv_gpio_irq_handler;
+drivers/pinctrl/intel/pinctrl-cherryview.c:	chip->irq.num_parents = 1;
+drivers/pinctrl/intel/pinctrl-cherryview.c:	chip->irq.parents = &pctrl->irq;
+drivers/pinctrl/intel/pinctrl-cherryview.c:	chip->irq.default_type = IRQ_TYPE_NONE;
+drivers/pinctrl/intel/pinctrl-cherryview.c:	chip->irq.handler = handle_bad_irq;
+drivers/pinctrl/intel/pinctrl-cherryview.c:		chip->irq.init_valid_mask = chv_init_irq_valid_mask;
+drivers/pinctrl/intel/pinctrl-cherryview.c:			irq_domain_associate_many(chip->irq.domain, irq_base,
+drivers/pinctrl/intel/pinctrl-intel.c:	return pinctrl_gpio_direction_input(chip->base + offset);
+drivers/pinctrl/intel/pinctrl-intel.c:	return pinctrl_gpio_direction_output(chip->base + offset);
+drivers/pinctrl/mediatek/pinctrl-moore.c:	return pinctrl_gpio_direction_input(chip->base + gpio);
+drivers/pinctrl/mediatek/pinctrl-moore.c:	return pinctrl_gpio_direction_output(chip->base + gpio);
+drivers/pinctrl/mediatek/pinctrl-moore.c:	chip->label		= PINCTRL_PINCTRL_DEV;
+drivers/pinctrl/mediatek/pinctrl-moore.c:	chip->parent		= hw->dev;
+drivers/pinctrl/mediatek/pinctrl-moore.c:	chip->request		= gpiochip_generic_request;
+drivers/pinctrl/mediatek/pinctrl-moore.c:	chip->free		= gpiochip_generic_free;
+drivers/pinctrl/mediatek/pinctrl-moore.c:	chip->direction_input	= mtk_gpio_direction_input;
+drivers/pinctrl/mediatek/pinctrl-moore.c:	chip->direction_output	= mtk_gpio_direction_output;
+drivers/pinctrl/mediatek/pinctrl-moore.c:	chip->get		= mtk_gpio_get;
+drivers/pinctrl/mediatek/pinctrl-moore.c:	chip->set		= mtk_gpio_set;
+drivers/pinctrl/mediatek/pinctrl-moore.c:	chip->to_irq		= mtk_gpio_to_irq,
+drivers/pinctrl/mediatek/pinctrl-moore.c:	chip->set_config	= mtk_gpio_set_config,
+drivers/pinctrl/mediatek/pinctrl-moore.c:	chip->base		= -1;
+drivers/pinctrl/mediatek/pinctrl-moore.c:	chip->ngpio		= hw->soc->npins;
+drivers/pinctrl/mediatek/pinctrl-moore.c:	chip->of_node		= np;
+drivers/pinctrl/mediatek/pinctrl-moore.c:	chip->of_gpio_n_cells	= 2;
+drivers/pinctrl/mediatek/pinctrl-moore.c:					     chip->ngpio);
+drivers/pinctrl/mediatek/pinctrl-mtk-common.c:	return pinctrl_gpio_direction_input(chip->base + offset);
+drivers/pinctrl/mediatek/pinctrl-mtk-common.c:	return pinctrl_gpio_direction_output(chip->base + offset);
+drivers/pinctrl/mediatek/pinctrl-mtk-common.c:	pctl->chip->ngpio = pctl->devdata->npins;
+drivers/pinctrl/mediatek/pinctrl-mtk-common.c:	pctl->chip->label = dev_name(&pdev->dev);
+drivers/pinctrl/mediatek/pinctrl-mtk-common.c:	pctl->chip->parent = &pdev->dev;
+drivers/pinctrl/mediatek/pinctrl-mtk-common.c:	pctl->chip->base = -1;
+drivers/pinctrl/mediatek/pinctrl-paris.c:	return pinctrl_gpio_direction_input(chip->base + gpio);
+drivers/pinctrl/mediatek/pinctrl-paris.c:	return pinctrl_gpio_direction_output(chip->base + gpio);
+drivers/pinctrl/mediatek/pinctrl-paris.c:	chip->label		= PINCTRL_PINCTRL_DEV;
+drivers/pinctrl/mediatek/pinctrl-paris.c:	chip->parent		= hw->dev;
+drivers/pinctrl/mediatek/pinctrl-paris.c:	chip->request		= gpiochip_generic_request;
+drivers/pinctrl/mediatek/pinctrl-paris.c:	chip->free		= gpiochip_generic_free;
+drivers/pinctrl/mediatek/pinctrl-paris.c:	chip->get_direction	= mtk_gpio_get_direction;
+drivers/pinctrl/mediatek/pinctrl-paris.c:	chip->direction_input	= mtk_gpio_direction_input;
+drivers/pinctrl/mediatek/pinctrl-paris.c:	chip->direction_output	= mtk_gpio_direction_output;
+drivers/pinctrl/mediatek/pinctrl-paris.c:	chip->get		= mtk_gpio_get;
+drivers/pinctrl/mediatek/pinctrl-paris.c:	chip->set		= mtk_gpio_set;
+drivers/pinctrl/mediatek/pinctrl-paris.c:	chip->to_irq		= mtk_gpio_to_irq,
+drivers/pinctrl/mediatek/pinctrl-paris.c:	chip->set_config	= mtk_gpio_set_config,
+drivers/pinctrl/mediatek/pinctrl-paris.c:	chip->base		= -1;
+drivers/pinctrl/mediatek/pinctrl-paris.c:	chip->ngpio		= hw->soc->npins;
+drivers/pinctrl/mediatek/pinctrl-paris.c:	chip->of_node		= np;
+drivers/pinctrl/mediatek/pinctrl-paris.c:	chip->of_gpio_n_cells	= 2;
+drivers/pinctrl/mvebu/pinctrl-armada-37xx.c:	irqchip->irq_ack = armada_37xx_irq_ack;
+drivers/pinctrl/mvebu/pinctrl-armada-37xx.c:	irqchip->irq_mask = armada_37xx_irq_mask;
+drivers/pinctrl/mvebu/pinctrl-armada-37xx.c:	irqchip->irq_unmask = armada_37xx_irq_unmask;
+drivers/pinctrl/mvebu/pinctrl-armada-37xx.c:	irqchip->irq_set_wake = armada_37xx_irq_set_wake;
+drivers/pinctrl/mvebu/pinctrl-armada-37xx.c:	irqchip->irq_set_type = armada_37xx_irq_set_type;
+drivers/pinctrl/mvebu/pinctrl-armada-37xx.c:	irqchip->irq_startup = armada_37xx_irq_startup;
+drivers/pinctrl/mvebu/pinctrl-armada-37xx.c:	irqchip->name = info->data->name;
+drivers/pinctrl/nomadik/pinctrl-abx500.c:		seq_printf(s, " %-9s", chip->get(chip, offset) ? "hi" : "lo");
+drivers/pinctrl/nomadik/pinctrl-abx500.c:	unsigned gpio = chip->base;
+drivers/pinctrl/nomadik/pinctrl-abx500.c:	for (i = 0; i < chip->ngpio; i++, gpio++) {
+drivers/pinctrl/nomadik/pinctrl-abx500.c:				 chip->base + offset - 1);
+drivers/pinctrl/nomadik/pinctrl-abx500.c:		dev_dbg(chip->parent, "pin %d [%#lx]: %s %s\n",
+drivers/pinctrl/nomadik/pinctrl-abx500.c:			dev_err(chip->parent,
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~BIT(offset);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~BIT(offset);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:		nmk_chip->pull_up &= ~BIT(offset);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:		nmk_chip->pull_up |= BIT(offset);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:		writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:		nmk_chip->pull_up &= ~BIT(offset);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:		writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	bool enabled = nmk_chip->lowemi & BIT(offset);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:		nmk_chip->lowemi |= BIT(offset);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:		nmk_chip->lowemi &= ~BIT(offset);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	writel_relaxed(nmk_chip->lowemi,
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:		       nmk_chip->addr + NMK_GPIO_LOWEMI);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:		writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:		writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRS);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	u32 rwimsc = nmk_chip->rwimsc;
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	u32 fwimsc = nmk_chip->fwimsc;
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	if (glitch && nmk_chip->set_ioforce) {
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:		writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:		writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:		nmk_chip->set_ioforce(true);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	if (glitch && nmk_chip->set_ioforce) {
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:		nmk_chip->set_ioforce(false);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:		writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:		writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	u32 falling = nmk_chip->fimsc & BIT(offset);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	u32 rising = nmk_chip->rimsc & BIT(offset);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	int gpio = nmk_chip->chip.base + offset;
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	int irq = irq_find_mapping(nmk_chip->chip.irq.domain, offset);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:		nmk_chip->rimsc &= ~BIT(offset);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:		writel_relaxed(nmk_chip->rimsc,
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:			       nmk_chip->addr + NMK_GPIO_RIMSC);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:		nmk_chip->fimsc &= ~BIT(offset);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:		writel_relaxed(nmk_chip->fimsc,
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:			       nmk_chip->addr + NMK_GPIO_FIMSC);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	dev_dbg(nmk_chip->chip.parent, "%d: clearing interrupt mask\n", gpio);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:		clk_enable(chip->clk);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:		slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:		writel(temp, chip->addr + NMK_GPIO_SLPC);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:		writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:		clk_disable(chip->clk);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	clk_enable(nmk_chip->clk);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	writel(BIT(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	clk_disable(nmk_chip->clk);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:		rimscval = &nmk_chip->rimsc;
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:		fimscval = &nmk_chip->fimsc;
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:		rimscval = &nmk_chip->rwimsc;
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:		fimscval = &nmk_chip->fwimsc;
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	if (nmk_chip->edge_rising & BIT(offset)) {
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:		writel(*rimscval, nmk_chip->addr + rimscreg);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	if (nmk_chip->edge_falling & BIT(offset)) {
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:		writel(*fimscval, nmk_chip->addr + fimscreg);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	if (nmk_chip->sleepmode && on) {
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	clk_enable(nmk_chip->clk);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	spin_lock(&nmk_chip->lock);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	if (!(nmk_chip->real_wake & BIT(d->hwirq)))
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	spin_unlock(&nmk_chip->lock);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	clk_disable(nmk_chip->clk);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	clk_enable(nmk_chip->clk);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	spin_lock(&nmk_chip->lock);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:		nmk_chip->real_wake |= BIT(d->hwirq);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:		nmk_chip->real_wake &= ~BIT(d->hwirq);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	spin_unlock(&nmk_chip->lock);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	clk_disable(nmk_chip->clk);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	clk_enable(nmk_chip->clk);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	spin_lock_irqsave(&nmk_chip->lock, flags);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	nmk_chip->edge_rising &= ~BIT(d->hwirq);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:		nmk_chip->edge_rising |= BIT(d->hwirq);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	nmk_chip->edge_falling &= ~BIT(d->hwirq);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:		nmk_chip->edge_falling |= BIT(d->hwirq);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	spin_unlock_irqrestore(&nmk_chip->lock, flags);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	clk_disable(nmk_chip->clk);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	clk_enable(nmk_chip->clk);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	clk_disable(nmk_chip->clk);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	clk_enable(nmk_chip->clk);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	status = readl(nmk_chip->addr + NMK_GPIO_IS);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	clk_disable(nmk_chip->clk);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:		generic_handle_irq(irq_find_mapping(chip->irq.domain, bit));
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	clk_enable(nmk_chip->clk);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	dir = !(readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset));
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	clk_disable(nmk_chip->clk);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	clk_enable(nmk_chip->clk);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	clk_disable(nmk_chip->clk);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	clk_enable(nmk_chip->clk);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	value = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset));
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	clk_disable(nmk_chip->clk);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	clk_enable(nmk_chip->clk);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	clk_disable(nmk_chip->clk);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	clk_enable(nmk_chip->clk);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	clk_disable(nmk_chip->clk);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	clk_enable(nmk_chip->clk);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & BIT(offset);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & BIT(offset);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	clk_disable(nmk_chip->clk);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	clk_enable(nmk_chip->clk);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset));
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & BIT(offset));
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	data_out = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset));
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:		int irq = chip->to_irq(chip, offset);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:			if (nmk_chip->edge_rising & BIT(offset))
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:			else if (nmk_chip->edge_falling & BIT(offset))
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	clk_disable(nmk_chip->clk);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	unsigned		gpio = chip->base;
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	for (i = 0; i < chip->ngpio; i++, gpio++) {
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	nmk_chip->bank = id;
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	chip = &nmk_chip->chip;
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	chip->base = id * NMK_GPIO_PER_CHIP;
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	chip->ngpio = NMK_GPIO_PER_CHIP;
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	chip->label = dev_name(&gpio_pdev->dev);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	chip->parent = &gpio_pdev->dev;
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	nmk_chip->addr = base;
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	nmk_chip->clk = clk;
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	dev->id = nmk_chip->bank;
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	 * The virt address in nmk_chip->addr is in the nomadik register space,
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	nmk_chip->sleepmode = supports_sleepmode;
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	spin_lock_init(&nmk_chip->lock);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	chip = &nmk_chip->chip;
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	chip->request = gpiochip_generic_request;
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	chip->free = gpiochip_generic_free;
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	chip->get_direction = nmk_gpio_get_dir;
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	chip->direction_input = nmk_gpio_make_input;
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	chip->get = nmk_gpio_get_input;
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	chip->direction_output = nmk_gpio_make_output;
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	chip->set = nmk_gpio_set_output;
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	chip->dbg_show = nmk_gpio_dbg_show;
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	chip->can_sleep = false;
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	chip->owner = THIS_MODULE;
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	irqchip = &nmk_chip->irqchip;
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	irqchip->irq_ack = nmk_gpio_irq_ack;
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	irqchip->irq_mask = nmk_gpio_irq_mask;
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	irqchip->irq_unmask = nmk_gpio_irq_unmask;
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	irqchip->irq_set_type = nmk_gpio_irq_set_type;
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	irqchip->irq_set_wake = nmk_gpio_irq_set_wake;
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	irqchip->irq_startup = nmk_gpio_irq_startup;
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	irqchip->irq_shutdown = nmk_gpio_irq_shutdown;
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	irqchip->flags = IRQCHIP_MASK_ON_SUSPEND;
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	irqchip->name = kasprintf(GFP_KERNEL, "nmk%u-%u-%u",
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:				  chip->base,
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:				  chip->base + chip->ngpio - 1);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	girq = &chip->irq;
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	clk_enable(nmk_chip->clk);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	clk_disable(nmk_chip->clk);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	chip->of_node = np;
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:		clk_enable(nmk_chip->clk);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:		clk_disable(nmk_chip->clk);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	clk_enable(nmk_chip->clk);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c:	clk_disable(nmk_chip->clk);
+drivers/pinctrl/nomadik/pinctrl-nomadik.c: