* [PATCH v3 1/1] mtd: spi-nor: micron-st: Enable locking for mt25qu256a
@ 2022-10-20 9:20 Eliav Farber
2022-10-20 10:46 ` Michael Walle
2022-11-21 15:11 ` Tudor Ambarus
0 siblings, 2 replies; 3+ messages in thread
From: Eliav Farber @ 2022-10-20 9:20 UTC (permalink / raw)
To: tudor.ambarus, pratyush, michael, miquel.raynal, richard,
vigneshr, linux-mtd, linux-kernel
Cc: talel, jonnyc, hhhawa, hanochu, farbere, itamark, shellykz,
amitlavi, dkl
mt25qu256a [1] uses the 4 bit Block Protection scheme and supports
Top/Bottom protection via the BP and TB bits of the Status Register.
BP3 is located in bit 6 of the Status Register.
Tested on MT25QU256ABA8ESF-0SIT.
[1] https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-a/mt25q_qljs_u_256_aba_0.pdf
Signed-off-by: Eliav Farber <farbere@amazon.com>
Link: https://lore.kernel.org/lkml/20221019071631.15191-1-farbere@amazon.com
---
xxd -p /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/sfdp
53464450060101ff00060110300000ff84000102800000ffffffffffffff
ffffffffffffffffffffffffffffffffffffe520fbffffffff0f29eb276b
273b27bbffffffffffff27bbffff29eb0c2010d80f520000244a99008b8e
03d4ac0127387a757a75fbbdd55c4a0f82ff81bd3d36ffffffffffffffff
ffffffffffffffffffe7ffff21dcffff
md5sum /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/sfdp
5ea738216f68c9f98987bb3725699a32 /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/sfdp
cat /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/jedec_id
20bb19104400
cat /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/partname
mt25qu256a
cat /sys/devices/platform/soc/fd882000.spi/spi_master/spi0/spi0.0/spi-nor/manufacturer
st
v3 --> v2:
- Minimize change only to mt25qu256a which it was tested on.
v2 --> v1:
- Enable locking also for mt25qu256a.
- Dump the SFDP tables.
drivers/mtd/spi-nor/micron-st.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index 3c9681a3f7a3..53ff41534977 100644
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -201,6 +201,8 @@ static const struct flash_info st_nor_parts[] = {
MFR_FLAGS(USE_FSR)
},
{ "mt25qu256a", INFO6(0x20bb19, 0x104400, 64 * 1024, 512)
+ FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
+ SPI_NOR_BP3_SR_BIT6)
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
MFR_FLAGS(USE_FSR)
--
2.37.1
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^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v3 1/1] mtd: spi-nor: micron-st: Enable locking for mt25qu256a
2022-10-20 9:20 [PATCH v3 1/1] mtd: spi-nor: micron-st: Enable locking for mt25qu256a Eliav Farber
@ 2022-10-20 10:46 ` Michael Walle
2022-11-21 15:11 ` Tudor Ambarus
1 sibling, 0 replies; 3+ messages in thread
From: Michael Walle @ 2022-10-20 10:46 UTC (permalink / raw)
To: Eliav Farber
Cc: tudor.ambarus, pratyush, miquel.raynal, richard, vigneshr,
linux-mtd, linux-kernel, talel, jonnyc, hhhawa, hanochu, itamark,
shellykz, amitlavi, dkl
Am 2022-10-20 11:20, schrieb Eliav Farber:
> mt25qu256a [1] uses the 4 bit Block Protection scheme and supports
> Top/Bottom protection via the BP and TB bits of the Status Register.
> BP3 is located in bit 6 of the Status Register.
> Tested on MT25QU256ABA8ESF-0SIT.
>
> [1]
> https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-a/mt25q_qljs_u_256_aba_0.pdf
>
> Signed-off-by: Eliav Farber <farbere@amazon.com>
> Link:
> https://lore.kernel.org/lkml/20221019071631.15191-1-farbere@amazon.com
Reviewed-by: Michael Walle <michael@walle.cc>
Thanks,
-michael
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^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v3 1/1] mtd: spi-nor: micron-st: Enable locking for mt25qu256a
2022-10-20 9:20 [PATCH v3 1/1] mtd: spi-nor: micron-st: Enable locking for mt25qu256a Eliav Farber
2022-10-20 10:46 ` Michael Walle
@ 2022-11-21 15:11 ` Tudor Ambarus
1 sibling, 0 replies; 3+ messages in thread
From: Tudor Ambarus @ 2022-11-21 15:11 UTC (permalink / raw)
To: linux-kernel, linux-mtd, richard, vigneshr, pratyush, michael,
farbere, miquel.raynal
Cc: Tudor Ambarus, talel, shellykz, hhhawa, jonnyc, itamark, dkl,
amitlavi, hanochu
On Thu, 20 Oct 2022 09:20:58 +0000, Eliav Farber wrote:
> mt25qu256a [1] uses the 4 bit Block Protection scheme and supports
> Top/Bottom protection via the BP and TB bits of the Status Register.
> BP3 is located in bit 6 of the Status Register.
> Tested on MT25QU256ABA8ESF-0SIT.
>
> [1] https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-a/mt25q_qljs_u_256_aba_0.pdf
>
> [...]
Applied to spi-nor/next, thanks!
[1/1] mtd: spi-nor: micron-st: Enable locking for mt25qu256a
https://git.kernel.org/mtd/c/bcc0c61e6134
Best regards,
--
Tudor Ambarus <tudor.ambarus@microchip.com>
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
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2022-10-20 9:20 [PATCH v3 1/1] mtd: spi-nor: micron-st: Enable locking for mt25qu256a Eliav Farber
2022-10-20 10:46 ` Michael Walle
2022-11-21 15:11 ` Tudor Ambarus
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