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From: Jungseung Lee <js07.lee@samsung.com>
To: js07.lee@samsung.com, michael@walle.cc, vigneshr@ti.com,
	linux-mtd@lists.infradead.org, Tudor.Ambarus@microchip.com
Subject: Re: [PATCH v3 3/5] mtd: spi-nor: Add new formula for SR block protection handling
Date: Mon, 23 Mar 2020 22:32:48 +0900
Message-ID: <dd90ca2707b6c78adbaaf608ad21d2268f09d382.camel@samsung.com> (raw)
In-Reply-To: <000001d600ff$063a8fd0$12afaf70$@samsung.com>

> From: Tudor.Ambarus@microchip.com <Tudor.Ambarus@microchip.com> 
> Sent: Monday, March 23, 2020 6:25 PM
> To: js07.lee@samsung.com; michael@walle.cc; vigneshr@ti.com
> Cc: linux-mtd@lists.infradead.org; Tudor.Ambarus@microchip.com
> Subject: [PATCH v3 3/5] mtd: spi-nor: Add new formula for SR block
> protection handling
> 
> From: Jungseung Lee <js07.lee@samsung.com>
> 
> The current mainline locking was restricted and could only be applied
> to flashes that has 3 block protection bit and fixed locking ratio.
> 
> A new method of normalization was reached at the end of the
> discussion [1].
> 
>     (1) - if bp slot is insufficient.
>     (2) - if bp slot is sufficient.
> 
>     if (bp_slots_needed > bp_slots)    // (1)
>         min_prot_length = sector_size << (bp_slots_needed -
> bp_slots);
>     else                               // (2)
>         min_prot_length = sector_size;
> 
> This patch changes logic to handle block protection based on
> min_prot_length.
> It is suitable for the overall flashes with exception of some corner
> cases
> (see EON and catalyst) and easy to extend and apply for the case of
> 2bit or
> 4bit block protection.
> 
> [1] https://protect2.fireeye.com/url?k=d62c9c1b-8bf82073-d62d1754-
> 0cc47a3356b2-012ef3655070329a&u=
> http://lists.infradead.org/pipermail/linux-
> mtd/2020-February/093934.html
> 
> Signed-off-by: Jungseung Lee <js07.lee@samsung.com>
> Reviewed-by: Michael Walle <michael@walle.cc>
> Tested-by: Michael Walle <michael@walle.cc>
> [ta: - drop spi_nor_get_bp_mask(), spi_nor_get_tb_mask()
> - rename spi_nor_get_min_prot_length/spi_nor_get_min_prot_length_sr
> - static u64 spi_nor_get_min_prot_length
> - unsigned int bp_slots, bp_slots_needed;
> - bp_slots = (mask >> SR_BP_SHIFT) + 1 - 2;
> - amend commit description]

All looks good and it's ok for me.

Thanks,

> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
> ---
>  drivers/mtd/spi-nor/core.c | 72 ++++++++++++++++++++++------------
> ----
>  1 file changed, 41 insertions(+), 31 deletions(-)
> 
> diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
> index 3788a95c0a47..c0d186f417d8 100644
> --- a/drivers/mtd/spi-nor/core.c
> +++ b/drivers/mtd/spi-nor/core.c
> @@ -1514,29 +1514,51 @@ static int spi_nor_erase(struct mtd_info
> *mtd,
> struct erase_info *instr)
>  	return ret;
>  }
>  
> +static u64 spi_nor_get_min_prot_length_sr(struct spi_nor *nor)
> +{
> +	unsigned int bp_slots, bp_slots_needed;
> +	u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
> +
> +	/* Reserved one for "protect none" and one for "protect all".
> */
> +	bp_slots = (mask >> SR_BP_SHIFT) + 1 - 2;
> +	bp_slots_needed = ilog2(nor->info->n_sectors);
> +
> +	if (bp_slots_needed > bp_slots)
> +		return nor->info->sector_size <<
> +			(bp_slots_needed - bp_slots);
> +	else
> +		return nor->info->sector_size;
> +}
> +
>  static void spi_nor_get_locked_range_sr(struct spi_nor *nor, u8 sr,
> loff_t
> *ofs,
>  					uint64_t *len)
>  {
>  	struct mtd_info *mtd = &nor->mtd;
> +	u64 min_prot_len;
>  	u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
>  	u8 tb_mask = SR_TB_BIT5;
> -	int pow;
> +	u8 bp = (sr & mask) >> SR_BP_SHIFT;
>  
>  	if (nor->flags & SNOR_F_HAS_SR_TB_BIT6)
>  		tb_mask = SR_TB_BIT6;
>  
> -	if (!(sr & mask)) {
> +	if (!bp) {
>  		/* No protection */
>  		*ofs = 0;
>  		*len = 0;
> -	} else {
> -		pow = ((sr & mask) ^ mask) >> SR_BP_SHIFT;
> -		*len = mtd->size >> pow;
> -		if (nor->flags & SNOR_F_HAS_SR_TB && sr & tb_mask)
> -			*ofs = 0;
> -		else
> -			*ofs = mtd->size - *len;
> +		return;
>  	}
> +
> +	min_prot_len = spi_nor_get_min_prot_length_sr(nor);
> +	*len = min_prot_len << (bp - 1);
> +
> +	if (*len > mtd->size)
> +		*len = mtd->size;
> +
> +	if (nor->flags & SNOR_F_HAS_SR_TB && sr & tb_mask)
> +		*ofs = 0;
> +	else
> +		*ofs = mtd->size - *len;
>  }
>  
>  /*
> @@ -1609,6 +1631,7 @@ static int spi_nor_is_unlocked_sr(struct
> spi_nor
> *nor, loff_t ofs, uint64_t len,
>  static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, uint64_t
> len)
>  {
>  	struct mtd_info *mtd = &nor->mtd;
> +	u64 min_prot_len;
>  	int ret, status_old, status_new;
>  	u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
>  	u8 tb_mask = SR_TB_BIT5;
> @@ -1651,20 +1674,12 @@ static int spi_nor_sr_lock(struct spi_nor
> *nor,
> loff_t ofs, uint64_t len)
>  	if (nor->flags & SNOR_F_HAS_SR_TB_BIT6)
>  		tb_mask = SR_TB_BIT6;
>  
> -	/*
> -	 * Need smallest pow such that:
> -	 *
> -	 *   1 / ((2^pow) - 1) <= (len / size)
> -	 *
> -	 * so (assuming power-of-2 size) we do:
> -	 *
> -	 *   pow = ceil(log2(size / len)) = log2(size) -
> floor(log2(len)) +
> 1
> -	 */
>  	if (lock_len == mtd->size) {
>  		val = mask;
>  	} else {
> -		pow = ilog2(mtd->size) - ilog2(lock_len) + 1;
> -		val = mask - (pow << SR_BP_SHIFT);
> +		min_prot_len = spi_nor_get_min_prot_length_sr(nor);
> +		pow = ilog2(lock_len) - ilog2(min_prot_len) + 1;
> +		val = pow << SR_BP_SHIFT;
>  
>  		if (val & ~mask)
>  			return -EINVAL;
> @@ -1701,6 +1716,7 @@ static int spi_nor_sr_lock(struct spi_nor *nor,
> loff_t ofs, uint64_t len)
>  static int spi_nor_sr_unlock(struct spi_nor *nor, loff_t ofs,
> uint64_t len)
>  {
>  	struct mtd_info *mtd = &nor->mtd;
> +	u64 min_prot_len;
>  	int ret, status_old, status_new;
>  	u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
>  	u8 tb_mask = SR_TB_BIT5;
> @@ -1742,20 +1758,14 @@ static int spi_nor_sr_unlock(struct spi_nor
> *nor,
> loff_t ofs, uint64_t len)
>  
>  	if (nor->flags & SNOR_F_HAS_SR_TB_BIT6)
>  		tb_mask = SR_TB_BIT6;
> -	/*
> -	 * Need largest pow such that:
> -	 *
> -	 *   1 / ((2^pow) - 1) >= (len / size)
> -	 *
> -	 * so (assuming power-of-2 size) we do:
> -	 *
> -	 *   pow = floor(log2(size / len)) = log2(size) -
> ceil(log2(len)) +
> 1
> -	 */
> -	pow = ilog2(mtd->size) - order_base_2(lock_len) + 1;
> +
>  	if (lock_len == 0) {
>  		val = 0; /* fully unlocked */
>  	} else {
> -		val = mask - (pow << SR_BP_SHIFT);
> +		min_prot_len = spi_nor_get_min_prot_length_sr(nor);
> +		pow = ilog2(lock_len) - ilog2(min_prot_len) + 1;
> +		val = pow << SR_BP_SHIFT;
> +
>  		/* Some power-of-two sizes are not supported */
>  		if (val & ~mask)
>  			return -EINVAL;


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  parent reply index

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-23  9:24 [PATCH v3 0/5] mtd: spi-nor: Add SR 4bit block protection support Tudor.Ambarus
2020-03-23  9:24 ` [PATCH v3 1/5] mtd: spi-nor: Fix gap in SR block protection locking Tudor.Ambarus
2020-03-23 18:27   ` Michael Walle
2020-03-23 19:20     ` Tudor.Ambarus
2020-03-23 19:54       ` Michael Walle
2020-03-23 20:26         ` Tudor.Ambarus
2020-03-23 21:14           ` Michael Walle
2020-03-23 21:30             ` Tudor.Ambarus
2020-03-23 21:33               ` Tudor.Ambarus
2020-03-23 22:35               ` Michael Walle
2020-03-24  5:37                 ` Tudor.Ambarus
2020-03-24  3:52   ` Jungseung Lee
2020-03-25  9:44   ` Tudor.Ambarus
2020-03-23  9:24 ` [PATCH v3 2/5] mtd: spi-nor: Set all BP bits to one when lock_len == mtd->size Tudor.Ambarus
2020-03-23 14:08   ` Jungseung Lee
2020-03-23 18:28   ` Michael Walle
2020-03-23  9:24 ` [PATCH v3 3/5] mtd: spi-nor: Add new formula for SR block protection handling Tudor.Ambarus
     [not found]   ` <000001d600ff$063a8fd0$12afaf70$@samsung.com>
2020-03-23 13:32     ` Jungseung Lee [this message]
2020-03-23  9:24 ` [PATCH v3 4/5] mtd: spi-nor: Add SR 4bit block protection support Tudor.Ambarus
2020-03-23 12:43   ` Jungseung Lee
2020-03-23 12:55     ` Tudor.Ambarus
2020-03-23 13:16       ` Jungseung Lee
2020-03-23 18:33   ` Michael Walle
2020-03-23 18:51     ` Tudor.Ambarus
2020-03-23  9:24 ` [PATCH v3 4/5] mtd: spi-nor: Add 4bit SR " Tudor.Ambarus
2020-03-23  9:46   ` Tudor.Ambarus
2020-03-23  9:24 ` [PATCH v3 5/5] mtd: spi-nor: Enable locking for n25q512ax3/n25q512a Tudor.Ambarus

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