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* [PATCH 0/2] mtd: spi-nor: OTP support
@ 2020-01-08 23:36 Michael Walle
  2020-01-08 23:36 ` [PATCH 1/2] mtd: spi-nor: add " Michael Walle
  2020-01-08 23:36 ` [PATCH 2/2] mtd: spi-nor: implement OTP support for Winbond flashes Michael Walle
  0 siblings, 2 replies; 5+ messages in thread
From: Michael Walle @ 2020-01-08 23:36 UTC (permalink / raw)
  To: linux-mtd, linux-kernel
  Cc: Vignesh Raghavendra, Rahul Bedarkar, Tudor Ambarus,
	Richard Weinberger, Rahul Bedarkar, Michael Walle, Miquel Raynal,
	Brian Norris

This patchset implements the mtd otp functions to allow access to the SPI
OTP data. Specific support is added for the Winbond flash chips.

In the past there was already an attempt by Rahul Bedarkar to add this, but
there was no response. These two patches are slightly based on his work.

https://lore.kernel.org/linux-mtd/1489754636-21461-1-git-send-email-rahul.bedarkar@imgtec.com/

This series is based on top of the following patches. They are not strictly
needed, but the patches might not apply cleanly and - more importantly -
OTP support for the new W25QnnJW flashes, which are added by one of the
patches, is already added.

https://lore.kernel.org/linux-mtd/20200107222317.3527-1-michael@walle.cc/
https://lore.kernel.org/linux-mtd/20200107222317.3527-2-michael@walle.cc/
https://lore.kernel.org/linux-mtd/20200103223423.14025-1-michael@walle.cc/

To dump an OTP area which doesn't start at zero (like for the Winbond
flashes) the following patch must be applied to mtd-utils:

https://lore.kernel.org/linux-mtd/20200108232359.27372-1-michael@walle.cc/

Michael Walle (2):
  mtd: spi-nor: add OTP support
  mtd: spi-nor: implement OTP support for Winbond flashes

 drivers/mtd/spi-nor/spi-nor.c | 279 ++++++++++++++++++++++++++++++++++
 include/linux/mtd/spi-nor.h   |  52 +++++++
 2 files changed, 331 insertions(+)

-- 
2.20.1


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH 1/2] mtd: spi-nor: add OTP support
  2020-01-08 23:36 [PATCH 0/2] mtd: spi-nor: OTP support Michael Walle
@ 2020-01-08 23:36 ` " Michael Walle
  2020-01-13  8:37   ` Michael Walle
  2020-01-08 23:36 ` [PATCH 2/2] mtd: spi-nor: implement OTP support for Winbond flashes Michael Walle
  1 sibling, 1 reply; 5+ messages in thread
From: Michael Walle @ 2020-01-08 23:36 UTC (permalink / raw)
  To: linux-mtd, linux-kernel
  Cc: Vignesh Raghavendra, Rahul Bedarkar, Tudor Ambarus,
	Richard Weinberger, Rahul Bedarkar, Michael Walle, Miquel Raynal,
	Brian Norris

Implement the MTD callbacks for the OTP methods for the SPI NOR
subsystem.

Usually, the OTP area of a SPI flash can be accessed like the normal
memory, eg by offset addressing; except that you either have to use
special read/write commands (Winbond) or you have to enter (and exit) a
specific OTP mode (Macronix, Micron). Sometimes there are individual
regions, which might have individual offsets. Therefore, it is possible
to specify the starting address of the first regions as well as the
distance between two regions (Winbond).

Additionally, the regions might be locked down. Once locked, no further
write access is possible.

Signed-off-by: Michael Walle <michael@walle.cc>
---
 drivers/mtd/spi-nor/spi-nor.c | 147 ++++++++++++++++++++++++++++++++++
 include/linux/mtd/spi-nor.h   |  38 +++++++++
 2 files changed, 185 insertions(+)

diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 818cb9393f41..5eabaec70508 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -241,6 +241,15 @@ struct flash_info {
 
 	/* Part specific fixup hooks. */
 	const struct spi_nor_fixups *fixups;
+
+	/* OTP size in bytes */
+	u16 otp_size;
+	/* Number of OTP banks */
+	u16 n_otps;
+	/* Start address of OTP area */
+	u32 otp_start_addr;
+	/* Offset between consecutive OTP banks if there are more than one */
+	u32 otp_addr_offset;
 };
 
 #define JEDEC_MFR(info)	((info)->id[0])
@@ -2240,6 +2249,12 @@ static int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor)
 		.addr_width = 3,					\
 		.flags = SPI_NOR_NO_FR | SPI_S3AN,
 
+#define OTP_INFO(_otp_size, _n_otps, _otp_start_addr, _otp_addr_offset)	\
+		.otp_size = (_otp_size),				\
+		.n_otps = (_n_otps),					\
+		.otp_start_addr = (_otp_start_addr),			\
+		.otp_addr_offset = (_otp_addr_offset),
+
 static int
 is25lp256_post_bfpt_fixups(struct spi_nor *nor,
 			   const struct sfdp_parameter_header *bfpt_header,
@@ -4827,6 +4842,12 @@ static void spi_nor_info_init_params(struct spi_nor *nor)
 	spi_nor_set_erase_type(&map->erase_type[i], info->sector_size,
 			       SPINOR_OP_SE);
 	spi_nor_init_uniform_erase_map(map, erase_mask, params->size);
+
+	/* OTP parameters */
+	nor->params.otp_info.otp_size = info->otp_size;
+	nor->params.otp_info.n_otps = info->n_otps;
+	nor->params.otp_info.otp_start_addr = info->otp_start_addr;
+	nor->params.otp_info.otp_addr_offset = info->otp_addr_offset;
 }
 
 static void spansion_post_sfdp_fixups(struct spi_nor *nor)
@@ -5122,6 +5143,125 @@ static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor,
 	return info;
 }
 
+static loff_t spi_nor_otp_region_start(struct spi_nor *nor, int region)
+{
+	struct spi_nor_otp_info *info = &nor->params.otp_info;
+
+	return info->otp_start_addr + region * info->otp_addr_offset;
+}
+
+static loff_t spi_nor_otp_region_end(struct spi_nor *nor, int region)
+{
+	struct spi_nor_otp_info *info = &nor->params.otp_info;
+
+	return (info->otp_start_addr + region * info->otp_addr_offset
+		+ info->otp_size - 1);
+}
+
+static int spi_nor_otp_info(struct mtd_info *mtd, size_t len, size_t *retlen,
+			    struct otp_info *buf)
+{
+	struct spi_nor *nor = mtd_to_spi_nor(mtd);
+	int i;
+
+	for (i = 0; i < nor->params.otp_info.n_otps; i++) {
+		buf[i].start = spi_nor_otp_region_start(nor, i);
+		buf[i].length = nor->params.otp_info.otp_size;
+		buf[i].locked = !!(nor->params.otp_ops->is_locked(nor, i));
+	}
+
+	*retlen = nor->params.otp_info.n_otps * sizeof(*buf);
+
+	return 0;
+}
+
+static int spi_nor_otp_addr_to_region(struct spi_nor *nor, loff_t addr)
+{
+	int i;
+
+	for (i = 0; i < nor->params.otp_info.n_otps; i++)
+		if (addr >= spi_nor_otp_region_start(nor, i) &&
+		    addr <= spi_nor_otp_region_end(nor, i))
+			return i;
+
+	return -EINVAL;
+}
+
+static int _spi_nor_otp_read_write(struct mtd_info *mtd, loff_t ofs,
+				   size_t len, size_t *retlen, u_char *buf,
+				   bool is_write)
+{
+	struct spi_nor *nor = mtd_to_spi_nor(mtd);
+	enum spi_nor_ops ops = (is_write) ? SPI_NOR_OPS_OTP_WRITE
+					  : SPI_NOR_OPS_OTP_READ;
+	int region;
+	int ret;
+
+	*retlen = 0;
+
+	/* check boundaries */
+	region = spi_nor_otp_addr_to_region(nor, ofs);
+	if (region < 0)
+		return 0;
+
+	if (ofs < spi_nor_otp_region_start(nor, region))
+		return 0;
+
+	if ((ofs + len - 1) > spi_nor_otp_region_end(nor, region))
+		return 0;
+
+	ret = spi_nor_lock_and_prep(nor, ops);
+
+	if (is_write)
+		ret = nor->params.otp_ops->write(nor, ofs, len, buf);
+	else
+		ret = nor->params.otp_ops->read(nor, ofs, len, buf);
+
+	spi_nor_unlock_and_unprep(nor, ops);
+
+	if (ret < 0)
+		return ret;
+
+	*retlen = len;
+	return 0;
+}
+
+static int spi_nor_otp_read(struct mtd_info *mtd, loff_t from, size_t len,
+			    size_t *retlen, u_char *buf)
+{
+	return _spi_nor_otp_read_write(mtd, from, len, retlen, buf, false);
+}
+
+static int spi_nor_otp_write(struct mtd_info *mtd, loff_t to, size_t len,
+			     size_t *retlen, u_char *buf)
+{
+	return _spi_nor_otp_read_write(mtd, to, len, retlen, buf, true);
+}
+
+static int spi_nor_otp_lock(struct mtd_info *mtd, loff_t from, size_t len)
+{
+	struct spi_nor *nor = mtd_to_spi_nor(mtd);
+	int region;
+	int ret;
+
+	region = spi_nor_otp_addr_to_region(nor, from);
+	if (region < 0)
+		return -EINVAL;
+
+	if (len != nor->params.otp_info.otp_size)
+		return -EINVAL;
+
+	ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_OTP_LOCK);
+	if (ret)
+		return ret;
+
+	ret = nor->params.otp_ops->lock(nor, region);
+
+	spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_OTP_LOCK);
+
+	return ret;
+}
+
 int spi_nor_scan(struct spi_nor *nor, const char *name,
 		 const struct spi_nor_hwcaps *hwcaps)
 {
@@ -5197,6 +5337,13 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
 		mtd->_is_locked = spi_nor_is_locked;
 	}
 
+	if (nor->params.otp_ops) {
+		mtd->_get_user_prot_info = spi_nor_otp_info;
+		mtd->_read_user_prot_reg = spi_nor_otp_read;
+		mtd->_write_user_prot_reg = spi_nor_otp_write;
+		mtd->_lock_user_prot_reg = spi_nor_otp_lock;
+	}
+
 	/* sst nor chips use AAI word program */
 	if (info->flags & SST_WRITE)
 		mtd->_write = sst_write;
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 7cefad41acff..e427dcd72f79 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -232,6 +232,9 @@ enum spi_nor_ops {
 	SPI_NOR_OPS_LOCK,
 	SPI_NOR_OPS_UNLOCK,
 	SPI_NOR_OPS_IS_LOCKED,
+	SPI_NOR_OPS_OTP_READ,
+	SPI_NOR_OPS_OTP_WRITE,
+	SPI_NOR_OPS_OTP_LOCK,
 };
 
 enum spi_nor_option_flags {
@@ -510,6 +513,36 @@ struct spi_nor_locking_ops {
 	int (*is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len);
 };
 
+/**
+ * struct spi_nor_otp_info - Structure to describe the SPI NOR OTP region
+ * @otp_size:		size of one OTP region in bytes.
+ * @n_otps:		number of individual OTP regions.
+ * @otp_start_addr:	start address of the OTP area.
+ * @otp_addr_offset:	offset between consecutive OTP regions if there are
+ *			more than one.
+ */
+struct spi_nor_otp_info {
+	u32 otp_size;
+	int n_otps;
+	u32 otp_start_addr;
+	u32 otp_addr_offset;
+};
+
+/**
+ * struct spi_nor_otp_ops - SPI NOR OTP methods
+ * @read:	read from the SPI NOR OTP area.
+ * @write:	write to the SPI NOR OTP area.
+ * @lock:	lock an OTP region.
+ * @is_locked:	check if an OTP region of the SPI NOR is locked.
+ */
+struct spi_nor_otp_ops {
+	int (*read)(struct spi_nor *nor, loff_t ofs, uint64_t len, u8 *buf);
+	int (*write)(struct spi_nor *nor, loff_t ofs, uint64_t len, u8 *buf);
+	int (*lock)(struct spi_nor *nor, unsigned int region);
+	int (*is_locked)(struct spi_nor *nor, unsigned int region);
+};
+
+
 /**
  * struct spi_nor_flash_parameter - SPI NOR flash parameters and settings.
  * Includes legacy flash parameters and settings that can be overwritten
@@ -526,6 +559,7 @@ struct spi_nor_locking_ops {
  *                      higher index in the array, the higher priority.
  * @erase_map:		the erase map parsed from the SFDP Sector Map Parameter
  *                      Table.
+ * @otp_info:		describes the OTP regions.
  * @quad_enable:	enables SPI NOR quad mode.
  * @set_4byte:		puts the SPI NOR in 4 byte addressing mode.
  * @convert_addr:	converts an absolute address into something the flash
@@ -536,6 +570,7 @@ struct spi_nor_locking_ops {
  *                      e.g. different opcodes, specific address calculation,
  *                      page size, etc.
  * @locking_ops:	SPI NOR locking methods.
+ * @otp_ops:		SPI NOR OTP methods.
  */
 struct spi_nor_flash_parameter {
 	u64				size;
@@ -547,12 +582,15 @@ struct spi_nor_flash_parameter {
 
 	struct spi_nor_erase_map        erase_map;
 
+	struct spi_nor_otp_info otp_info;
+
 	int (*quad_enable)(struct spi_nor *nor);
 	int (*set_4byte)(struct spi_nor *nor, bool enable);
 	u32 (*convert_addr)(struct spi_nor *nor, u32 addr);
 	int (*setup)(struct spi_nor *nor, const struct spi_nor_hwcaps *hwcaps);
 
 	const struct spi_nor_locking_ops *locking_ops;
+	const struct spi_nor_otp_ops *otp_ops;
 };
 
 /**
-- 
2.20.1


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH 2/2] mtd: spi-nor: implement OTP support for Winbond flashes
  2020-01-08 23:36 [PATCH 0/2] mtd: spi-nor: OTP support Michael Walle
  2020-01-08 23:36 ` [PATCH 1/2] mtd: spi-nor: add " Michael Walle
@ 2020-01-08 23:36 ` Michael Walle
  2020-01-13  8:39   ` Michael Walle
  1 sibling, 1 reply; 5+ messages in thread
From: Michael Walle @ 2020-01-08 23:36 UTC (permalink / raw)
  To: linux-mtd, linux-kernel
  Cc: Vignesh Raghavendra, Rahul Bedarkar, Tudor Ambarus,
	Richard Weinberger, Rahul Bedarkar, Michael Walle, Miquel Raynal,
	Brian Norris

Use the new OTP ops to implement OTP access on Winbond flashes. Most
Winbond flashes provides up to four different OTP areas ("Security
Registers"). Newer flashes uses the first OTP area for SFDP data. Thus,
this only handles the last three areas and leave the first untouched.

This was tested on a Winbond W25Q32JW. Please note, that there is a
variant of the W25Q32JW which reuses the same JEDEC ID as the W25Q32FW
which could support all four OTP areas. But because we cannot distiguish
between these two, the driver only uses three areas on the W25Q32FW.

Signed-off-by: Michael Walle <michael@walle.cc>
---
 drivers/mtd/spi-nor/spi-nor.c | 132 ++++++++++++++++++++++++++++++++++
 include/linux/mtd/spi-nor.h   |  14 ++++
 2 files changed, 146 insertions(+)

diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 5eabaec70508..99d365cb63b1 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -2641,17 +2641,20 @@ static const struct flash_info spi_nor_ids[] = {
 		"w25q16dw", INFO(0xef6015, 0, 64 * 1024,  32,
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+			OTP_INFO(256, 3, 0x1000, 0x1000)
 	},
 	{
 		"w25q16jwim", INFO(0xef8015, 0, 64 * 1024,  32,
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+			OTP_INFO(256, 3, 0x1000, 0x1000)
 	},
 	{ "w25x32", INFO(0xef3016, 0, 64 * 1024,  64, SECT_4K) },
 	{
 		"w25q16jv-im/jm", INFO(0xef7015, 0, 64 * 1024,  32,
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+			OTP_INFO(256, 3, 0x1000, 0x1000)
 	},
 	{ "w25q20cl", INFO(0xef4012, 0, 64 * 1024,  4, SECT_4K) },
 	{ "w25q20bw", INFO(0xef5012, 0, 64 * 1024,  4, SECT_4K) },
@@ -2661,16 +2664,19 @@ static const struct flash_info spi_nor_ids[] = {
 		"w25q32dw", INFO(0xef6016, 0, 64 * 1024,  64,
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+			OTP_INFO(256, 3, 0x1000, 0x1000)
 	},
 	{
 		"w25q32jv", INFO(0xef7016, 0, 64 * 1024,  64,
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+			OTP_INFO(256, 3, 0x1000, 0x1000)
 	},
 	{
 		"w25q32jwim", INFO(0xef8016, 0, 64 * 1024,  64,
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+			OTP_INFO(256, 3, 0x1000, 0x1000)
 	},
 	{ "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
 	{ "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
@@ -2678,26 +2684,31 @@ static const struct flash_info spi_nor_ids[] = {
 		"w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128,
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+			OTP_INFO(256, 3, 0x1000, 0x1000)
 	},
 	{
 		"w25q64jwim", INFO(0xef8017, 0, 64 * 1024, 128,
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+			OTP_INFO(256, 3, 0x1000, 0x1000)
 	},
 	{
 		"w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256,
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+			OTP_INFO(256, 3, 0x1000, 0x1000)
 	},
 	{
 		"w25q128jv", INFO(0xef7018, 0, 64 * 1024, 256,
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+			OTP_INFO(256, 3, 0x1000, 0x1000)
 	},
 	{
 		"w25q128jwim", INFO(0xef8018, 0, 64 * 1024, 256,
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+			OTP_INFO(256, 3, 0x1000, 0x1000)
 	},
 	{ "w25q80", INFO(0xef5014, 0, 64 * 1024,  16, SECT_4K) },
 	{ "w25q80bl", INFO(0xef4014, 0, 64 * 1024,  16, SECT_4K) },
@@ -4645,6 +4656,125 @@ static int spi_nor_setup(struct spi_nor *nor,
 	return nor->params.setup(nor, hwcaps);
 }
 
+static int winbond_otp_read(struct spi_nor *nor, loff_t addr, uint64_t len,
+			    u8 *buf)
+{
+	u8 addr_width, read_opcode, read_dummy;
+	enum spi_nor_protocol read_proto;
+	int ret;
+
+	read_opcode = nor->read_opcode;
+	addr_width = nor->addr_width;
+	read_dummy = nor->read_dummy;
+	read_proto = nor->read_proto;
+
+	nor->read_opcode = SPINOR_OP_WB_RSECR;
+	nor->addr_width = 3;
+	nor->read_dummy = 8;
+	nor->read_proto = SNOR_PROTO_1_1_1;
+
+	ret = spi_nor_read_raw(nor, addr, len, buf);
+
+	nor->read_opcode = read_opcode;
+	nor->addr_width = addr_width;
+	nor->read_dummy = read_dummy;
+	nor->read_proto = read_proto;
+
+	return ret;
+}
+
+static int winbond_otp_write(struct spi_nor *nor, loff_t addr, uint64_t len,
+			     u8 *buf)
+{
+	u8 addr_width, program_opcode;
+	enum spi_nor_protocol write_proto;
+	int ret;
+
+	program_opcode = nor->program_opcode;
+	addr_width = nor->addr_width;
+	write_proto = nor->write_proto;
+
+	nor->program_opcode = SPINOR_OP_WB_PSECR;
+	nor->addr_width = 3;
+	nor->write_proto = SNOR_PROTO_1_1_1;
+
+	/*
+	 * We only support a write to one single page. For now all winbond
+	 * flashes only have one page per OTP region.
+	 */
+	ret = spi_nor_write_enable(nor);
+	if (ret)
+		goto out;
+
+	ret = spi_nor_write_data(nor, addr, len, buf);
+	if (ret < 0)
+		goto out;
+
+	ret = spi_nor_wait_till_ready(nor);
+
+out:
+	nor->program_opcode = program_opcode;
+	nor->addr_width = addr_width;
+	nor->write_proto = write_proto;
+
+	return ret;
+}
+
+static int _winbond_otp_lock_bit(unsigned int region)
+{
+	static const int lock_bits[] = { SR2_WB_LB1, SR2_WB_LB2, SR2_WB_LB3 };
+
+	if (region >= ARRAY_SIZE(lock_bits))
+		return -EINVAL;
+
+	return lock_bits[region];
+}
+
+static int winbond_otp_lock(struct spi_nor *nor, unsigned int region)
+{
+	int lock_bit;
+	u8 sr2;
+	int ret;
+
+	lock_bit = _winbond_otp_lock_bit(region);
+	if (lock_bit < 0)
+		return lock_bit;
+
+	ret = spi_nor_read_cr(nor, &sr2);
+	if (ret)
+		return ret;
+
+	/* check if its already locked */
+	if (sr2 & lock_bit)
+		return 0;
+
+	return spi_nor_write_16bit_cr_and_check(nor, sr2 | lock_bit);
+}
+
+static int winbond_otp_is_locked(struct spi_nor *nor, unsigned int region)
+{
+	int lock_bit;
+	u8 sr2;
+	int ret;
+
+	lock_bit = _winbond_otp_lock_bit(region);
+	if (lock_bit < 0)
+		return lock_bit;
+
+	ret = spi_nor_read_cr(nor, &sr2);
+	if (ret)
+		return ret;
+
+	return (sr2 & lock_bit);
+}
+
+static const struct spi_nor_otp_ops winbond_otp_ops = {
+	.read = winbond_otp_read,
+	.write = winbond_otp_write,
+	.lock = winbond_otp_lock,
+	.is_locked = winbond_otp_is_locked,
+};
+
 static void atmel_set_default_init(struct spi_nor *nor)
 {
 	nor->flags |= SNOR_F_HAS_LOCK;
@@ -4681,6 +4811,8 @@ static void st_micron_set_default_init(struct spi_nor *nor)
 static void winbond_set_default_init(struct spi_nor *nor)
 {
 	nor->params.set_4byte = winbond_set_4byte;
+	if (nor->params.otp_info.n_otps)
+		nor->params.otp_ops = &winbond_otp_ops;
 }
 
 /**
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index e427dcd72f79..cc847ed06ef3 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -121,6 +121,20 @@
 #define SPINOR_OP_RD_EVCR      0x65    /* Read EVCR register */
 #define SPINOR_OP_WD_EVCR      0x61    /* Write EVCR register */
 
+/* Used for Winbond flashes only. */
+#define SPINOR_OP_WB_ESECR	0x44	/* Erase Security registers */
+#define SPINOR_OP_WB_PSECR	0x42	/* Program Security registers */
+#define SPINOR_OP_WB_RSECR	0x48	/* Read Security registers */
+
+/*
+ * Warning: LB0 (and thus the security register 0) is used for the SFDP
+ * data on all newer flashes.
+ */
+#define SR2_WB_LB0		BIT(2)	/* Security Register Lock Bit 0 */
+#define SR2_WB_LB1		BIT(3)	/* Security Register Lock Bit 1 */
+#define SR2_WB_LB2		BIT(4)	/* Security Register Lock Bit 2 */
+#define SR2_WB_LB3		BIT(5)	/* Security Register Lock Bit 3 */
+
 /* Status Register bits. */
 #define SR_WIP			BIT(0)	/* Write in progress */
 #define SR_WEL			BIT(1)	/* Write enable latch */
-- 
2.20.1


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^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH 1/2] mtd: spi-nor: add OTP support
  2020-01-08 23:36 ` [PATCH 1/2] mtd: spi-nor: add " Michael Walle
@ 2020-01-13  8:37   ` Michael Walle
  0 siblings, 0 replies; 5+ messages in thread
From: Michael Walle @ 2020-01-13  8:37 UTC (permalink / raw)
  To: linux-mtd, linux-kernel
  Cc: Vignesh Raghavendra, Rahul Bedarkar, Tudor Ambarus,
	Richard Weinberger, Rahul Bedarkar, Miquel Raynal, Brian Norris

Am 2020-01-09 00:36, schrieb Michael Walle:
> Implement the MTD callbacks for the OTP methods for the SPI NOR
> subsystem.
> 
> Usually, the OTP area of a SPI flash can be accessed like the normal
> memory, eg by offset addressing; except that you either have to use
> special read/write commands (Winbond) or you have to enter (and exit) a
> specific OTP mode (Macronix, Micron). Sometimes there are individual
> regions, which might have individual offsets. Therefore, it is possible
> to specify the starting address of the first regions as well as the
> distance between two regions (Winbond).
> 
> Additionally, the regions might be locked down. Once locked, no further
> write access is possible.
> 
> Signed-off-by: Michael Walle <michael@walle.cc>
> ---
>  drivers/mtd/spi-nor/spi-nor.c | 147 ++++++++++++++++++++++++++++++++++
>  include/linux/mtd/spi-nor.h   |  38 +++++++++
>  2 files changed, 185 insertions(+)
> 
> diff --git a/drivers/mtd/spi-nor/spi-nor.c 
> b/drivers/mtd/spi-nor/spi-nor.c
> index 818cb9393f41..5eabaec70508 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -241,6 +241,15 @@ struct flash_info {
> 
>  	/* Part specific fixup hooks. */
>  	const struct spi_nor_fixups *fixups;
> +
> +	/* OTP size in bytes */
> +	u16 otp_size;
> +	/* Number of OTP banks */
> +	u16 n_otps;
> +	/* Start address of OTP area */
> +	u32 otp_start_addr;
> +	/* Offset between consecutive OTP banks if there are more than one */
> +	u32 otp_addr_offset;
>  };
> 
>  #define JEDEC_MFR(info)	((info)->id[0])
> @@ -2240,6 +2249,12 @@ static int spi_nor_sr2_bit7_quad_enable(struct
> spi_nor *nor)
>  		.addr_width = 3,					\
>  		.flags = SPI_NOR_NO_FR | SPI_S3AN,
> 
> +#define OTP_INFO(_otp_size, _n_otps, _otp_start_addr, 
> _otp_addr_offset)	\
> +		.otp_size = (_otp_size),				\
> +		.n_otps = (_n_otps),					\
> +		.otp_start_addr = (_otp_start_addr),			\
> +		.otp_addr_offset = (_otp_addr_offset),
> +
>  static int
>  is25lp256_post_bfpt_fixups(struct spi_nor *nor,
>  			   const struct sfdp_parameter_header *bfpt_header,
> @@ -4827,6 +4842,12 @@ static void spi_nor_info_init_params(struct 
> spi_nor *nor)
>  	spi_nor_set_erase_type(&map->erase_type[i], info->sector_size,
>  			       SPINOR_OP_SE);
>  	spi_nor_init_uniform_erase_map(map, erase_mask, params->size);
> +
> +	/* OTP parameters */
> +	nor->params.otp_info.otp_size = info->otp_size;
> +	nor->params.otp_info.n_otps = info->n_otps;
> +	nor->params.otp_info.otp_start_addr = info->otp_start_addr;
> +	nor->params.otp_info.otp_addr_offset = info->otp_addr_offset;
>  }
> 
>  static void spansion_post_sfdp_fixups(struct spi_nor *nor)
> @@ -5122,6 +5143,125 @@ static const struct flash_info
> *spi_nor_get_flash_info(struct spi_nor *nor,
>  	return info;
>  }
> 
> +static loff_t spi_nor_otp_region_start(struct spi_nor *nor, int 
> region)
> +{
> +	struct spi_nor_otp_info *info = &nor->params.otp_info;
> +
> +	return info->otp_start_addr + region * info->otp_addr_offset;
> +}
> +
> +static loff_t spi_nor_otp_region_end(struct spi_nor *nor, int region)
> +{
> +	struct spi_nor_otp_info *info = &nor->params.otp_info;
> +
> +	return (info->otp_start_addr + region * info->otp_addr_offset
> +		+ info->otp_size - 1);
> +}
> +
> +static int spi_nor_otp_info(struct mtd_info *mtd, size_t len, size_t 
> *retlen,
> +			    struct otp_info *buf)
> +{
> +	struct spi_nor *nor = mtd_to_spi_nor(mtd);
> +	int i;
> +
> +	for (i = 0; i < nor->params.otp_info.n_otps; i++) {
> +		buf[i].start = spi_nor_otp_region_start(nor, i);
> +		buf[i].length = nor->params.otp_info.otp_size;
> +		buf[i].locked = !!(nor->params.otp_ops->is_locked(nor, i));

is_locked() might return an error. will be fixed in the next version.


> +	}
> +
> +	*retlen = nor->params.otp_info.n_otps * sizeof(*buf);
> +
> +	return 0;
> +}
> +
> +static int spi_nor_otp_addr_to_region(struct spi_nor *nor, loff_t 
> addr)
> +{
> +	int i;
> +
> +	for (i = 0; i < nor->params.otp_info.n_otps; i++)
> +		if (addr >= spi_nor_otp_region_start(nor, i) &&
> +		    addr <= spi_nor_otp_region_end(nor, i))
> +			return i;
> +
> +	return -EINVAL;
> +}
> +
> +static int _spi_nor_otp_read_write(struct mtd_info *mtd, loff_t ofs,
> +				   size_t len, size_t *retlen, u_char *buf,
> +				   bool is_write)
> +{
> +	struct spi_nor *nor = mtd_to_spi_nor(mtd);
> +	enum spi_nor_ops ops = (is_write) ? SPI_NOR_OPS_OTP_WRITE
> +					  : SPI_NOR_OPS_OTP_READ;
> +	int region;
> +	int ret;
> +
> +	*retlen = 0;
> +
> +	/* check boundaries */
> +	region = spi_nor_otp_addr_to_region(nor, ofs);
> +	if (region < 0)
> +		return 0;
> +
> +	if (ofs < spi_nor_otp_region_start(nor, region))
> +		return 0;
> +
> +	if ((ofs + len - 1) > spi_nor_otp_region_end(nor, region))
> +		return 0;
> +
> +	ret = spi_nor_lock_and_prep(nor, ops);
> +
> +	if (is_write)
> +		ret = nor->params.otp_ops->write(nor, ofs, len, buf);
> +	else
> +		ret = nor->params.otp_ops->read(nor, ofs, len, buf);
> +
> +	spi_nor_unlock_and_unprep(nor, ops);
> +
> +	if (ret < 0)
> +		return ret;
> +
> +	*retlen = len;
> +	return 0;
> +}
> +
> +static int spi_nor_otp_read(struct mtd_info *mtd, loff_t from, size_t 
> len,
> +			    size_t *retlen, u_char *buf)
> +{
> +	return _spi_nor_otp_read_write(mtd, from, len, retlen, buf, false);
> +}
> +
> +static int spi_nor_otp_write(struct mtd_info *mtd, loff_t to, size_t 
> len,
> +			     size_t *retlen, u_char *buf)
> +{
> +	return _spi_nor_otp_read_write(mtd, to, len, retlen, buf, true);
> +}
> +
> +static int spi_nor_otp_lock(struct mtd_info *mtd, loff_t from, size_t 
> len)
> +{
> +	struct spi_nor *nor = mtd_to_spi_nor(mtd);
> +	int region;
> +	int ret;
> +
> +	region = spi_nor_otp_addr_to_region(nor, from);
> +	if (region < 0)
> +		return -EINVAL;
> +
> +	if (len != nor->params.otp_info.otp_size)
> +		return -EINVAL;
> +
> +	ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_OTP_LOCK);
> +	if (ret)
> +		return ret;
> +
> +	ret = nor->params.otp_ops->lock(nor, region);
> +
> +	spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_OTP_LOCK);
> +
> +	return ret;
> +}
> +
>  int spi_nor_scan(struct spi_nor *nor, const char *name,
>  		 const struct spi_nor_hwcaps *hwcaps)
>  {
> @@ -5197,6 +5337,13 @@ int spi_nor_scan(struct spi_nor *nor, const char 
> *name,
>  		mtd->_is_locked = spi_nor_is_locked;
>  	}
> 
> +	if (nor->params.otp_ops) {
> +		mtd->_get_user_prot_info = spi_nor_otp_info;
> +		mtd->_read_user_prot_reg = spi_nor_otp_read;
> +		mtd->_write_user_prot_reg = spi_nor_otp_write;
> +		mtd->_lock_user_prot_reg = spi_nor_otp_lock;
> +	}
> +
>  	/* sst nor chips use AAI word program */
>  	if (info->flags & SST_WRITE)
>  		mtd->_write = sst_write;
> diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
> index 7cefad41acff..e427dcd72f79 100644
> --- a/include/linux/mtd/spi-nor.h
> +++ b/include/linux/mtd/spi-nor.h
> @@ -232,6 +232,9 @@ enum spi_nor_ops {
>  	SPI_NOR_OPS_LOCK,
>  	SPI_NOR_OPS_UNLOCK,
>  	SPI_NOR_OPS_IS_LOCKED,
> +	SPI_NOR_OPS_OTP_READ,
> +	SPI_NOR_OPS_OTP_WRITE,
> +	SPI_NOR_OPS_OTP_LOCK,
>  };
> 
>  enum spi_nor_option_flags {
> @@ -510,6 +513,36 @@ struct spi_nor_locking_ops {
>  	int (*is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len);
>  };
> 
> +/**
> + * struct spi_nor_otp_info - Structure to describe the SPI NOR OTP 
> region
> + * @otp_size:		size of one OTP region in bytes.
> + * @n_otps:		number of individual OTP regions.
> + * @otp_start_addr:	start address of the OTP area.
> + * @otp_addr_offset:	offset between consecutive OTP regions if there 
> are
> + *			more than one.
> + */
> +struct spi_nor_otp_info {
> +	u32 otp_size;
> +	int n_otps;
> +	u32 otp_start_addr;
> +	u32 otp_addr_offset;
> +};
> +
> +/**
> + * struct spi_nor_otp_ops - SPI NOR OTP methods
> + * @read:	read from the SPI NOR OTP area.
> + * @write:	write to the SPI NOR OTP area.
> + * @lock:	lock an OTP region.
> + * @is_locked:	check if an OTP region of the SPI NOR is locked.
> + */
> +struct spi_nor_otp_ops {
> +	int (*read)(struct spi_nor *nor, loff_t ofs, uint64_t len, u8 *buf);
> +	int (*write)(struct spi_nor *nor, loff_t ofs, uint64_t len, u8 *buf);
> +	int (*lock)(struct spi_nor *nor, unsigned int region);
> +	int (*is_locked)(struct spi_nor *nor, unsigned int region);
> +};
> +
> +
>  /**
>   * struct spi_nor_flash_parameter - SPI NOR flash parameters and 
> settings.
>   * Includes legacy flash parameters and settings that can be 
> overwritten
> @@ -526,6 +559,7 @@ struct spi_nor_locking_ops {
>   *                      higher index in the array, the higher 
> priority.
>   * @erase_map:		the erase map parsed from the SFDP Sector Map 
> Parameter
>   *                      Table.
> + * @otp_info:		describes the OTP regions.
>   * @quad_enable:	enables SPI NOR quad mode.
>   * @set_4byte:		puts the SPI NOR in 4 byte addressing mode.
>   * @convert_addr:	converts an absolute address into something the 
> flash
> @@ -536,6 +570,7 @@ struct spi_nor_locking_ops {
>   *                      e.g. different opcodes, specific address 
> calculation,
>   *                      page size, etc.
>   * @locking_ops:	SPI NOR locking methods.
> + * @otp_ops:		SPI NOR OTP methods.
>   */
>  struct spi_nor_flash_parameter {
>  	u64				size;
> @@ -547,12 +582,15 @@ struct spi_nor_flash_parameter {
> 
>  	struct spi_nor_erase_map        erase_map;
> 
> +	struct spi_nor_otp_info otp_info;
> +
>  	int (*quad_enable)(struct spi_nor *nor);
>  	int (*set_4byte)(struct spi_nor *nor, bool enable);
>  	u32 (*convert_addr)(struct spi_nor *nor, u32 addr);
>  	int (*setup)(struct spi_nor *nor, const struct spi_nor_hwcaps 
> *hwcaps);
> 
>  	const struct spi_nor_locking_ops *locking_ops;
> +	const struct spi_nor_otp_ops *otp_ops;
>  };
> 
>  /**

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^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH 2/2] mtd: spi-nor: implement OTP support for Winbond flashes
  2020-01-08 23:36 ` [PATCH 2/2] mtd: spi-nor: implement OTP support for Winbond flashes Michael Walle
@ 2020-01-13  8:39   ` Michael Walle
  0 siblings, 0 replies; 5+ messages in thread
From: Michael Walle @ 2020-01-13  8:39 UTC (permalink / raw)
  To: linux-mtd, linux-kernel
  Cc: Vignesh Raghavendra, Rahul Bedarkar, Tudor Ambarus,
	Richard Weinberger, Rahul Bedarkar, Miquel Raynal, Brian Norris

Am 2020-01-09 00:36, schrieb Michael Walle:
> Use the new OTP ops to implement OTP access on Winbond flashes. Most
> Winbond flashes provides up to four different OTP areas ("Security
> Registers"). Newer flashes uses the first OTP area for SFDP data. Thus,
> this only handles the last three areas and leave the first untouched.
> 
> This was tested on a Winbond W25Q32JW. Please note, that there is a
> variant of the W25Q32JW which reuses the same JEDEC ID as the W25Q32FW
> which could support all four OTP areas. But because we cannot 
> distiguish
> between these two, the driver only uses three areas on the W25Q32FW.
> 
> Signed-off-by: Michael Walle <michael@walle.cc>
> ---
>  drivers/mtd/spi-nor/spi-nor.c | 132 ++++++++++++++++++++++++++++++++++
>  include/linux/mtd/spi-nor.h   |  14 ++++
>  2 files changed, 146 insertions(+)
> 
> diff --git a/drivers/mtd/spi-nor/spi-nor.c 
> b/drivers/mtd/spi-nor/spi-nor.c
> index 5eabaec70508..99d365cb63b1 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -2641,17 +2641,20 @@ static const struct flash_info spi_nor_ids[] = 
> {
>  		"w25q16dw", INFO(0xef6015, 0, 64 * 1024,  32,
>  			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
>  			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
> +			OTP_INFO(256, 3, 0x1000, 0x1000)
>  	},
>  	{
>  		"w25q16jwim", INFO(0xef8015, 0, 64 * 1024,  32,
>  			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
>  			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
> +			OTP_INFO(256, 3, 0x1000, 0x1000)
>  	},
>  	{ "w25x32", INFO(0xef3016, 0, 64 * 1024,  64, SECT_4K) },
>  	{
>  		"w25q16jv-im/jm", INFO(0xef7015, 0, 64 * 1024,  32,
>  			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
>  			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
> +			OTP_INFO(256, 3, 0x1000, 0x1000)
>  	},
>  	{ "w25q20cl", INFO(0xef4012, 0, 64 * 1024,  4, SECT_4K) },
>  	{ "w25q20bw", INFO(0xef5012, 0, 64 * 1024,  4, SECT_4K) },
> @@ -2661,16 +2664,19 @@ static const struct flash_info spi_nor_ids[] = 
> {
>  		"w25q32dw", INFO(0xef6016, 0, 64 * 1024,  64,
>  			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
>  			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
> +			OTP_INFO(256, 3, 0x1000, 0x1000)
>  	},
>  	{
>  		"w25q32jv", INFO(0xef7016, 0, 64 * 1024,  64,
>  			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
>  			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
> +			OTP_INFO(256, 3, 0x1000, 0x1000)
>  	},
>  	{
>  		"w25q32jwim", INFO(0xef8016, 0, 64 * 1024,  64,
>  			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
>  			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
> +			OTP_INFO(256, 3, 0x1000, 0x1000)
>  	},
>  	{ "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
>  	{ "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
> @@ -2678,26 +2684,31 @@ static const struct flash_info spi_nor_ids[] = 
> {
>  		"w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128,
>  			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
>  			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
> +			OTP_INFO(256, 3, 0x1000, 0x1000)
>  	},
>  	{
>  		"w25q64jwim", INFO(0xef8017, 0, 64 * 1024, 128,
>  			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
>  			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
> +			OTP_INFO(256, 3, 0x1000, 0x1000)
>  	},
>  	{
>  		"w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256,
>  			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
>  			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
> +			OTP_INFO(256, 3, 0x1000, 0x1000)
>  	},
>  	{
>  		"w25q128jv", INFO(0xef7018, 0, 64 * 1024, 256,
>  			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
>  			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
> +			OTP_INFO(256, 3, 0x1000, 0x1000)
>  	},
>  	{
>  		"w25q128jwim", INFO(0xef8018, 0, 64 * 1024, 256,
>  			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
>  			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
> +			OTP_INFO(256, 3, 0x1000, 0x1000)
>  	},
>  	{ "w25q80", INFO(0xef5014, 0, 64 * 1024,  16, SECT_4K) },
>  	{ "w25q80bl", INFO(0xef4014, 0, 64 * 1024,  16, SECT_4K) },
> @@ -4645,6 +4656,125 @@ static int spi_nor_setup(struct spi_nor *nor,
>  	return nor->params.setup(nor, hwcaps);
>  }
> 
> +static int winbond_otp_read(struct spi_nor *nor, loff_t addr, uint64_t 
> len,
> +			    u8 *buf)
> +{
> +	u8 addr_width, read_opcode, read_dummy;
> +	enum spi_nor_protocol read_proto;
> +	int ret;
> +
> +	read_opcode = nor->read_opcode;
> +	addr_width = nor->addr_width;
> +	read_dummy = nor->read_dummy;
> +	read_proto = nor->read_proto;
> +
> +	nor->read_opcode = SPINOR_OP_WB_RSECR;
> +	nor->addr_width = 3;
> +	nor->read_dummy = 8;
> +	nor->read_proto = SNOR_PROTO_1_1_1;
> +
> +	ret = spi_nor_read_raw(nor, addr, len, buf);
> +
> +	nor->read_opcode = read_opcode;
> +	nor->addr_width = addr_width;
> +	nor->read_dummy = read_dummy;
> +	nor->read_proto = read_proto;
> +
> +	return ret;
> +}
> +
> +static int winbond_otp_write(struct spi_nor *nor, loff_t addr, 
> uint64_t len,
> +			     u8 *buf)
> +{
> +	u8 addr_width, program_opcode;
> +	enum spi_nor_protocol write_proto;
> +	int ret;
> +
> +	program_opcode = nor->program_opcode;
> +	addr_width = nor->addr_width;
> +	write_proto = nor->write_proto;
> +
> +	nor->program_opcode = SPINOR_OP_WB_PSECR;
> +	nor->addr_width = 3;
> +	nor->write_proto = SNOR_PROTO_1_1_1;
> +
> +	/*
> +	 * We only support a write to one single page. For now all winbond
> +	 * flashes only have one page per OTP region.
> +	 */
> +	ret = spi_nor_write_enable(nor);
> +	if (ret)
> +		goto out;
> +
> +	ret = spi_nor_write_data(nor, addr, len, buf);
> +	if (ret < 0)
> +		goto out;
> +
> +	ret = spi_nor_wait_till_ready(nor);
> +
> +out:
> +	nor->program_opcode = program_opcode;
> +	nor->addr_width = addr_width;
> +	nor->write_proto = write_proto;
> +
> +	return ret;
> +}
> +
> +static int _winbond_otp_lock_bit(unsigned int region)
> +{
> +	static const int lock_bits[] = { SR2_WB_LB1, SR2_WB_LB2, SR2_WB_LB3 
> };
> +
> +	if (region >= ARRAY_SIZE(lock_bits))
> +		return -EINVAL;
> +
> +	return lock_bits[region];
> +}
> +
> +static int winbond_otp_lock(struct spi_nor *nor, unsigned int region)
> +{
> +	int lock_bit;
> +	u8 sr2;

will be "u8 *sr2 = nor->bouncebuf"; in the next version

> +	int ret;
> +
> +	lock_bit = _winbond_otp_lock_bit(region);
> +	if (lock_bit < 0)
> +		return lock_bit;
> +
> +	ret = spi_nor_read_cr(nor, &sr2);
> +	if (ret)
> +		return ret;
> +
> +	/* check if its already locked */
> +	if (sr2 & lock_bit)
> +		return 0;
> +
> +	return spi_nor_write_16bit_cr_and_check(nor, sr2 | lock_bit);
> +}
> +
> +static int winbond_otp_is_locked(struct spi_nor *nor, unsigned int 
> region)
> +{
> +	int lock_bit;
> +	u8 sr2;

likewise

> +	int ret;
> +
> +	lock_bit = _winbond_otp_lock_bit(region);
> +	if (lock_bit < 0)
> +		return lock_bit;
> +
> +	ret = spi_nor_read_cr(nor, &sr2);
> +	if (ret)
> +		return ret;
> +
> +	return (sr2 & lock_bit);
> +}
> +
> +static const struct spi_nor_otp_ops winbond_otp_ops = {
> +	.read = winbond_otp_read,
> +	.write = winbond_otp_write,
> +	.lock = winbond_otp_lock,
> +	.is_locked = winbond_otp_is_locked,
> +};
> +
>  static void atmel_set_default_init(struct spi_nor *nor)
>  {
>  	nor->flags |= SNOR_F_HAS_LOCK;
> @@ -4681,6 +4811,8 @@ static void st_micron_set_default_init(struct
> spi_nor *nor)
>  static void winbond_set_default_init(struct spi_nor *nor)
>  {
>  	nor->params.set_4byte = winbond_set_4byte;
> +	if (nor->params.otp_info.n_otps)
> +		nor->params.otp_ops = &winbond_otp_ops;
>  }
> 
>  /**
> diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
> index e427dcd72f79..cc847ed06ef3 100644
> --- a/include/linux/mtd/spi-nor.h
> +++ b/include/linux/mtd/spi-nor.h
> @@ -121,6 +121,20 @@
>  #define SPINOR_OP_RD_EVCR      0x65    /* Read EVCR register */
>  #define SPINOR_OP_WD_EVCR      0x61    /* Write EVCR register */
> 
> +/* Used for Winbond flashes only. */
> +#define SPINOR_OP_WB_ESECR	0x44	/* Erase Security registers */
> +#define SPINOR_OP_WB_PSECR	0x42	/* Program Security registers */
> +#define SPINOR_OP_WB_RSECR	0x48	/* Read Security registers */
> +
> +/*
> + * Warning: LB0 (and thus the security register 0) is used for the 
> SFDP
> + * data on all newer flashes.
> + */
> +#define SR2_WB_LB0		BIT(2)	/* Security Register Lock Bit 0 */
> +#define SR2_WB_LB1		BIT(3)	/* Security Register Lock Bit 1 */
> +#define SR2_WB_LB2		BIT(4)	/* Security Register Lock Bit 2 */
> +#define SR2_WB_LB3		BIT(5)	/* Security Register Lock Bit 3 */
> +
>  /* Status Register bits. */
>  #define SR_WIP			BIT(0)	/* Write in progress */
>  #define SR_WEL			BIT(1)	/* Write enable latch */

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^ permalink raw reply	[flat|nested] 5+ messages in thread

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Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-01-08 23:36 [PATCH 0/2] mtd: spi-nor: OTP support Michael Walle
2020-01-08 23:36 ` [PATCH 1/2] mtd: spi-nor: add " Michael Walle
2020-01-13  8:37   ` Michael Walle
2020-01-08 23:36 ` [PATCH 2/2] mtd: spi-nor: implement OTP support for Winbond flashes Michael Walle
2020-01-13  8:39   ` Michael Walle

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