From: Michael Walle <michael@walle.cc>
To: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
Cc: greg.malysa@timesys.com,
Tudor Ambarus <tudor.ambarus@microchip.com>,
Pratyush Yadav <pratyush@kernel.org>,
Miquel Raynal <miquel.raynal@bootlin.com>,
Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>,
linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4 3/3] mtd: spi-nor: Add support for IS25LX256 operating in 1S-8S-8S octal read mode
Date: Fri, 02 Dec 2022 16:20:47 +0100 [thread overview]
Message-ID: <fa6f089e529b649603db4cf7024ae59b@walle.cc> (raw)
In-Reply-To: <20221202135539.271936-4-nathan.morrison@timesys.com>
Am 2022-12-02 14:55, schrieb Nathan Barrett-Morrison:
> This adds the IS25LX256 chip into the ISSI flash_info parts table
>
> Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
> ---
> drivers/mtd/spi-nor/issi.c | 32 ++++++++++++++++++++++++++++++++
> 1 file changed, 32 insertions(+)
>
> diff --git a/drivers/mtd/spi-nor/issi.c b/drivers/mtd/spi-nor/issi.c
> index 89a66a19d754..362bc3603d8f 100644
> --- a/drivers/mtd/spi-nor/issi.c
> +++ b/drivers/mtd/spi-nor/issi.c
> @@ -29,6 +29,35 @@ static const struct spi_nor_fixups is25lp256_fixups
> = {
> .post_bfpt = is25lp256_post_bfpt_fixups,
> };
>
> +static int
> +is25lx256_post_bfpt_fixups(struct spi_nor *nor,
> + const struct sfdp_parameter_header *bfpt_header,
> + const struct sfdp_bfpt *bfpt)
> +{
> + /*
> + * IS25LX256 supports both 1S-1S-8S and 1S-8S-8S.
> + * However, the BFPT does not contain any information denoting this
> + * functionality, so the proper fast read opcodes are never setup.
> + * We're correcting this issue via the fixup below. Page program
> + * commands are detected and setup properly via the 4BAIT lookup.
> + */
> + params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
> + spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_8],
> + 0, 8, SPINOR_OP_READ_1_1_8,
> + SNOR_PROTO_1_1_8);
> +
> + params->hwcaps.mask |= SNOR_HWCAPS_READ_1_8_8;
> + spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_8_8],
> + 0, 16, SPINOR_OP_READ_1_8_8,
> + SNOR_PROTO_1_8_8);
> +
> + return 0;
> +}
> +
> +static const struct spi_nor_fixups is25lx256_fixups = {
> + .post_bfpt = is25lx256_post_bfpt_fixups,
> +};
> +
> static void pm25lv_nor_late_init(struct spi_nor *nor)
> {
> struct spi_nor_erase_map *map = &nor->params->erase_map;
> @@ -74,6 +103,9 @@ static const struct flash_info issi_nor_parts[] = {
> NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
> FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
> .fixups = &is25lp256_fixups },
> + { "is25lx256", INFO(0x9d5a19, 0, 0, 0)
> + PARSE_SFDP
> + .fixups = &is25lx256_fixups },
Very nice!
Subject is slightly wrong because you fix up the BFPT to get
correct 1-1-8 and 1-8-8 read modes.
With that fixed:
Reviewed-by: Michael Walle <michael@walle.cc>
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next prev parent reply other threads:[~2022-12-02 15:21 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-02 13:55 [PATCH v4 0/3] mtd: spi-nor: Extend SFDP to support additional octal modes as per latest JEDEC standard Nathan Barrett-Morrison
2022-12-02 13:55 ` [PATCH v4 1/3] mtd: spi-nor: Extend SFDP 4byte address instruction lookup table with new octal modes as per JEDEC JESD216F Nathan Barrett-Morrison
2022-12-02 15:13 ` Michael Walle
2022-12-26 8:12 ` Tudor Ambarus
2022-12-02 13:55 ` [PATCH v4 2/3] mtd: spi-nor: Add additional octal-mode page program flags to be checked during SFDP 4BAIT parsing Nathan Barrett-Morrison
2022-12-02 15:16 ` Michael Walle
2022-12-26 8:14 ` Tudor Ambarus
2022-12-02 13:55 ` [PATCH v4 3/3] mtd: spi-nor: Add support for IS25LX256 operating in 1S-8S-8S octal read mode Nathan Barrett-Morrison
2022-12-02 15:20 ` Michael Walle [this message]
2022-12-03 4:32 ` kernel test robot
2022-12-03 7:44 ` kernel test robot
2022-12-26 8:04 ` Tudor Ambarus
2022-12-26 8:17 ` Tudor Ambarus
2022-12-27 12:37 ` Michael Walle
2022-12-27 13:24 ` Tudor Ambarus
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