Hi all,

Today's linux-next merge of the sound-asoc tree got a conflict in
sound/soc/fsl/fsl_ssi.c between commit bf02c7cb4314 ("ASoC: fsl_ssi: Add
dual fifo mode support") from the slave-dma tree and commit 2924a9981006
("ASoC: fsl_ssi: Add monaural audio support for non-ac97 interface") from
the sound-asoc tree.

I fixed it up (see below) and can carry the fix as necessary (no action
is required).

-- 
Cheers,
Stephen Rothwell                    sfr@canb.auug.org.au

diff --cc sound/soc/fsl/fsl_ssi.c
index f43be6d4c549,90ff1071e29c..000000000000
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@@ -143,7 -143,7 +143,8 @@@ struct fsl_ssi_private 
  	bool ssi_on_imx;
  	bool imx_ac97;
  	bool use_dma;
 +	bool use_dual_fifo;
+ 	u8 i2s_mode;
  	struct clk *clk;
  	struct snd_dmaengine_dai_dma_data dma_params_tx;
  	struct snd_dmaengine_dai_dma_data dma_params_rx;
@@@ -388,38 -417,9 +418,15 @@@ static int fsl_ssi_setup(struct fsl_ssi
  	 * because it is also running without an active substream. Normally SSI
  	 * is only enabled when there is a substream.
  	 */
- 	if (ssi_private->imx_ac97) {
- 		/*
- 		 * Setup the clock control register
- 		 */
- 		write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
- 				&ssi->stccr);
- 		write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
- 				&ssi->srccr);
- 
- 		/*
- 		 * Enable AC97 mode and startup the SSI
- 		 */
- 		write_ssi(CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV,
- 				&ssi->sacnt);
- 		write_ssi(0xff, &ssi->saccdis);
- 		write_ssi(0x300, &ssi->saccen);
- 
- 		/*
- 		 * Enable SSI, Transmit and Receive
- 		 */
- 		write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN |
- 				CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE);
- 
- 		write_ssi(CCSR_SSI_SOR_WAIT(3), &ssi->sor);
- 	}
+ 	if (ssi_private->imx_ac97)
+ 		fsl_ssi_setup_ac97(ssi_private);
  
 +	if (ssi_private->use_dual_fifo) {
 +		write_ssi_mask(&ssi->srcr, 0, CCSR_SSI_SRCR_RFEN1);
 +		write_ssi_mask(&ssi->stcr, 0, CCSR_SSI_STCR_TFEN1);
 +		write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_TCH_EN);
 +	}
 +
  	return 0;
  }