Hi all,

Today's linux-next merge of the sound-asoc tree got a conflict in
sound/soc/fsl/fsl_ssi.c between commit 0da9e55e71bc ("ASoC: fsl_ssi: Add
dual fifo mode support") from the slave-dma tree and commit c1953bfe1329
("ASoC: fsl-ssi: Add imx51-ssi and of_device_id matching") and
0888efd166fa ("ASoC: fsl-ssi: Fix interrupt stats for imx") from the
sound-asoc tree.

I fixed it up (I think - see below) and can carry the fix as necessary
(no action is required).

-- 
Cheers,
Stephen Rothwell                    sfr@canb.auug.org.au

diff --cc sound/soc/fsl/fsl_ssi.c
index 2101fc5c5739,94dedcb0868d..000000000000
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@@ -140,8 -162,9 +162,10 @@@ struct fsl_ssi_private 
  	bool ssi_on_imx;
  	bool imx_ac97;
  	bool use_dma;
 +	bool use_dual_fifo;
  	bool baudclk_locked;
+ 	bool irq_stats;
+ 	bool offline_config;
  	u8 i2s_mode;
  	spinlock_t baudclk_lock;
  	struct clk *baudclk;
@@@ -1170,8 -1332,35 +1348,35 @@@ static int fsl_ssi_probe(struct platfor
  	ssi_private->baudclk_locked = false;
  	spin_lock_init(&ssi_private->baudclk_lock);
  
- 	if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx21-ssi")) {
+ 	/*
+ 	 * imx51 and later SoCs have a slightly different IP that allows the
+ 	 * SSI configuration while the SSI unit is running.
+ 	 *
+ 	 * More important, it is necessary on those SoCs to configure the
+ 	 * sperate TX/RX DMA bits just before starting the stream
+ 	 * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi
+ 	 * sends any DMA requests to the SDMA unit, otherwise it is not defined
+ 	 * how the SDMA unit handles the DMA request.
+ 	 *
+ 	 * SDMA units are present on devices starting at imx35 but the imx35
+ 	 * reference manual states that the DMA bits should not be changed
+ 	 * while the SSI unit is running (SSIEN). So we support the necessary
+ 	 * online configuration of fsl-ssi starting at imx51.
+ 	 */
+ 	switch (hw_type) {
+ 	case FSL_SSI_MCP8610:
+ 	case FSL_SSI_MX21:
+ 	case FSL_SSI_MX35:
+ 		ssi_private->offline_config = true;
+ 		break;
+ 	case FSL_SSI_MX51:
+ 		ssi_private->offline_config = false;
+ 		break;
+ 	}
+ 
+ 	if (hw_type == FSL_SSI_MX21 || hw_type == FSL_SSI_MX51 ||
+ 			hw_type == FSL_SSI_MX35) {
 -		u32 dma_events[2];
 +		u32 dma_events[2], dmas[4];
  		ssi_private->ssi_on_imx = true;
  
  		ssi_private->clk = devm_clk_get(&pdev->dev, NULL);
@@@ -1234,16 -1424,13 +1440,22 @@@
  			dma_events[0], shared ? IMX_DMATYPE_SSI_SP : IMX_DMATYPE_SSI);
  		imx_pcm_dma_params_init_data(&ssi_private->filter_data_rx,
  			dma_events[1], shared ? IMX_DMATYPE_SSI_SP : IMX_DMATYPE_SSI);
 +		if (!of_property_read_u32_array(pdev->dev.of_node, "dmas", dmas, 4)
 +				&& dmas[2] == IMX_DMATYPE_SSI_DUAL) {
 +			ssi_private->use_dual_fifo = true;
 +			/* When using dual fifo mode, we need to keep watermark
 +			 * as even numbers due to dma script limitation.
 +			 */
 +			ssi_private->dma_params_tx.maxburst &= ~0x1;
 +			ssi_private->dma_params_rx.maxburst &= ~0x1;
 +		}
- 	} else if (ssi_private->use_dma) {
+ 	}
+ 
+ 	/*
+ 	 * Enable interrupts only for MCP8610 and MX51. The other MXs have
+ 	 * different writeable interrupt status registers.
+ 	 */
+ 	if (ssi_private->use_dma) {
  		/* The 'name' should not have any slashes in it. */
  		ret = devm_request_irq(&pdev->dev, ssi_private->irq,
  					fsl_ssi_isr, 0, ssi_private->name,