From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Rothwell Subject: linux-next: manual merge of the arm64 tree with Linus' tree Date: Fri, 12 Jan 2018 08:23:59 +1100 Message-ID: <20180112082359.3d8c4c8d@canb.auug.org.au> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-path: Received: from ozlabs.org ([103.22.144.67]:56241 "EHLO ozlabs.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752634AbeAKVYD (ORCPT ); Thu, 11 Jan 2018 16:24:03 -0500 Sender: linux-next-owner@vger.kernel.org List-ID: To: Catalin Marinas Cc: Linux-Next Mailing List , Linux Kernel Mailing List , Dave Martin , Will Deacon Hi Catalin, Today's linux-next merge of the arm64 tree got a conflict in: arch/arm64/kernel/cpufeature.c between commit: 3fab39997a98 ("arm64/sve: Report SVE to userspace via CPUID only if supported") from Linus' tree and commits: 179a56f6f9fb ("arm64: Take into account ID_AA64PFR0_EL1.CSV3") 0f15adbb2861 ("arm64: Add skeleton to harden the branch predictor against aliasing attacks") from the arm64 tree. I fixed it up (see below) and can carry the fix as necessary. This is now fixed as far as linux-next is concerned, but any non trivial conflicts should be mentioned to your upstream maintainer when your tree is submitted for merging. You may also want to consider cooperating with the maintainer of the conflicting tree to minimise any particularly complex conflicts. -- Cheers, Stephen Rothwell diff --cc arch/arm64/kernel/cpufeature.c index a73a5928f09b,da6722db50b0..000000000000 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@@ -145,8 -146,9 +146,10 @@@ static const struct arm64_ftr_bits ftr_ }; static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0), - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0), S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI), S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),