linux-next: manual merge of the mips tree with the mips-fixes tree

linux-next: manual merge of the mips tree with the mips-fixes tree

[Stephen Rothwell]

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Hi all,

Today's linux-next merge of the mips tree got a conflict in:

  arch/mips/sgi-ip27/ip27-init.c

between commit:

  637346748245 ("MIPS: SGI-IP27: fix exception handler replication")

from the mips-fixes tree and commit:

  4bf841ebf17a ("MIPS: SGI-IP27: get rid of compact node ids")

from the mips tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc arch/mips/sgi-ip27/ip27-init.c
index 79a52c472782,8fd3505e2b9c..000000000000
--- a/arch/mips/sgi-ip27/ip27-init.c
+++ b/arch/mips/sgi-ip27/ip27-init.c
@@@ -67,16 -62,25 +62,16 @@@ static void per_hub_init(nasid_t nasid
  	REMOTE_HUB_S(nasid, IIO_ICTP, 0x800);
  	REMOTE_HUB_S(nasid, IIO_ICTO, 0xff);
  
- 	hub_rtc_init(cnode);
+ 	hub_rtc_init(nasid);
  
 -#ifdef CONFIG_REPLICATE_EXHANDLERS
 -	/*
 -	 * If this is not a headless node initialization,
 -	 * copy over the caliased exception handlers.
 -	 */
 -	if (get_nasid() == nasid) {
 -		extern char except_vec2_generic, except_vec3_generic;
 -		extern void build_tlb_refill_handler(void);
 -
 -		memcpy((void *)(CKSEG0 + 0x100), &except_vec2_generic, 0x80);
 -		memcpy((void *)(CKSEG0 + 0x180), &except_vec3_generic, 0x80);
 -		build_tlb_refill_handler();
 -		memcpy((void *)(CKSEG0 + 0x100), (void *) CKSEG0, 0x80);
 -		memcpy((void *)(CKSEG0 + 0x180), &except_vec3_generic, 0x100);
 +	if (nasid) {
 +		/* copy exception handlers from first node to current node */
 +		memcpy((void *)NODE_OFFSET_TO_K0(nasid, 0),
 +		       (void *)CKSEG0, 0x200);
  		__flush_cache_all();
 +		/* switch to node local exception handlers */
 +		REMOTE_HUB_S(nasid, PI_CALIAS_SIZE, PI_CALIAS_SIZE_8K);
  	}
 -#endif
  }
  
  void per_cpu_init(void)

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linux-next: manual merge of the mips tree with the mips-fixes tree

[Stephen Rothwell]

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Hi all,

Today's linux-next merge of the mips tree got a conflict in:

  arch/mips/include/asm/pgtable.h

between commit:

  e02e07e3127d ("MIPS: Loongson: Introduce and use loongson_llsc_mb()")

from the mips-fixes tree and commit:

  c7e2d71dda7a ("MIPS: Fix set_pte() for Netlogic XLR using cmpxchg64()")

from the mips tree.

I fixed it up (I just used the mips tree version) and can carry the fix
as necessary. This is now fixed as far as linux-next is concerned, but
any non trivial conflicts should be mentioned to your upstream maintainer
when your tree is submitted for merging.  You may also want to consider
cooperating with the maintainer of the conflicting tree to minimise any
particularly complex conflicts.



-- 
Cheers,
Stephen Rothwell

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Re: linux-next: manual merge of the mips tree with the mips-fixes tree

[Stephen Rothwell]

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Hi Paul,

On Tue, 5 Feb 2019 23:35:31 +0000 Paul Burton <paul.burton@mips.com> wrote:
>
> cmpxchg() doesn't need the added loongson_llsc_mb() barrier that
> set_pte() has in mips-fixes because for the affected Loongson 3
> configurations the smp_mb__before_llsc() that cmpxchg() already contains
> is equivalent (both will emit a "sync 0" instruction).

OK, good to know, thanks.

-- 
Cheers,
Stephen Rothwell

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Re: linux-next: manual merge of the mips tree with the mips-fixes tree

[Paul Burton]

Hi Stephen,

On Wed, Feb 06, 2019 at 09:17:36AM +1100, Stephen Rothwell wrote:
> Hi all,
> 
> Today's linux-next merge of the mips tree got conflicts in:
> 
>   arch/mips/include/asm/barrier.h
>   arch/mips/include/asm/pgtable.h
> 
> between commit:
> 
>   e02e07e3127d ("MIPS: Loongson: Introduce and use loongson_llsc_mb()")
> 
> from the mips-fixes tree and commits:
> 
>   535113896e80 ("MIPS: Add GINVT instruction helpers")
>   82f4f66ddf11 ("MIPS: Remove open-coded cmpxchg() in set_pte()")
> 
> from the mips tree.
> 
> I fixed it up (see below and for the latter file, I used the mips tree
> version but wondered if cmpxchg() needs the fixups from the mips-fixes
> tree commit)

Thanks - that looks good.

cmpxchg() doesn't need the added loongson_llsc_mb() barrier that
set_pte() has in mips-fixes because for the affected Loongson 3
configurations the smp_mb__before_llsc() that cmpxchg() already contains
is equivalent (both will emit a "sync 0" instruction).

Thanks,
    Paul

linux-next: manual merge of the mips tree with the mips-fixes tree

[Stephen Rothwell]

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Hi all,

Today's linux-next merge of the mips tree got conflicts in:

  arch/mips/include/asm/barrier.h
  arch/mips/include/asm/pgtable.h

between commit:

  e02e07e3127d ("MIPS: Loongson: Introduce and use loongson_llsc_mb()")

from the mips-fixes tree and commits:

  535113896e80 ("MIPS: Add GINVT instruction helpers")
  82f4f66ddf11 ("MIPS: Remove open-coded cmpxchg() in set_pte()")

from the mips tree.

I fixed it up (see below and for the latter file, I used the mips tree
version but wondered if cmpxchg() needs the fixups from the mips-fixes
tree commit) and can carry the fix as necessary. This is now fixed as
far as linux-next is concerned, but any non trivial conflicts should be
mentioned to your upstream maintainer when your tree is submitted for
merging. You may also want to consider cooperating with the maintainer
of the conflicting tree to minimise any particularly complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc arch/mips/include/asm/barrier.h
index b7f6ac5e513c,b48ee2caf78d..000000000000
--- a/arch/mips/include/asm/barrier.h
+++ b/arch/mips/include/asm/barrier.h
@@@ -222,42 -236,11 +236,47 @@@
  #define __smp_mb__before_atomic()	__smp_mb__before_llsc()
  #define __smp_mb__after_atomic()	smp_llsc_mb()
  
 +/*
 + * Some Loongson 3 CPUs have a bug wherein execution of a memory access (load,
 + * store or pref) in between an ll & sc can cause the sc instruction to
 + * erroneously succeed, breaking atomicity. Whilst it's unusual to write code
 + * containing such sequences, this bug bites harder than we might otherwise
 + * expect due to reordering & speculation:
 + *
 + * 1) A memory access appearing prior to the ll in program order may actually
 + *    be executed after the ll - this is the reordering case.
 + *
 + *    In order to avoid this we need to place a memory barrier (ie. a sync
 + *    instruction) prior to every ll instruction, in between it & any earlier
 + *    memory access instructions. Many of these cases are already covered by
 + *    smp_mb__before_llsc() but for the remaining cases, typically ones in
 + *    which multiple CPUs may operate on a memory location but ordering is not
 + *    usually guaranteed, we use loongson_llsc_mb() below.
 + *
 + *    This reordering case is fixed by 3A R2 CPUs, ie. 3A2000 models and later.
 + *
 + * 2) If a conditional branch exists between an ll & sc with a target outside
 + *    of the ll-sc loop, for example an exit upon value mismatch in cmpxchg()
 + *    or similar, then misprediction of the branch may allow speculative
 + *    execution of memory accesses from outside of the ll-sc loop.
 + *
 + *    In order to avoid this we need a memory barrier (ie. a sync instruction)
 + *    at each affected branch target, for which we also use loongson_llsc_mb()
 + *    defined below.
 + *
 + *    This case affects all current Loongson 3 CPUs.
 + */
 +#ifdef CONFIG_CPU_LOONGSON3_WORKAROUNDS /* Loongson-3's LLSC workaround */
 +#define loongson_llsc_mb()	__asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
 +#else
 +#define loongson_llsc_mb()	do { } while (0)
 +#endif
 +
+ static inline void sync_ginv(void)
+ {
+ 	asm volatile("sync\t%0" :: "i"(STYPE_GINV));
+ }
+ 
  #include <asm-generic/barrier.h>
  
  #endif /* __ASM_BARRIER_H */
diff --cc arch/mips/include/asm/pgtable.h
index 910851c62db3,6c13c1d44045..000000000000
--- a/arch/mips/include/asm/pgtable.h
+++ b/arch/mips/include/asm/pgtable.h

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linux-next: manual merge of the mips tree with the mips-fixes tree

[Stephen Rothwell]

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Hi all,

Today's linux-next merge of the mips tree got a conflict in:

  arch/mips/kernel/process.c

between commit:

  b63e132b6433 ("MIPS: Use async IPIs for arch_trigger_cpumask_backtrace()")

from the mips-fixes tree and commit:

  8c8d953c2800 ("MIPS: Schedule on CPUs we need to lose FPU for a mode switch")

from the mips tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc arch/mips/kernel/process.c
index 9670e70139fd,fe6001d748cf..000000000000
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@@ -29,7 -29,7 +29,8 @@@
  #include <linux/kallsyms.h>
  #include <linux/random.h>
  #include <linux/prctl.h>
 +#include <linux/nmi.h>
+ #include <linux/cpu.h>
  
  #include <asm/asm.h>
  #include <asm/bootinfo.h>

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