* Re: [Intel-gfx] [PATCH v3 03/13] drm/dp: add LTTPR DP 2.0 DPCD addresses
[not found] ` <def17e2329722f22c35807be26b35590ccb93bfd.1631191763.git.jani.nikula@intel.com>
@ 2021-09-21 22:58 ` Nathan Chancellor
2021-09-22 0:45 ` Stephen Rothwell
2021-09-22 11:10 ` Jani Nikula
0 siblings, 2 replies; 5+ messages in thread
From: Nathan Chancellor @ 2021-09-21 22:58 UTC (permalink / raw)
To: Jani Nikula
Cc: intel-gfx, dri-devel, ville.syrjala, manasi.d.navare,
Alex Deucher, Christian König, Pan, Xinhui, amd-gfx,
Stephen Rothwell, linux-next
On Thu, Sep 09, 2021 at 03:51:55PM +0300, Jani Nikula wrote:
> DP 2.0 brings some new DPCD addresses for PHY repeaters.
>
> Cc: dri-devel@lists.freedesktop.org
> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> include/drm/drm_dp_helper.h | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 1d5b3dbb6e56..f3a61341011d 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -1319,6 +1319,10 @@ struct drm_panel;
> #define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */
> #define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */
> #define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */
> +#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
> +# define DP_PHY_REPEATER_128B132B_SUPPORTED (1 << 0)
> +/* See DP_128B132B_SUPPORTED_LINK_RATES for values */
> +#define DP_PHY_REPEATER_128B132B_RATES 0xf0007 /* 2.0 */
>
> enum drm_dp_phy {
> DP_PHY_DPRX,
> --
> 2.30.2
>
>
This patch causes a build failure in -next when combined with the AMD
tree:
In file included from drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c:33:
In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu.h:70:
In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu_mode.h:36:
./include/drm/drm_dp_helper.h:1322:9: error: 'DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER' macro redefined [-Werror,-Wmacro-redefined]
#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
^
./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dp_types.h:881:9: note: previous definition is here
#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
^
1 error generated.
Perhaps something like this should be applied during the merge of the
second tree or maybe this patch should be in a branch that could be
shared between the Intel and AMD trees so that this diff could be
applied to the AMD tree directly? Not sure what the standard procedure
for this is.
Cheers,
Nathan
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 234dfbea926a..279863b5c650 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -4590,7 +4590,7 @@ bool dp_retrieve_lttpr_cap(struct dc_link *link)
DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.raw =
- lttpr_dpcd_data[DP_PHY_REPEATER_128b_132b_RATES -
+ lttpr_dpcd_data[DP_PHY_REPEATER_128B132B_RATES -
DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
index a5e798b5da79..8caf9af5ffa2 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
@@ -878,8 +878,6 @@ struct psr_caps {
# define DP_DSC_DECODER_COUNT_MASK (0b111 << 5)
# define DP_DSC_DECODER_COUNT_SHIFT 5
#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
-#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
-#define DP_PHY_REPEATER_128b_132b_RATES 0xF0007
#define DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xF0022
#define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3)
/* TODO - Use DRM header to replace above once available */
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [Intel-gfx] [PATCH v3 03/13] drm/dp: add LTTPR DP 2.0 DPCD addresses
2021-09-21 22:58 ` [Intel-gfx] [PATCH v3 03/13] drm/dp: add LTTPR DP 2.0 DPCD addresses Nathan Chancellor
@ 2021-09-22 0:45 ` Stephen Rothwell
2021-09-22 11:10 ` Jani Nikula
1 sibling, 0 replies; 5+ messages in thread
From: Stephen Rothwell @ 2021-09-22 0:45 UTC (permalink / raw)
To: Nathan Chancellor
Cc: Jani Nikula, intel-gfx, dri-devel, ville.syrjala,
manasi.d.navare, Alex Deucher, Christian König, Pan, Xinhui,
amd-gfx, linux-next
[-- Attachment #1: Type: text/plain, Size: 3964 bytes --]
Hi Nathan,
On Tue, 21 Sep 2021 15:58:23 -0700 Nathan Chancellor <nathan@kernel.org> wrote:
>
> On Thu, Sep 09, 2021 at 03:51:55PM +0300, Jani Nikula wrote:
> > DP 2.0 brings some new DPCD addresses for PHY repeaters.
> >
> > Cc: dri-devel@lists.freedesktop.org
> > Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
> > Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> > ---
> > include/drm/drm_dp_helper.h | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> > index 1d5b3dbb6e56..f3a61341011d 100644
> > --- a/include/drm/drm_dp_helper.h
> > +++ b/include/drm/drm_dp_helper.h
> > @@ -1319,6 +1319,10 @@ struct drm_panel;
> > #define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */
> > #define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */
> > #define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */
> > +#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
> > +# define DP_PHY_REPEATER_128B132B_SUPPORTED (1 << 0)
> > +/* See DP_128B132B_SUPPORTED_LINK_RATES for values */
> > +#define DP_PHY_REPEATER_128B132B_RATES 0xf0007 /* 2.0 */
> >
> > enum drm_dp_phy {
> > DP_PHY_DPRX,
> > --
> > 2.30.2
> >
> >
>
> This patch causes a build failure in -next when combined with the AMD
> tree:
>
> In file included from drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c:33:
> In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu.h:70:
> In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu_mode.h:36:
> ./include/drm/drm_dp_helper.h:1322:9: error: 'DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER' macro redefined [-Werror,-Wmacro-redefined]
> #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
> ^
> ./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dp_types.h:881:9: note: previous definition is here
> #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
> ^
> 1 error generated.
>
> Perhaps something like this should be applied during the merge of the
> second tree or maybe this patch should be in a branch that could be
> shared between the Intel and AMD trees so that this diff could be
> applied to the AMD tree directly? Not sure what the standard procedure
> for this is.
>
> Cheers,
> Nathan
>
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> index 234dfbea926a..279863b5c650 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> @@ -4590,7 +4590,7 @@ bool dp_retrieve_lttpr_cap(struct dc_link *link)
> DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
>
> link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.raw =
> - lttpr_dpcd_data[DP_PHY_REPEATER_128b_132b_RATES -
> + lttpr_dpcd_data[DP_PHY_REPEATER_128B132B_RATES -
> DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
> #endif
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
> index a5e798b5da79..8caf9af5ffa2 100644
> --- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
> +++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
> @@ -878,8 +878,6 @@ struct psr_caps {
> # define DP_DSC_DECODER_COUNT_MASK (0b111 << 5)
> # define DP_DSC_DECODER_COUNT_SHIFT 5
> #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
> -#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
> -#define DP_PHY_REPEATER_128b_132b_RATES 0xF0007
> #define DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xF0022
> #define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3)
> /* TODO - Use DRM header to replace above once available */
Thanks for the heads up. I have applied the above as a merge fix patch
until something else happens.
--
Cheers,
Stephen Rothwell
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Intel-gfx] [PATCH v3 03/13] drm/dp: add LTTPR DP 2.0 DPCD addresses
2021-09-21 22:58 ` [Intel-gfx] [PATCH v3 03/13] drm/dp: add LTTPR DP 2.0 DPCD addresses Nathan Chancellor
2021-09-22 0:45 ` Stephen Rothwell
@ 2021-09-22 11:10 ` Jani Nikula
2021-09-22 13:49 ` Alex Deucher
1 sibling, 1 reply; 5+ messages in thread
From: Jani Nikula @ 2021-09-22 11:10 UTC (permalink / raw)
To: Nathan Chancellor
Cc: intel-gfx, dri-devel, ville.syrjala, manasi.d.navare,
Alex Deucher, Christian König, Pan, Xinhui, amd-gfx,
Stephen Rothwell, linux-next, Dave Airlie, Daniel Vetter
On Tue, 21 Sep 2021, Nathan Chancellor <nathan@kernel.org> wrote:
> On Thu, Sep 09, 2021 at 03:51:55PM +0300, Jani Nikula wrote:
>> DP 2.0 brings some new DPCD addresses for PHY repeaters.
>>
>> Cc: dri-devel@lists.freedesktop.org
>> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> include/drm/drm_dp_helper.h | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
>> index 1d5b3dbb6e56..f3a61341011d 100644
>> --- a/include/drm/drm_dp_helper.h
>> +++ b/include/drm/drm_dp_helper.h
>> @@ -1319,6 +1319,10 @@ struct drm_panel;
>> #define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */
>> #define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */
>> #define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */
>> +#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
>> +# define DP_PHY_REPEATER_128B132B_SUPPORTED (1 << 0)
>> +/* See DP_128B132B_SUPPORTED_LINK_RATES for values */
>> +#define DP_PHY_REPEATER_128B132B_RATES 0xf0007 /* 2.0 */
>>
>> enum drm_dp_phy {
>> DP_PHY_DPRX,
>> --
>> 2.30.2
>>
>>
>
> This patch causes a build failure in -next when combined with the AMD
> tree:
>
> In file included from drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c:33:
> In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu.h:70:
> In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu_mode.h:36:
> ./include/drm/drm_dp_helper.h:1322:9: error: 'DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER' macro redefined [-Werror,-Wmacro-redefined]
> #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
> ^
> ./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dp_types.h:881:9: note: previous definition is here
> #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
> ^
> 1 error generated.
>
> Perhaps something like this should be applied during the merge of the
> second tree or maybe this patch should be in a branch that could be
> shared between the Intel and AMD trees so that this diff could be
> applied to the AMD tree directly? Not sure what the standard procedure
> for this is.
What's in the drm-intel-next branch is changing DRM DP helpers in
include/drm/drm_dp_helper.h with acks from a drm-misc maintainer. That's
where this stuff is supposed to land, not in a driver specific file, and
especially not if added with just a DP_ prefix.
BR,
Jani.
>
> Cheers,
> Nathan
>
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> index 234dfbea926a..279863b5c650 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> @@ -4590,7 +4590,7 @@ bool dp_retrieve_lttpr_cap(struct dc_link *link)
> DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
>
> link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.raw =
> - lttpr_dpcd_data[DP_PHY_REPEATER_128b_132b_RATES -
> + lttpr_dpcd_data[DP_PHY_REPEATER_128B132B_RATES -
> DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
> #endif
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
> index a5e798b5da79..8caf9af5ffa2 100644
> --- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
> +++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
> @@ -878,8 +878,6 @@ struct psr_caps {
> # define DP_DSC_DECODER_COUNT_MASK (0b111 << 5)
> # define DP_DSC_DECODER_COUNT_SHIFT 5
> #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
> -#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
> -#define DP_PHY_REPEATER_128b_132b_RATES 0xF0007
> #define DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xF0022
> #define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3)
> /* TODO - Use DRM header to replace above once available */
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Intel-gfx] [PATCH v3 03/13] drm/dp: add LTTPR DP 2.0 DPCD addresses
2021-09-22 11:10 ` Jani Nikula
@ 2021-09-22 13:49 ` Alex Deucher
2021-09-22 17:32 ` [PATCH] drm/amd/display: Only define DP 2.0 symbols if not already defined Harry Wentland
0 siblings, 1 reply; 5+ messages in thread
From: Alex Deucher @ 2021-09-22 13:49 UTC (permalink / raw)
To: Jani Nikula, Harry Wentland, Leo (Sunpeng) Li
Cc: Nathan Chancellor, Intel Graphics Development,
Maling list - DRI developers, Ville Syrjälä,
Manasi Navare, Alex Deucher, Christian König, Pan, Xinhui,
amd-gfx list, Stephen Rothwell, Linux-Next Mailing List,
Dave Airlie, Daniel Vetter
+ Harry, Leo
Can you guys get someone to clean this up?
Alex
On Wed, Sep 22, 2021 at 7:10 AM Jani Nikula <jani.nikula@intel.com> wrote:
>
> On Tue, 21 Sep 2021, Nathan Chancellor <nathan@kernel.org> wrote:
> > On Thu, Sep 09, 2021 at 03:51:55PM +0300, Jani Nikula wrote:
> >> DP 2.0 brings some new DPCD addresses for PHY repeaters.
> >>
> >> Cc: dri-devel@lists.freedesktop.org
> >> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >> ---
> >> include/drm/drm_dp_helper.h | 4 ++++
> >> 1 file changed, 4 insertions(+)
> >>
> >> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> >> index 1d5b3dbb6e56..f3a61341011d 100644
> >> --- a/include/drm/drm_dp_helper.h
> >> +++ b/include/drm/drm_dp_helper.h
> >> @@ -1319,6 +1319,10 @@ struct drm_panel;
> >> #define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */
> >> #define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */
> >> #define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */
> >> +#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
> >> +# define DP_PHY_REPEATER_128B132B_SUPPORTED (1 << 0)
> >> +/* See DP_128B132B_SUPPORTED_LINK_RATES for values */
> >> +#define DP_PHY_REPEATER_128B132B_RATES 0xf0007 /* 2.0 */
> >>
> >> enum drm_dp_phy {
> >> DP_PHY_DPRX,
> >> --
> >> 2.30.2
> >>
> >>
> >
> > This patch causes a build failure in -next when combined with the AMD
> > tree:
> >
> > In file included from drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c:33:
> > In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu.h:70:
> > In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu_mode.h:36:
> > ./include/drm/drm_dp_helper.h:1322:9: error: 'DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER' macro redefined [-Werror,-Wmacro-redefined]
> > #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
> > ^
> > ./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dp_types.h:881:9: note: previous definition is here
> > #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
> > ^
> > 1 error generated.
> >
> > Perhaps something like this should be applied during the merge of the
> > second tree or maybe this patch should be in a branch that could be
> > shared between the Intel and AMD trees so that this diff could be
> > applied to the AMD tree directly? Not sure what the standard procedure
> > for this is.
>
> What's in the drm-intel-next branch is changing DRM DP helpers in
> include/drm/drm_dp_helper.h with acks from a drm-misc maintainer. That's
> where this stuff is supposed to land, not in a driver specific file, and
> especially not if added with just a DP_ prefix.
>
>
> BR,
> Jani.
>
> >
> > Cheers,
> > Nathan
> >
> > diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> > index 234dfbea926a..279863b5c650 100644
> > --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> > +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> > @@ -4590,7 +4590,7 @@ bool dp_retrieve_lttpr_cap(struct dc_link *link)
> > DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
> >
> > link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.raw =
> > - lttpr_dpcd_data[DP_PHY_REPEATER_128b_132b_RATES -
> > + lttpr_dpcd_data[DP_PHY_REPEATER_128B132B_RATES -
> > DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
> > #endif
> >
> > diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
> > index a5e798b5da79..8caf9af5ffa2 100644
> > --- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
> > +++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
> > @@ -878,8 +878,6 @@ struct psr_caps {
> > # define DP_DSC_DECODER_COUNT_MASK (0b111 << 5)
> > # define DP_DSC_DECODER_COUNT_SHIFT 5
> > #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
> > -#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
> > -#define DP_PHY_REPEATER_128b_132b_RATES 0xF0007
> > #define DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xF0022
> > #define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3)
> > /* TODO - Use DRM header to replace above once available */
>
> --
> Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH] drm/amd/display: Only define DP 2.0 symbols if not already defined
2021-09-22 13:49 ` Alex Deucher
@ 2021-09-22 17:32 ` Harry Wentland
0 siblings, 0 replies; 5+ messages in thread
From: Harry Wentland @ 2021-09-22 17:32 UTC (permalink / raw)
To: jani.nikula, Sunpeng.Li, nathan, alexander.deucher
Cc: intel-gfx, dri-devel, ville.syrjala, manasi.d.navare,
christian.koenig, Xinhui.Pan, amd-gfx, sfr, linux-next, airlied,
daniel.vetter, Harry Wentland
[Why]
For some reason we're defining DP 2.0 definitions inside our
driver. Now that patches to introduce relevant definitions
are slated to be merged into drm-next this is causing conflicts.
In file included from drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c:33:
In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu.h:70:
In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu_mode.h:36:
./include/drm/drm_dp_helper.h:1322:9: error: 'DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER' macro redefined [-Werror,-Wmacro-redefined]
^
./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dp_types.h:881:9: note: previous definition is here
^
1 error generated.
[How]
Guard all display driver defines with #ifndef for now. Once we pull
in the new definitions into amd-staging-drm-next we will follow
up and drop definitions from our driver and provide follow-up
header updates for any addition DP 2.0 definitions required
by our driver.
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 53 ++++++++++++++++++--
1 file changed, 48 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
index a5e798b5da79..74b8de616dcd 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
@@ -860,28 +860,71 @@ struct psr_caps {
};
#if defined(CONFIG_DRM_AMD_DC_DCN)
+#ifndef DP_MAIN_LINK_CHANNEL_CODING_CAP
#define DP_MAIN_LINK_CHANNEL_CODING_CAP 0x006
+#endif
+#ifndef DP_SINK_VIDEO_FALLBACK_FORMATS
#define DP_SINK_VIDEO_FALLBACK_FORMATS 0x020
+#endif
+#ifndef DP_FEC_CAPABILITY_1
#define DP_FEC_CAPABILITY_1 0x091
+#endif
+#ifndef DP_DFP_CAPABILITY_EXTENSION_SUPPORT
#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+#endif
+#ifndef DP_DSC_CONFIGURATION
#define DP_DSC_CONFIGURATION 0x161
+#endif
+#ifndef DP_PHY_SQUARE_PATTERN
#define DP_PHY_SQUARE_PATTERN 0x249
+#endif
+#ifndef DP_128b_132b_SUPPORTED_LINK_RATES
#define DP_128b_132b_SUPPORTED_LINK_RATES 0x2215
+#endif
+#ifndef DP_128b_132b_TRAINING_AUX_RD_INTERVAL
#define DP_128b_132b_TRAINING_AUX_RD_INTERVAL 0x2216
+#endif
+#ifndef DP_TEST_264BIT_CUSTOM_PATTERN_7_0
#define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0X2230
+#endif
+#ifndef DP_TEST_264BIT_CUSTOM_PATTERN_263_256
#define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0X2250
+#endif
+#ifndef DP_DSC_SUPPORT_AND_DECODER_COUNT
#define DP_DSC_SUPPORT_AND_DECODER_COUNT 0x2260
+#endif
+#ifndef DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0
#define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270
-# define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0)
-# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1)
-# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1
-# define DP_DSC_DECODER_COUNT_MASK (0b111 << 5)
-# define DP_DSC_DECODER_COUNT_SHIFT 5
+#endif
+#ifndef DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK
+#define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0)
+#endif
+#ifndef DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK
+#define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1)
+#endif
+#ifndef DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT
+#define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1
+#endif
+#ifndef DP_DSC_DECODER_COUNT_MASK
+#define DP_DSC_DECODER_COUNT_MASK (0b111 << 5)
+#endif
+#ifndef DP_DSC_DECODER_COUNT_SHIFT
+#define DP_DSC_DECODER_COUNT_SHIFT 5
+#endif
+#ifndef DP_MAIN_LINK_CHANNEL_CODING_SET
#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
+#endif
+#ifndef DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER
#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006
+#endif
+#ifndef DP_PHY_REPEATER_128b_132b_RATES
#define DP_PHY_REPEATER_128b_132b_RATES 0xF0007
+#ifndef DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1
#define DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xF0022
+#endif
+#ifndef DP_INTRA_HOP_AUX_REPLY_INDICATION
#define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3)
+#endif
/* TODO - Use DRM header to replace above once available */
union dp_main_line_channel_coding_cap {
--
2.33.0
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[not found] <cover.1631191763.git.jani.nikula@intel.com>
[not found] ` <def17e2329722f22c35807be26b35590ccb93bfd.1631191763.git.jani.nikula@intel.com>
2021-09-21 22:58 ` [Intel-gfx] [PATCH v3 03/13] drm/dp: add LTTPR DP 2.0 DPCD addresses Nathan Chancellor
2021-09-22 0:45 ` Stephen Rothwell
2021-09-22 11:10 ` Jani Nikula
2021-09-22 13:49 ` Alex Deucher
2021-09-22 17:32 ` [PATCH] drm/amd/display: Only define DP 2.0 symbols if not already defined Harry Wentland
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