Re: [PATCH] usb: dwc3: dwc3-octeon: Verify clock divider

From: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
To: Ladislav Michl <oss-lists@triops.cz>
Cc: Naresh Kamboju <naresh.kamboju@linaro.org>,
	Linux-Next Mailing List <linux-next@vger.kernel.org>,
	"linux-usb@vger.kernel.org" <linux-usb@vger.kernel.org>,
	"linux-mips@vger.kernel.org" <linux-mips@vger.kernel.org>,
	"lkft-triage@lists.linaro.org" <lkft-triage@lists.linaro.org>,
	Thinh Nguyen <Thinh.Nguyen@synopsys.com>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Arnd Bergmann <arnd@arndb.de>,
	Anders Roxell <anders.roxell@linaro.org>,
	Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Subject: Re: [PATCH] usb: dwc3: dwc3-octeon: Verify clock divider
Date: Tue, 8 Aug 2023 23:41:08 +0000	[thread overview]
Message-ID: <20230808234059.bosmyyltsp42mt43@synopsys.com> (raw)
In-Reply-To: <ZNIM7tlBNdHFzXZG@lenoch>

On Tue, Aug 08, 2023, Ladislav Michl wrote:
> From: Ladislav Michl <ladis@linux-mips.org>
> 
> Although valid USB clock divider will be calculated for all valid
> Octeon core frequencies, make code formally correct limiting
> divider not to be greater that 7 so it fits into H_CLKDIV_SEL
> field.
> 
> Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
> Reported-by: Linux Kernel Functional Testing <lkft@linaro.org>
> Closes: https://urldefense.com/v3/__https://qa-reports.linaro.org/lkft/linux-next-master/build/next-20230808/testrun/18882876/suite/build/test/gcc-8-cavium_octeon_defconfig/log__;!!A4F2R9G_pg!aMHLJEE_aLERK48OJY2mcfvhm6OZMeAB8IUZUc16me_jFuy-VVsgIXn-cP5K99sPe_eEZToGWIBXQJB1CxZFVgMcJA$ 
> ---
>  Greg, if you want to resent whole serie, just drop me a note.
>  Otherwise, this patch is meant to be applied on to of it.
>  Thank you.
> 
>  drivers/usb/dwc3/dwc3-octeon.c | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/usb/dwc3/dwc3-octeon.c b/drivers/usb/dwc3/dwc3-octeon.c
> index 6f47262a117a..73bdcebf465c 100644
> --- a/drivers/usb/dwc3/dwc3-octeon.c
> +++ b/drivers/usb/dwc3/dwc3-octeon.c
> @@ -251,11 +251,11 @@ static int dwc3_octeon_get_divider(void)
>  	while (div < ARRAY_SIZE(clk_div)) {
>  		uint64_t rate = octeon_get_io_clock_rate() / clk_div[div];
>  		if (rate <= 300000000 && rate >= 150000000)
> -			break;
> +			return div;
>  		div++;
>  	}
>  
> -	return div;
> +	return -EINVAL;
>  }
>  
>  static int dwc3_octeon_setup(struct dwc3_octeon *octeon,
> @@ -289,6 +289,10 @@ static int dwc3_octeon_setup(struct dwc3_octeon *octeon,
>  
>  	/* Step 4b: Select controller clock frequency. */
>  	div = dwc3_octeon_get_divider();
> +	if (div < 0) {
> +		dev_err(dev, "clock divider invalid\n");
> +		return div;
> +	}
>  	val = dwc3_octeon_readq(uctl_ctl_reg);
>  	val &= ~USBDRD_UCTL_CTL_H_CLKDIV_SEL;
>  	val |= FIELD_PREP(USBDRD_UCTL_CTL_H_CLKDIV_SEL, div);
> -- 
> 2.39.2
> 

Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>

Thanks,
Thinh