Hi all,

Today's linux-next merge of the iommufd tree got a conflict in:

  drivers/iommu/intel/pasid.c

between commit:

  c61c255e114c ("iommu/vt-d: Remove unused function")

from the iommu tree and commit:

  3c576c995219 ("iommu/intel: Access/Dirty bit support for SL domains")

from the iommufd tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc drivers/iommu/intel/pasid.c
index 06ddb3c927f5,b9264b9174e8..000000000000
--- a/drivers/iommu/intel/pasid.c
+++ b/drivers/iommu/intel/pasid.c
@@@ -335,6 -340,45 +340,36 @@@ static inline void pasid_set_fault_enab
  	pasid_set_bits(&pe->val[0], 1 << 1, 0);
  }
  
+ /*
+  * Enable second level A/D bits by setting the SLADE (Second Level
+  * Access Dirty Enable) field (Bit 9) of a scalable mode PASID
+  * entry.
+  */
+ static inline void pasid_set_ssade(struct pasid_entry *pe)
+ {
+ 	pasid_set_bits(&pe->val[0], 1 << 9, 1 << 9);
+ }
+ 
+ /*
+  * Disable second level A/D bits by clearing the SLADE (Second Level
+  * Access Dirty Enable) field (Bit 9) of a scalable mode PASID
+  * entry.
+  */
+ static inline void pasid_clear_ssade(struct pasid_entry *pe)
+ {
+ 	pasid_set_bits(&pe->val[0], 1 << 9, 0);
+ }
+ 
+ /*
+  * Checks if second level A/D bits specifically the SLADE (Second Level
+  * Access Dirty Enable) field (Bit 9) of a scalable mode PASID
+  * entry is set.
+  */
+ static inline bool pasid_get_ssade(struct pasid_entry *pe)
+ {
+ 	return pasid_get_bits(&pe->val[0]) & (1 << 9);
+ }
+ 
 -/*
 - * Setup the WPE(Write Protect Enable) field (Bit 132) of a
 - * scalable mode PASID entry.
 - */
 -static inline void pasid_set_wpe(struct pasid_entry *pe)
 -{
 -	pasid_set_bits(&pe->val[2], 1 << 4, 1 << 4);
 -}
 -
  /*
   * Setup the P(Present) field (Bit 0) of a scalable mode PASID
   * entry.