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From: Jani Nikula <jani.nikula@intel.com>
To: "mpe@ellerman.id.au" <michael@ozlabs.org>,
	Dave Airlie <airlied@linux.ie>,
	Daniel Vetter <daniel.vetter@ffwll.ch>,
	intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: linux-next@vger.kernel.org, linux-kernel@vger.kernel.org,
	"Nick Hoath" <nicholas.hoath@intel.com>,
	"Ville Syrjälä" <ville.syrjala@linux.intel.com>,
	"Damien Lespiau" <damien.lespiau@intel.com>
Subject: Re: linux-next: manual merge of the drm tree with the drm-intel-fixes tree
Date: Fri, 05 Jun 2015 11:03:20 +0300
Message-ID: <87sia6a8fr.fsf@intel.com> (raw)
In-Reply-To: <20150605054634.E4FA3140218@ozlabs.org>

On Fri, 05 Jun 2015, "mpe@ellerman.id.au" <michael@ozlabs.org> wrote:
> Hi Dave,
>
> Today's linux-next merge of the drm tree got a conflict in
> drivers/gpu/drm/i915/intel_ringbuffer.c between commit 4f47c99a9be7 ("drm/i915:
> Move WaBarrierPerformanceFixDisable:skl to skl code from chv code") from the
> drm-intel-fixes tree and commit b62adbd1ea1f ("drm/i915/bxt: Move
> WaForceEnableNonCoherent to Skylake only") from the drm tree.
>
> I fixed it up (see below) and can carry the fix as necessary (no action
> is required).

Our tree seems to have the if blocks the other way round. I don't think
it matters, but Ville, Damien, chime in if you think it does.

BR
Jani.

>
> cheers
>
> diff --cc drivers/gpu/drm/i915/intel_ringbuffer.c
> index 005b5e04de4d,d934f857394d..000000000000
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@@ -1017,13 -1030,17 +1023,24 @@@ static int skl_init_workarounds(struct 
>   		WA_SET_BIT_MASKED(HIZ_CHICKEN,
>   				  BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
>   
>  +	if (INTEL_REVID(dev) == SKL_REVID_C0 ||
>  +	    INTEL_REVID(dev) == SKL_REVID_D0)
>  +		/* WaBarrierPerformanceFixDisable:skl */
>  +		WA_SET_BIT_MASKED(HDC_CHICKEN0,
>  +				  HDC_FENCE_DEST_SLM_DISABLE |
>  +				  HDC_BARRIER_PERFORMANCE_DISABLE);
>  +
> + 	if (INTEL_REVID(dev) <= SKL_REVID_D0) {
> + 		/*
> + 		 *Use Force Non-Coherent whenever executing a 3D context. This
> + 		 * is a workaround for a possible hang in the unlikely event
> + 		 * a TLB invalidation occurs during a PSD flush.
> + 		 */
> + 		/* WaForceEnableNonCoherent:skl */
> + 		WA_SET_BIT_MASKED(HDC_CHICKEN0,
> + 				  HDC_FORCE_NON_COHERENT);
> + 	}
> + 
>   	return skl_tune_iz_hashing(ring);
>   }
>   

-- 
Jani Nikula, Intel Open Source Technology Center

  reply index

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-06-05  5:46 michael
2015-06-05  8:03 ` Jani Nikula [this message]
2015-06-09  1:58   ` Stephen Rothwell
  -- strict thread matches above, loose matches on Subject: below --
2019-10-31  0:33 Stephen Rothwell
2019-11-08  0:42 ` Stephen Rothwell
2018-01-05  1:00 Stephen Rothwell
2017-07-21  1:26 Stephen Rothwell
2017-06-14  0:56 Stephen Rothwell
2017-06-14  0:50 Stephen Rothwell
2017-06-09  2:26 Stephen Rothwell
2017-06-08  2:53 Stephen Rothwell
2017-03-30  1:14 Stephen Rothwell
2017-03-30  1:08 Stephen Rothwell
2017-03-22  0:00 Stephen Rothwell
2017-03-27 17:14 ` Paul McKenney
2017-03-21 23:57 Stephen Rothwell
2017-03-21  0:28 Stephen Rothwell
2016-06-14  2:10 Stephen Rothwell
2015-12-22 23:06 Stephen Rothwell
2015-12-09  2:35 Stephen Rothwell
2015-12-03 14:51 Mark Brown
2015-12-03 15:49 ` Jani Nikula
2015-12-03 14:47 Mark Brown
2015-12-03 14:52 ` Imre Deak
2015-08-17  3:23 Stephen Rothwell
2015-03-16  2:30 Stephen Rothwell
2015-03-16 13:43 ` Xi Ruoyao
2015-03-16 15:04   ` Jani Nikula
2014-12-03  2:27 Stephen Rothwell
2014-12-03  8:24 ` Jani Nikula
2014-12-03  8:28   ` Stephen Rothwell
2014-11-17  3:04 Stephen Rothwell
2014-07-23  2:38 Stephen Rothwell
2014-07-09  4:06 Stephen Rothwell
2014-05-22  5:44 Stephen Rothwell
2014-05-22  5:40 Stephen Rothwell
2014-05-07  3:24 Stephen Rothwell
2013-10-28  5:46 Stephen Rothwell
2013-10-28  6:12 ` Stephen Rothwell

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