Hello Stephen, Tomer, and others, On Wed, Mar 16, 2022 at 06:32:27PM +1100, Stephen Rothwell wrote: > Hi all, > > After merging the kspp tree, today's linux-next build (x86_64 > allmodconfig) failed like this: > [...] > drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c: In function 'npcmgpio_irq_handler': > include/linux/find.h:40:23: error: array subscript 'long unsigned int[0]' is partly outside array bounds of 'u32[1]' {aka 'unsigned int[1]'} [-Werror=array-bounds] > 40 | val = *addr & GENMASK(size - 1, offset); > | ^~~~~ > drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c:219:13: note: while referencing 'sts' > 219 | u32 sts, en, bit; > | ^~~ Quoting the code in pinctrl-npcm7xx: for_each_set_bit(bit, (const void *)&sts, NPCM7XX_GPIO_PER_BANK) generic_handle_domain_irq(gc->irq.domain, bit); The cast is indeed already a bit suspicious, because such casts can hide type mismatch bugs. The pinctrl-npcm7xx driver probably won't actually *run* on a 64-bit platform (I guess there will be a separate pinctrl-npcm8xx driver for the upcoming 64-bit platform from Nuvoton) but it's better not to have unnecessary 32bit-isms. > > Caused by commit > > 3b588e43ee5c ("pinctrl: nuvoton: add NPCM7xx pinctrl and GPIO driver") > > probably exposed by commit > > a1d1e0e3d80a ("pinctrl: nuvoton: Add driver for WPCM450") > > from the pinctrl tree and enabling -Werror=array-bounds. > > I have applied the following hack patch for today. > > From: Stephen Rothwell > Date: Wed, 16 Mar 2022 18:12:14 +1100 > Subject: [PATCH] fixup for "pinctrl: nuvoton: add NPCM7xx pinctrl and GPIO driver" > > Signed-off-by: Stephen Rothwell > --- > drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c > index 41136f63014a..fddcb7d6bdf4 100644 > --- a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c > +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c > @@ -216,7 +216,8 @@ static void npcmgpio_irq_handler(struct irq_desc *desc) > struct gpio_chip *gc; > struct irq_chip *chip; > struct npcm7xx_gpio *bank; > - u32 sts, en, bit; > + unsigned long sts, bit; > + u32 en; > > gc = irq_desc_get_handler_data(desc); > bank = gpiochip_get_data(gc); > @@ -225,7 +226,7 @@ static void npcmgpio_irq_handler(struct irq_desc *desc) > chained_irq_enter(chip, desc); > sts = ioread32(bank->base + NPCM7XX_GP_N_EVST); > en = ioread32(bank->base + NPCM7XX_GP_N_EVEN); > - dev_dbg(bank->gc.parent, "==> got irq sts %.8x %.8x\n", sts, > + dev_dbg(bank->gc.parent, "==> got irq sts %.8lx %.8x\n", sts, > en); This fix looks reasonable to me. Thanks, Jonathan