From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5114282ED4; Fri, 15 Dec 2023 17:42:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0E005C15; Fri, 15 Dec 2023 09:43:38 -0800 (PST) Received: from [192.168.1.3] (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3404A3F5A1; Fri, 15 Dec 2023 09:42:51 -0800 (PST) Message-ID: Date: Fri, 15 Dec 2023 17:42:50 +0000 Precedence: bulk X-Mailing-List: linux-next@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH 1/2] arm: perf: Fix ARCH=arm build with GCC in armv8pmu_write_evtype() Content-Language: en-US To: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-next@vger.kernel.org, will@kernel.org, u.kleine-koenig@pengutronix.de, Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt , Anshuman Khandual , Suzuki K Poulose , linux-kernel@vger.kernel.org, llvm@lists.linux.dev References: <20231215150040.3342183-1-james.clark@arm.com> <20231215150040.3342183-2-james.clark@arm.com> From: James Clark In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 15/12/2023 16:21, Mark Rutland wrote: > On Fri, Dec 15, 2023 at 03:00:38PM +0000, James Clark wrote: >> LLVM ignores everything inside the if statement and doesn't generate >> errors, but GCC doesn't ignore it, resulting in the following error: >> >> drivers/perf/arm_pmuv3.c: In function 'armv8pmu_write_evtype': >> include/linux/bits.h:34:29: error: left shift count >= width of type [-Werror=shift-count-overflow] >> 34 | (((~UL(0)) - (UL(1) << (l)) + 1) & \ >> >> Fix it by changing the if to #if. > > I reckon it'd be cleaner to use GENMASK_ULL for the TH and TC fields, in > include/linux/perf/arm_pmu.h have: > > | /* > | * PMXEVTYPER: Event selection reg > | */ > | #define ARMV8_PMU_EVTYPE_EVENT GENMASK(15, 0) /* Mask for EVENT bits */ > | #define ARMV8_PMU_EVTYPE_TH GENMASK_ULL(43, 32) /* arm64 only */ > | #define ARMV8_PMU_EVTYPE_TC GENMASK_ULL(63, 61) /* arm64 only */ > > IIUC that should silence this warning, and it'd remove the need for the > ifdeffery and other changes in patch 2. > > Does that work, or am I missing something? > > Thanks, > Mark. > You're right that does work. For some reason I thought there was some component of writing it to the mask that was the issue as well. I'll send another version with that fix instead. Thanks James >> >> Fixes: 3115ee021bfb ("arm64: perf: Include threshold control fields in PMEVTYPER mask") >> Reported-by: Uwe Kleine-K"onig >> Closes: https://lore.kernel.org/linux-arm-kernel/20231215120817.h2f3akgv72zhrtqo@pengutronix.de/ >> Signed-off-by: James Clark >> --- >> drivers/perf/arm_pmuv3.c | 5 +++-- >> 1 file changed, 3 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c >> index 23fa6c5da82c..3ed2086cefc3 100644 >> --- a/drivers/perf/arm_pmuv3.c >> +++ b/drivers/perf/arm_pmuv3.c >> @@ -631,8 +631,9 @@ static void armv8pmu_write_evtype(int idx, unsigned long val) >> ARMV8_PMU_EXCLUDE_EL0 | >> ARMV8_PMU_EXCLUDE_EL1; >> >> - if (IS_ENABLED(CONFIG_ARM64)) >> - mask |= ARMV8_PMU_EVTYPE_TC | ARMV8_PMU_EVTYPE_TH; >> +#if IS_ENABLED(CONFIG_ARM64) >> + mask |= ARMV8_PMU_EVTYPE_TC | ARMV8_PMU_EVTYPE_TH; >> +#endif >> >> val &= mask; >> write_pmevtypern(counter, val); >> -- >> 2.34.1 >>