From: "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>
To: linuxppc-dev@lists.ozlabs.org, mpe@ellerman.id.au,
linux-nvdimm@lists.01.org, dan.j.williams@intel.com
Cc: Jan Kara <jack@suse.cz>,
msuchanek@suse.de,
"Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>
Subject: [PATCH v7 6/7] powerpc/pmem: Avoid the barrier in flush routines
Date: Wed, 1 Jul 2020 12:52:34 +0530 [thread overview]
Message-ID: <20200701072235.223558-7-aneesh.kumar@linux.ibm.com> (raw)
In-Reply-To: <20200701072235.223558-1-aneesh.kumar@linux.ibm.com>
nvdimm expect the flush routines to just mark the cache clean. The barrier
that mark the store globally visible is done in nvdimm_flush().
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
---
arch/powerpc/lib/pmem.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/arch/powerpc/lib/pmem.c b/arch/powerpc/lib/pmem.c
index 5a61aaeb6930..21210fa676e5 100644
--- a/arch/powerpc/lib/pmem.c
+++ b/arch/powerpc/lib/pmem.c
@@ -19,9 +19,6 @@ static inline void __clean_pmem_range(unsigned long start, unsigned long stop)
for (i = 0; i < size >> shift; i++, addr += bytes)
asm volatile(PPC_DCBSTPS(%0, %1): :"i"(0), "r"(addr): "memory");
-
-
- asm volatile(PPC_PHWSYNC ::: "memory");
}
static inline void __flush_pmem_range(unsigned long start, unsigned long stop)
@@ -34,9 +31,6 @@ static inline void __flush_pmem_range(unsigned long start, unsigned long stop)
for (i = 0; i < size >> shift; i++, addr += bytes)
asm volatile(PPC_DCBFPS(%0, %1): :"i"(0), "r"(addr): "memory");
-
-
- asm volatile(PPC_PHWSYNC ::: "memory");
}
static inline void clean_pmem_range(unsigned long start, unsigned long stop)
--
2.26.2
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next prev parent reply other threads:[~2020-07-01 7:28 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-01 7:22 [PATCH v7 0/7] Support new pmem flush and sync instructions for POWER Aneesh Kumar K.V
2020-07-01 7:22 ` [PATCH v7 1/7] powerpc/pmem: Restrict papr_scm to P8 and above Aneesh Kumar K.V
2020-07-01 7:22 ` [PATCH v7 2/7] powerpc/pmem: Add new instructions for persistent storage and sync Aneesh Kumar K.V
2020-07-01 7:22 ` [PATCH v7 3/7] powerpc/pmem: Add flush routines using new pmem store and sync instruction Aneesh Kumar K.V
2020-07-01 7:22 ` [PATCH v7 4/7] libnvdimm/nvdimm/flush: Allow architecture to override the flush barrier Aneesh Kumar K.V
2020-07-01 7:22 ` [PATCH v7 5/7] powerpc/pmem: Update ppc64 to use the new barrier instruction Aneesh Kumar K.V
2020-07-01 7:22 ` Aneesh Kumar K.V [this message]
2020-07-01 7:22 ` [PATCH v7 7/7] powerpc/pmem: Initialize pmem device on newer hardware Aneesh Kumar K.V
2020-07-16 12:55 ` [PATCH v7 0/7] Support new pmem flush and sync instructions for POWER Michael Ellerman
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