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From: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
To: Ben Widawsky <ben.widawsky@intel.com>
Cc: linux-cxl@vger.kernel.org, linux-acpi@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-nvdimm@lists.01.org,
	linux-pci@vger.kernel.org, Bjorn Helgaas <helgaas@kernel.org>,
	Chris Browy <cbrowy@avery-design.com>,
	Christoph Hellwig <hch@infradead.org>,
	David Hildenbrand <david@redhat.com>,
	David Rientjes <rientjes@google.com>,
	Jon Masters <jcm@jonmasters.org>,
	Jonathan Cameron <Jonathan.Cameron@Huawei.com>,
	Rafael Wysocki <rafael.j.wysocki@intel.com>,
	Randy Dunlap <rdunlap@infradead.org>,
	"John Groves (jgroves)" <jgroves@micron.com>,
	"Kelley, Sean V" <sean.v.kelley@intel.com>,
	Jonathan Corbet <corbet@lwn.net>
Subject: Re: [PATCH v5 1/9] cxl/mem: Introduce a driver for CXL-2.0-Type-3 endpoints
Date: Fri, 19 Feb 2021 19:54:44 -0500	[thread overview]
Message-ID: <YDBd1J98VJM0dLvE@Konrads-MacBook-Pro.local> (raw)
In-Reply-To: <20210217040958.1354670-2-ben.widawsky@intel.com>

On Tue, Feb 16, 2021 at 08:09:50PM -0800, Ben Widawsky wrote:
> From: Dan Williams <dan.j.williams@intel.com>
> 
> The CXL.mem protocol allows a device to act as a provider of "System
> RAM" and/or "Persistent Memory" that is fully coherent as if the memory
> was attached to the typical CPU memory controller.
> 
> With the CXL-2.0 specification a PCI endpoint can implement a "Type-3"
> device interface and give the operating system control over "Host
> Managed Device Memory". See section 2.3 Type 3 CXL Device.
> 
> The memory range exported by the device may optionally be described by
> the platform firmware memory map, or by infrastructure like LIBNVDIMM to
> provision persistent memory capacity from one, or more, CXL.mem devices.
> 
> A pre-requisite for Linux-managed memory-capacity provisioning is this
> cxl_mem driver that can speak the mailbox protocol defined in section
> 8.2.8.4 Mailbox Registers.
> 
> For now just land the initial driver boiler-plate and Documentation/
> infrastructure.
> 
> Link: https://www.computeexpresslink.org/download-the-specification
> Cc: Jonathan Corbet <corbet@lwn.net>
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
> Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
> Acked-by: David Rientjes <rientjes@google.com> (v1)
Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>

Albeit you may want to modify 2020 to 2021 in the Copyright sections.
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  reply	other threads:[~2021-02-20  0:55 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-17  4:09 [PATCH v5 0/9] CXL 2.0 Support Ben Widawsky
2021-02-17  4:09 ` [PATCH v5 1/9] cxl/mem: Introduce a driver for CXL-2.0-Type-3 endpoints Ben Widawsky
2021-02-20  0:54   ` Konrad Rzeszutek Wilk [this message]
2021-02-17  4:09 ` [PATCH v5 2/9] cxl/mem: Find device capabilities Ben Widawsky
2021-02-17 12:22   ` Jonathan Cameron
2021-02-17  4:09 ` [PATCH v5 3/9] cxl/mem: Register CXL memX devices Ben Widawsky
2021-02-17  4:09 ` [PATCH v5 4/9] cxl/mem: Add basic IOCTL interface Ben Widawsky
2021-02-17 14:16   ` Jonathan Cameron
2021-02-20  1:22   ` Konrad Rzeszutek Wilk
2021-02-20 16:33     ` Ben Widawsky
2021-02-20 17:48       ` Dan Williams
2021-02-17  4:09 ` [PATCH v5 5/9] cxl/mem: Add a "RAW" send command Ben Widawsky
2021-02-20  1:03   ` Konrad Rzeszutek Wilk
2021-02-17  4:09 ` [PATCH v5 6/9] cxl/mem: Enable commands via CEL Ben Widawsky
2021-02-20  1:11   ` Konrad Rzeszutek Wilk
2021-02-17  4:09 ` [PATCH v5 7/9] cxl/mem: Add set of informational commands Ben Widawsky
2021-02-20  1:12   ` Konrad Rzeszutek Wilk
2021-02-17  4:09 ` [PATCH v5 8/9] MAINTAINERS: Add maintainers of the CXL driver Ben Widawsky
2021-02-17  4:09 ` [RFC PATCH v5 9/9] cxl/mem: Add payload dumping for debug Ben Widawsky

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