From: Ming Lei <firstname.lastname@example.org>
To: Jens Axboe <email@example.com>
Cc: Sagi Grimberg <firstname.lastname@example.org>, Long Li <email@example.com>,
Nadolski Edmund <firstname.lastname@example.org>,
Keith Busch <email@example.com>,
Thomas Gleixner <firstname.lastname@example.org>,
Christoph Hellwig <email@example.com>
Subject: Re: [PATCH V3 0/2] nvme-pci: check CQ after batch submission for Microsoft device
Date: Sat, 23 Nov 2019 05:49:54 +0800 [thread overview]
Message-ID: <20191122214954.GB8700@ming.t460p> (raw)
On Fri, Nov 22, 2019 at 02:04:52PM +0000, Jens Axboe wrote:
> On 11/22/19 3:25 AM, Ming Lei wrote:
> >> as that will still overload the one cpu that the interrupt handler was
> >> assigned to. A dumb fix would be a cpu mask for the threaded interrupt
> > Actually one CPU is fast enough to handle several drive's interrupt handling.
> > Also there is per-queue depth limit, and the interrupt flood issue in network
> > can't be serious on storage.
> This is true today, but it won't be true in the future. Lets aim for a
> solution that's a little more future proof than just "enough today", if
> we're going to make changes in this area.
That should be a new feature for future hardware, and we don't know any
performance details, and it can be hard to prepare for it now. Maybe
such hardware or case never comes:
- storage device has queue depth, which limits the max in-flight requests
to be handled in each queue's interrupt handler.
- Suppose such fast hardware comes, it isn't reasonable for them
to support N:1 mapping(N is big).
- Also IRQ matrix has balanced interrupt handling loading already, that
said most of times, one CPU is just responsible for handing one hw queue's
interrupt. Even in Azure's case, 8 CPUs are mapped to one hw queue, but
there is just several CPUs which is for responsible for at most 2 hw queues.
So could we focus on now and fix the regression first?
Linux-nvme mailing list
next prev parent reply other threads:[~2019-11-22 21:50 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-14 2:59 [PATCH V3 0/2] nvme-pci: check CQ after batch submission for Microsoft device Ming Lei
2019-11-14 2:59 ` [PATCH V3 1/2] nvme-pci: move sq/cq_poll lock initialization into nvme_init_queue Ming Lei
2019-11-14 2:59 ` [PATCH V3 2/2] nvme-pci: check CQ after batch submission for Microsoft device Ming Lei
2019-11-14 4:56 ` Keith Busch
2019-11-14 8:56 ` Ming Lei
2019-11-21 3:11 ` [PATCH V3 0/2] " Ming Lei
2019-11-21 6:14 ` Christoph Hellwig
2019-11-21 7:46 ` Ming Lei
2019-11-21 15:45 ` Keith Busch
2019-11-22 9:44 ` Ming Lei
2019-11-22 9:57 ` Christoph Hellwig
2019-11-22 10:25 ` Ming Lei
2019-11-22 14:04 ` Jens Axboe
2019-11-22 21:49 ` Ming Lei [this message]
2019-11-22 21:58 ` Jens Axboe
2019-11-22 22:30 ` Ming Lei
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