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From: "hch@lst.de" <hch@lst.de>
To: "Sironi, Filippo" <sironi@amazon.de>
Cc: "sagi@grimberg.me" <sagi@grimberg.me>,
	"bigeasy@linutronix.de" <bigeasy@linutronix.de>,
	"linux-nvme@lists.infradead.org" <linux-nvme@lists.infradead.org>,
	"ming.lei@redhat.com" <ming.lei@redhat.com>,
	"helgaas@kernel.org" <helgaas@kernel.org>,
	Keith Busch <kbusch@kernel.org>,
	"tglx@linutronix.de" <tglx@linutronix.de>,
	"hch@lst.de" <hch@lst.de>
Subject: Re: [PATCHv2 2/2] nvme/pci: Mask device interrupts for threaded handlers
Date: Wed, 4 Dec 2019 14:58:51 +0100
Message-ID: <20191204135851.GB31262@lst.de> (raw)
In-Reply-To: <1646A1C5-C2E3-46CD-9269-115601132C4B@amazon.de>

On Wed, Dec 04, 2019 at 10:10:05AM +0000, Sironi, Filippo wrote:
> > +	if (to_pci_dev(nvmeq->dev->dev)->msix_enabled)
> > +		__pci_msix_desc_mask_irq(irq_get_msi_desc(irq), 1);
> 
> Have you considered that __pci_msix_desc_mask_irq will cause
> a trap from guest to hypervisor mode when running virtualized?

As mentioned in my reply we need to route this through the irq chip
abstraction.  With that a PV irq chip handler doesn't need to trap if
it has smarter means available.

> > +	else
> > +		writel(1 << nvmeq->cq_vector, nvmeq->dev->bar + NVME_REG_INTMS);
> 
> What's stopping us from always using this method?

The fact that the NVMe spec doesn't specify it for MSI-X.  From section
3.1.3 of NVMe 1.4:

"This register is used to mask interrupts when using pin-based interrupts,
single message MSI, or multiple message MSI. When using MSI-X, the
interrupt mask table defined as part of MSI-X should be used to mask
interrupts. Host software shall not access this register when configured
for MSI-X; any accesses when configured for MSI-X is undefined. For
interrupt behavior requirements, refer to section 7.5."

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Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-12-02 22:20 [PATCHv2 0/2] Keith Busch
2019-12-02 22:20 ` [PATCHv2 1/2] PCI/MSI: Export __pci_msix_desc_mask_irq Keith Busch
2019-12-02 22:46   ` Christoph Hellwig
2019-12-03  9:04     ` Sebastian Andrzej Siewior
2019-12-06 21:18       ` Keith Busch
2019-12-02 22:20 ` [PATCHv2 2/2] nvme/pci: Mask device interrupts for threaded handlers Keith Busch
2019-12-03  7:47   ` Christoph Hellwig
2019-12-03 12:07     ` Keith Busch
2019-12-04 10:10   ` Sironi, Filippo
2019-12-04 13:58     ` hch [this message]

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