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From: Keith Busch <kbusch@kernel.org>
To: Prike Liang <Prike.Liang@amd.com>
Cc: linux-nvme@lists.infradead.org, Chaitanya.Kulkarni@wdc.com,
	gregkh@linuxfoundation.org, hch@infradead.org,
	stable@vger.kernel.org, Shyam-sundar.S-k@amd.com,
	Alexander.Deucher@amd.com
Subject: Re: [PATCH 2/2] nvme-pci: add AMD PCIe quirk for suspend/resume
Date: Wed, 14 Apr 2021 09:24:08 -0700	[thread overview]
Message-ID: <20210414162408.GC2448507@dhcp-10-100-145-180.wdc.com> (raw)
In-Reply-To: <1618388281-15629-2-git-send-email-Prike.Liang@amd.com>

On Wed, Apr 14, 2021 at 04:18:01PM +0800, Prike Liang wrote:
> The NVME device pluged in some AMD PCIE root port will resume timeout
> from s2idle which caused by NVME power CFG lost in the SMU FW restore.
> This issue can be workaround by using PCIe power set with simple
> suspend/resume process path instead of APST. In the onwards ASIC will
> try do the NVME shutdown save and restore in the BIOS and still need
> PCIe power setting to resume from RTD3 for s2idle.
> 
> Update the nvme_acpi_storage_d3() _with previously added quirk.
> 
> Signed-off-by: Chaitanya Kulkarni <chaitanya.kulkarni@wdc.com>
> [ck: split patches for nvme and pcie]

Chaitanya's Sign-off should be under the annotation explaining what he
changed, and placed below the original author's sign-off.

> Signed-off-by: Prike Liang <Prike.Liang@amd.com>
> Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
> Reviewed-by: Chaitanya Kulkarni <chaitanya.kulkarni@wdc.com>
> Cc: <stable@vger.kernel.org> # 5.11+
> ---

It doesn't appear that you're reading Greg's autobot reply. This spot
right here is where you should describe what is different about this
patch compared to your previous versions.

>  drivers/nvme/host/pci.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
> index 6bad4d4..ce9f42b 100644
> --- a/drivers/nvme/host/pci.c
> +++ b/drivers/nvme/host/pci.c
> @@ -2832,6 +2832,7 @@ static bool nvme_acpi_storage_d3(struct pci_dev *dev)
>  {
>  	struct acpi_device *adev;
>  	struct pci_dev *root;
> +	struct pci_dev *rdev;
>  	acpi_handle handle;
>  	acpi_status status;
>  	u8 val;
> @@ -2845,6 +2846,12 @@ static bool nvme_acpi_storage_d3(struct pci_dev *dev)
>  	if (!root)
>  		return false;
>  
> +	rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));

Instead of assuming '0', shouldn't you use the domain of the NVMe PCI
device?

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  parent reply	other threads:[~2021-04-14 16:24 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-14  8:18 [PATCH 1/2] PCI: add AMD PCIe quirk for nvme shutdown opt Prike Liang
2021-04-14  8:18 ` [PATCH 2/2] nvme-pci: add AMD PCIe quirk for suspend/resume Prike Liang
2021-04-14  8:39   ` Greg KH
2021-04-14 16:24   ` Keith Busch [this message]
2021-04-15  3:22     ` Liang, Prike
2021-04-15  3:59       ` Keith Busch
2021-04-15  6:14         ` Liang, Prike
2021-04-14  8:39 ` [PATCH 1/2] PCI: add AMD PCIe quirk for nvme shutdown opt Greg KH
  -- strict thread matches above, loose matches on Subject: below --
2021-04-14  6:19 Prike Liang
2021-04-14  6:20 ` [PATCH 2/2] nvme-pci: add AMD PCIe quirk for suspend/resume Prike Liang
2021-04-14  6:39   ` Greg KH
2021-04-14  7:13     ` Liang, Prike
2021-04-14  7:48       ` Greg KH
2021-04-14  8:16         ` Liang, Prike
2021-04-14  2:18 [PATCH 1/2] PCI: add AMD PCIe quirk for nvme shutdown opt Prike Liang
2021-04-14  2:18 ` [PATCH 2/2] nvme-pci: add AMD PCIe quirk for suspend/resume Prike Liang
2021-04-14  5:34   ` Greg KH
2021-04-14  6:10     ` Liang, Prike

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