[PATCH v3 0/4] clk: ti: add am33xx spread spectrum clock support

[PATCH v3 0/4] clk: ti: add am33xx spread spectrum clock support

[Dario Binacchi]

As reported by the TI spruh73x RM, MPU and LCD modules support spread
spectrum clocking (SSC) on their output clocks. SSC is used to spread
the spectral peaking of the clock to reduce any electromagnetic
interference (EMI) that may be caused due to the clock’s fundamental
or any of its harmonics.
The series allows you to enable and adjust the spread spectrum clocking
for all am33xx PLLs for which it is supported.


Changes in v3:
- Add '-hz' suffix to "ti,ssc-modfreq" binding.
- Add Tony Lindgren acked tag.
- Use "ti,ssc-modfreq-hz" binding instead of "ti,ssc-modfreq".

Changes in v2:
- Remove SSC registers from dpll_core_ck@490 node (SSC is not supported)
- Add SSC registers to dpll_mpu_ck@488 node.
- Move the DT changes to the previous patch in the series.

Dario Binacchi (4):
  clk: ti: fix typo in routine description
  dt-bindings: ti: dpll: add spread spectrum support
  ARM: dts: am33xx-clocks: add spread spectrum support
  clk: ti: add am33xx spread spectrum clock support

 .../devicetree/bindings/clock/ti/dpll.txt     | 20 +++++
 arch/arm/boot/dts/am33xx-clocks.dtsi          |  4 +-
 drivers/clk/ti/dpll.c                         | 42 +++++++++
 drivers/clk/ti/dpll3xxx.c                     | 87 ++++++++++++++++++-
 include/linux/clk/ti.h                        | 24 +++++
 5 files changed, 174 insertions(+), 3 deletions(-)

-- 
2.17.1

[PATCH v3 1/4] clk: ti: fix typo in routine description

[Dario Binacchi]

Replace _omap3_noncore_dpll_program with omap3_noncore_dpll_program.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
---

(no changes since v1)

 drivers/clk/ti/dpll3xxx.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/ti/dpll3xxx.c b/drivers/clk/ti/dpll3xxx.c
index 6097b099a5df..94d5b5fe9a2b 100644
--- a/drivers/clk/ti/dpll3xxx.c
+++ b/drivers/clk/ti/dpll3xxx.c
@@ -292,7 +292,7 @@ static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n)
 }
 
 /**
- * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly
+ * omap3_noncore_dpll_program - set non-core DPLL M,N values directly
  * @clk:	struct clk * of DPLL to set
  * @freqsel:	FREQSEL value to set
  *
-- 
2.17.1

[PATCH v3 3/4] ARM: dts: am33xx-clocks: add spread spectrum support

[Dario Binacchi]

Registers for adjusting the spread spectrum clocking (SSC) have been
added. As reported by the TI spruh73x RM, SSC is supported only for
LCD and MPU PLLs.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
Acked-by: Tony Lindgren <tony@atomide.com>

---

Changes in v3:
- Add Tony Lindgren acked tag.

Changes in v2:
- Remove SSC registers from dpll_core_ck@490 node (SSC is not supported)
- Add SSC registers to dpll_mpu_ck@488 node.

 arch/arm/boot/dts/am33xx-clocks.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi
index dced92a8970e..a02e0b1229a4 100644
--- a/arch/arm/boot/dts/am33xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am33xx-clocks.dtsi
@@ -204,7 +204,7 @@
 		#clock-cells = <0>;
 		compatible = "ti,am3-dpll-clock";
 		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
-		reg = <0x0488>, <0x0420>, <0x042c>;
+		reg = <0x0488>, <0x0420>, <0x042c>, <0x0424>, <0x0428>;
 	};
 
 	dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 {
@@ -244,7 +244,7 @@
 		#clock-cells = <0>;
 		compatible = "ti,am3-dpll-no-gate-clock";
 		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
-		reg = <0x0498>, <0x0448>, <0x0454>;
+		reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>;
 	};
 
 	dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 {
-- 
2.17.1

[PATCH v3 4/4] clk: ti: add am33xx spread spectrum clock support

[Dario Binacchi]

The patch enables spread spectrum clocking (SSC) for MPU and LCD PLLs.
As reported by the TI spruh73x RM, SSC is only supported for the
DISP/LCD and MPU PLLs on am33xx device. SSC is not supported for DDR,
PER, and CORE PLLs.

Calculating the required values and setting the registers accordingly
was taken from the set_mpu_spreadspectrum routine contained in the
arch/arm/mach-omap2/am33xx/clock_am33xx.c file of the u-boot project.

In locked condition, DPLL output clock = CLKINP *[M/N]. In case of
SSC enabled, the AM335x reference manual explains that there is a
restriction of range of M values. Since the omap2_dpll_round_rate
routine attempts to select the minimum possible N, the value of M
obtained is not guaranteed to be within the range required. With the new
"ti,min-div" parameter it is possible to increase N and consequently M
to satisfy the constraint imposed by SSC.

Signed-off-by: Dario Binacchi <dariobin@libero.it>

---

Changes in v3:
- Use "ti,ssc-modfreq-hz" binding instead of "ti,ssc-modfreq".

Changes in v2:
- Move the DT changes to the previous patch in the series.

 drivers/clk/ti/dpll.c     | 42 +++++++++++++++++++
 drivers/clk/ti/dpll3xxx.c | 85 +++++++++++++++++++++++++++++++++++++++
 include/linux/clk/ti.h    | 24 +++++++++++
 3 files changed, 151 insertions(+)

diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c
index d6f1ac5b53e1..91bea2a9ee0d 100644
--- a/drivers/clk/ti/dpll.c
+++ b/drivers/clk/ti/dpll.c
@@ -290,7 +290,9 @@ static void __init of_ti_dpll_setup(struct device_node *node,
 	struct clk_init_data *init = NULL;
 	const char **parent_names = NULL;
 	struct dpll_data *dd = NULL;
+	int ssc_clk_index;
 	u8 dpll_mode = 0;
+	u32 min_div;
 
 	dd = kmemdup(ddt, sizeof(*dd), GFP_KERNEL);
 	clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
@@ -345,6 +347,28 @@ static void __init of_ti_dpll_setup(struct device_node *node,
 	if (dd->autoidle_mask) {
 		if (ti_clk_get_reg_addr(node, 3, &dd->autoidle_reg))
 			goto cleanup;
+
+		ssc_clk_index = 4;
+	} else {
+		ssc_clk_index = 3;
+	}
+
+	if (dd->ssc_deltam_int_mask && dd->ssc_deltam_frac_mask &&
+	    dd->ssc_modfreq_mant_mask && dd->ssc_modfreq_exp_mask) {
+		if (ti_clk_get_reg_addr(node, ssc_clk_index++,
+					&dd->ssc_deltam_reg))
+			goto cleanup;
+
+		if (ti_clk_get_reg_addr(node, ssc_clk_index++,
+					&dd->ssc_modfreq_reg))
+			goto cleanup;
+
+		of_property_read_u32(node, "ti,ssc-modfreq-hz",
+				     &dd->ssc_modfreq);
+		of_property_read_u32(node, "ti,ssc-deltam", &dd->ssc_deltam);
+		if (of_property_read_bool(node, "ti,ssc-downspread"))
+			dd->ssc_downspread = 1;
+
 	}
 
 	if (of_property_read_bool(node, "ti,low-power-stop"))
@@ -356,6 +380,10 @@ static void __init of_ti_dpll_setup(struct device_node *node,
 	if (of_property_read_bool(node, "ti,lock"))
 		dpll_mode |= 1 << DPLL_LOCKED;
 
+	if (!of_property_read_u32(node, "ti,min-div", &min_div) &&
+	    min_div > dd->min_divider)
+		dd->min_divider = min_div;
+
 	if (dpll_mode)
 		dd->modes = dpll_mode;
 
@@ -585,8 +613,15 @@ static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node)
 	const struct dpll_data dd = {
 		.idlest_mask = 0x1,
 		.enable_mask = 0x7,
+		.ssc_enable_mask = 0x1 << 12,
+		.ssc_ack_mask = 0x1 << 13,
+		.ssc_downspread_mask = 0x1 << 14,
 		.mult_mask = 0x7ff << 8,
 		.div1_mask = 0x7f,
+		.ssc_deltam_int_mask = 0x3 << 18,
+		.ssc_deltam_frac_mask = 0x3ffff,
+		.ssc_modfreq_mant_mask = 0x7f,
+		.ssc_modfreq_exp_mask = 0x7 << 8,
 		.max_multiplier = 2047,
 		.max_divider = 128,
 		.min_divider = 1,
@@ -645,8 +680,15 @@ static void __init of_ti_am3_dpll_setup(struct device_node *node)
 	const struct dpll_data dd = {
 		.idlest_mask = 0x1,
 		.enable_mask = 0x7,
+		.ssc_enable_mask = 0x1 << 12,
+		.ssc_ack_mask = 0x1 << 13,
+		.ssc_downspread_mask = 0x1 << 14,
 		.mult_mask = 0x7ff << 8,
 		.div1_mask = 0x7f,
+		.ssc_deltam_int_mask = 0x3 << 18,
+		.ssc_deltam_frac_mask = 0x3ffff,
+		.ssc_modfreq_mant_mask = 0x7f,
+		.ssc_modfreq_exp_mask = 0x7 << 8,
 		.max_multiplier = 2047,
 		.max_divider = 128,
 		.min_divider = 1,
diff --git a/drivers/clk/ti/dpll3xxx.c b/drivers/clk/ti/dpll3xxx.c
index 94d5b5fe9a2b..e32b3515f9e7 100644
--- a/drivers/clk/ti/dpll3xxx.c
+++ b/drivers/clk/ti/dpll3xxx.c
@@ -291,6 +291,88 @@ static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n)
 	*sd_div = sd;
 }
 
+/**
+ * omap3_noncore_dpll_ssc_program - set spread-spectrum clocking registers
+ * @clk:	struct clk * of DPLL to set
+ *
+ * Enable the DPLL spread spectrum clocking if frequency modulation and
+ * frequency spreading have been set, otherwise disable it.
+ */
+static void omap3_noncore_dpll_ssc_program(struct clk_hw_omap *clk)
+{
+	struct dpll_data *dd = clk->dpll_data;
+	unsigned long ref_rate;
+	u32 v, ctrl, mod_freq_divider, exponent, mantissa;
+	u32 deltam_step, deltam_ceil;
+
+	ctrl = ti_clk_ll_ops->clk_readl(&dd->control_reg);
+
+	if (dd->ssc_modfreq && dd->ssc_deltam) {
+		ctrl |= dd->ssc_enable_mask;
+
+		if (dd->ssc_downspread)
+			ctrl |= dd->ssc_downspread_mask;
+		else
+			ctrl &= ~dd->ssc_downspread_mask;
+
+		ref_rate = clk_hw_get_rate(dd->clk_ref);
+		mod_freq_divider =
+		    (ref_rate / dd->last_rounded_n) / (4 * dd->ssc_modfreq);
+		if (dd->ssc_modfreq > (ref_rate / 70))
+			pr_warn("clock: SSC modulation frequency of DPLL %s greater than %ld\n",
+				__clk_get_name(clk->hw.clk), ref_rate / 70);
+
+		exponent = 0;
+		mantissa = mod_freq_divider;
+		while ((mantissa > 127) && (exponent < 7)) {
+			exponent++;
+			mantissa /= 2;
+		}
+		if (mantissa > 127)
+			mantissa = 127;
+
+		v = ti_clk_ll_ops->clk_readl(&dd->ssc_modfreq_reg);
+		v &= ~(dd->ssc_modfreq_mant_mask | dd->ssc_modfreq_exp_mask);
+		v |= mantissa << __ffs(dd->ssc_modfreq_mant_mask);
+		v |= exponent << __ffs(dd->ssc_modfreq_exp_mask);
+		ti_clk_ll_ops->clk_writel(v, &dd->ssc_modfreq_reg);
+
+		deltam_step = dd->last_rounded_m * dd->ssc_deltam;
+		deltam_step /= 10;
+		if (dd->ssc_downspread)
+			deltam_step /= 2;
+
+		deltam_step <<= __ffs(dd->ssc_deltam_int_mask);
+		deltam_step /= 100;
+		deltam_step /= mod_freq_divider;
+		if (deltam_step > 0xFFFFF)
+			deltam_step = 0xFFFFF;
+
+		deltam_ceil = (deltam_step & dd->ssc_deltam_int_mask) >>
+		    __ffs(dd->ssc_deltam_int_mask);
+		if (deltam_step & dd->ssc_deltam_frac_mask)
+			deltam_ceil++;
+
+		if ((dd->ssc_downspread &&
+		     ((dd->last_rounded_m - (2 * deltam_ceil)) < 20 ||
+		      dd->last_rounded_m > 2045)) ||
+		    ((dd->last_rounded_m - deltam_ceil) < 20 ||
+		     (dd->last_rounded_m + deltam_ceil) > 2045))
+			pr_warn("clock: SSC multiplier of DPLL %s is out of range\n",
+				__clk_get_name(clk->hw.clk));
+
+		v = ti_clk_ll_ops->clk_readl(&dd->ssc_deltam_reg);
+		v &= ~(dd->ssc_deltam_int_mask | dd->ssc_deltam_frac_mask);
+		v |= deltam_step << __ffs(dd->ssc_deltam_int_mask |
+					  dd->ssc_deltam_frac_mask);
+		ti_clk_ll_ops->clk_writel(v, &dd->ssc_deltam_reg);
+	} else {
+		ctrl &= ~dd->ssc_enable_mask;
+	}
+
+	ti_clk_ll_ops->clk_writel(ctrl, &dd->control_reg);
+}
+
 /**
  * omap3_noncore_dpll_program - set non-core DPLL M,N values directly
  * @clk:	struct clk * of DPLL to set
@@ -390,6 +472,9 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
 		ti_clk_ll_ops->clk_writel(v, &dd->control_reg);
 	}
 
+	if (dd->ssc_enable_mask)
+		omap3_noncore_dpll_ssc_program(clk);
+
 	/* We let the clock framework set the other output dividers later */
 
 	/* REVISIT: Set ramp-up delay? */
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index c62f6fa6763d..cba093de62d8 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -63,6 +63,18 @@ struct clk_omap_reg {
  * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
  * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
  * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
+ * @ssc_deltam_reg: register containing the DPLL SSC frequency spreading
+ * @ssc_modfreq_reg: register containing the DPLL SSC modulation frequency
+ * @ssc_modfreq_mant_mask: mask of the mantissa component in @ssc_modfreq_reg
+ * @ssc_modfreq_exp_mask: mask of the exponent component in @ssc_modfreq_reg
+ * @ssc_enable_mask: mask of the DPLL SSC enable bit in @control_reg
+ * @ssc_ack_mask: mask of the DPLL SSC turned on/off bit in @control_reg
+ * @ssc_downspread_mask: mask of the DPLL SSC low frequency only bit in
+ *                       @control_reg
+ * @ssc_modfreq: the DPLL SSC frequency modulation in kHz
+ * @ssc_deltam: the DPLL SSC frequency spreading in permille (10th of percent)
+ * @ssc_downspread: require the only low frequency spread of the DPLL in SSC
+ *                   mode
  * @flags: DPLL type/features (see below)
  *
  * Possible values for @flags:
@@ -110,6 +122,18 @@ struct dpll_data {
 	u8			auto_recal_bit;
 	u8			recal_en_bit;
 	u8			recal_st_bit;
+	struct clk_omap_reg	ssc_deltam_reg;
+	struct clk_omap_reg	ssc_modfreq_reg;
+	u32			ssc_deltam_int_mask;
+	u32			ssc_deltam_frac_mask;
+	u32			ssc_modfreq_mant_mask;
+	u32			ssc_modfreq_exp_mask;
+	u32                     ssc_enable_mask;
+	u32                     ssc_ack_mask;
+	u32                     ssc_downspread_mask;
+	u32                     ssc_modfreq;
+	u32                     ssc_deltam;
+	u8                      ssc_downspread;
 	u8			flags;
 };
 
-- 
2.17.1

Re: [PATCH v3 1/4] clk: ti: fix typo in routine description

[Stephen Boyd]

Quoting Dario Binacchi (2021-03-29 09:42:18)
> Replace _omap3_noncore_dpll_program with omap3_noncore_dpll_program.
> 
> Signed-off-by: Dario Binacchi <dariobin@libero.it>
> ---

Reviewed-by: Stephen Boyd <sboyd@kernel.org>

Re: [PATCH v3 0/4] clk: ti: add am33xx spread spectrum clock support

[Stephen Boyd]

Quoting Dario Binacchi (2021-03-29 09:42:17)
> 
> As reported by the TI spruh73x RM, MPU and LCD modules support spread
> spectrum clocking (SSC) on their output clocks. SSC is used to spread
> the spectral peaking of the clock to reduce any electromagnetic
> interference (EMI) that may be caused due to the clock’s fundamental
> or any of its harmonics.
> The series allows you to enable and adjust the spread spectrum clocking
> for all am33xx PLLs for which it is supported.
> 

What is your merge strategy? Should all the patches go through clk tree?
Or you'll send via arm-soc?

Re: [PATCH v3 0/4] clk: ti: add am33xx spread spectrum clock support

[Tony Lindgren]

* Stephen Boyd <sboyd@kernel.org> [210330 02:25]:
> Quoting Dario Binacchi (2021-03-29 09:42:17)
> > 
> > As reported by the TI spruh73x RM, MPU and LCD modules support spread
> > spectrum clocking (SSC) on their output clocks. SSC is used to spread
> > the spectral peaking of the clock to reduce any electromagnetic
> > interference (EMI) that may be caused due to the clock’s fundamental
> > or any of its harmonics.
> > The series allows you to enable and adjust the spread spectrum clocking
> > for all am33xx PLLs for which it is supported.
> > 
> 
> What is your merge strategy? Should all the patches go through clk tree?
> Or you'll send via arm-soc?

Probably best to just merge all via the clk tree as that's where most of
the changes are.

Regards,

Tony

Re: [PATCH v3 0/4] clk: ti: add am33xx spread spectrum clock support

[Dario Binacchi]

> Il 31/03/2021 07:51 Tony Lindgren <tony@atomide.com> ha scritto:
> 
>  
> * Stephen Boyd <sboyd@kernel.org> [210330 02:25]:
> > Quoting Dario Binacchi (2021-03-29 09:42:17)
> > > 
> > > As reported by the TI spruh73x RM, MPU and LCD modules support spread
> > > spectrum clocking (SSC) on their output clocks. SSC is used to spread
> > > the spectral peaking of the clock to reduce any electromagnetic
> > > interference (EMI) that may be caused due to the clock’s fundamental
> > > or any of its harmonics.
> > > The series allows you to enable and adjust the spread spectrum clocking
> > > for all am33xx PLLs for which it is supported.
> > > 
> > 
> > What is your merge strategy? Should all the patches go through clk tree?
> > Or you'll send via arm-soc?
> 
> Probably best to just merge all via the clk tree as that's where most of
> the changes are.
> 

This means that I no longer have to send patches to TI / OMAP maintainers, commiters 
and fixers, as well as at linux-omap@vger.kernel.org ?
Even if the a1e980789b06 ("am335x-spread-spectrum) clk: ti: add am33xx spread spectrum clock support") 
patch is basically related to the AM33xx/AM43xx SOCs?

Thanks and regards,
Dario

> Regards,
> 
> Tony

Re: [PATCH v3 0/4] clk: ti: add am33xx spread spectrum clock support

[Stephen Boyd]

Quoting Tony Lindgren (2021-03-30 22:51:04)
> * Stephen Boyd <sboyd@kernel.org> [210330 02:25]:
> > Quoting Dario Binacchi (2021-03-29 09:42:17)
> > > 
> > > As reported by the TI spruh73x RM, MPU and LCD modules support spread
> > > spectrum clocking (SSC) on their output clocks. SSC is used to spread
> > > the spectral peaking of the clock to reduce any electromagnetic
> > > interference (EMI) that may be caused due to the clock’s fundamental
> > > or any of its harmonics.
> > > The series allows you to enable and adjust the spread spectrum clocking
> > > for all am33xx PLLs for which it is supported.
> > > 
> > 
> > What is your merge strategy? Should all the patches go through clk tree?
> > Or you'll send via arm-soc?
> 
> Probably best to just merge all via the clk tree as that's where most of
> the changes are.
> 

Ok. If nobody reviews/acks the last patch in a few days I'll merge the
pile through clk tree.

Re: [PATCH v3 0/4] clk: ti: add am33xx spread spectrum clock support

[Dario Binacchi]

Hi Stephen, Hi Tony

> Il 01/04/2021 03:47 Stephen Boyd <sboyd@kernel.org> ha scritto:
> 
>  
> Quoting Tony Lindgren (2021-03-30 22:51:04)
> > * Stephen Boyd <sboyd@kernel.org> [210330 02:25]:
> > > Quoting Dario Binacchi (2021-03-29 09:42:17)
> > > > 
> > > > As reported by the TI spruh73x RM, MPU and LCD modules support spread
> > > > spectrum clocking (SSC) on their output clocks. SSC is used to spread
> > > > the spectral peaking of the clock to reduce any electromagnetic
> > > > interference (EMI) that may be caused due to the clock’s fundamental
> > > > or any of its harmonics.
> > > > The series allows you to enable and adjust the spread spectrum clocking
> > > > for all am33xx PLLs for which it is supported.
> > > > 
> > > 
> > > What is your merge strategy? Should all the patches go through clk tree?
> > > Or you'll send via arm-soc?
> > 
> > Probably best to just merge all via the clk tree as that's where most of
> > the changes are.
> > 
> 
> Ok. If nobody reviews/acks the last patch in a few days I'll merge the
> pile through clk tree.

It's been over a month since I submitted the patches. Meanwhile Tero Kristo has 
reviewed the most important patch of the series. However, I have not seen any 
progress in the state of the series. Furthermore, I don't see the DTS patches 
in the clk tree. Am I missing something? Or do I have to do something? Sorry 
for the questions but I don't have much experience with patch merge strategies.

Thanks and regards,
Dario