From: Marc Zyngier <maz@kernel.org>
To: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
Cc: tglx@linutronix.de, jason@lakedaemon.net, s-anna@ti.com,
robh+dt@kernel.org, lee.jones@linaro.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
david@lechnology.com, wmills@ti.com, praneeth@ti.com
Subject: Re: [PATCH v4 3/5] irqchip/irq-pruss-intc: Add logic for handling reserved interrupts
Date: Tue, 28 Jul 2020 17:37:57 +0100 [thread overview]
Message-ID: <1ae8b42d0e7a09caf01197b11cea2fff@kernel.org> (raw)
In-Reply-To: <1595927918-19845-4-git-send-email-grzegorz.jaszczyk@linaro.org>
On 2020-07-28 10:18, Grzegorz Jaszczyk wrote:
> From: Suman Anna <s-anna@ti.com>
>
> The PRUSS INTC has a fixed number of output interrupt lines that are
> connected to a number of processors or other PRUSS instances or other
> devices (like DMA) on the SoC. The output interrupt lines 2 through 9
> are usually connected to the main Arm host processor and are referred
> to as host interrupts 0 through 7 from ARM/MPU perspective.
>
> All of these 8 host interrupts are not always exclusively connected
> to the Arm interrupt controller. Some SoCs have some interrupt lines
> not connected to the Arm interrupt controller at all, while a few
> others
> have the interrupt lines connected to multiple processors in which they
> need to be partitioned as per SoC integration needs. For example,
> AM437x
> and 66AK2G SoCs have 2 PRUSS instances each and have the host interrupt
> 5
> connected to the other PRUSS, while AM335x has host interrupt 0 shared
> between MPU and TSC_ADC and host interrupts 6 & 7 shared between MPU
> and
> a DMA controller.
>
> Add logic to the PRUSS INTC driver to ignore both these shared and
> invalid interrupts.
>
> Signed-off-by: Suman Anna <s-anna@ti.com>
> Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
> ---
> v3->v4:
> - Due to changes in DT bindings which converts irqs-reserved
> property from uint8-array to bitmask requested by Rob introduce
> relevant changes in the driver.
> - Merge the irqs-reserved and irqs-shared to one property since they
> can be handled by one logic (relevant change was introduced to DT
> binding).
This isn't what I asked for in my initial review.
I repeatedly asked for the *handling* to be common, not for the
properties to be merged. I don't mind either way, but I understood
there were two properties for a good reason. Has this reason gone?
Anyway, I'll come back to it once I start reviewing the series
again.
M.
--
Jazz is not dead. It just smells funny...
next prev parent reply other threads:[~2020-07-28 16:38 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-28 9:18 [PATCH v4 0/5] Add TI PRUSS Local Interrupt Controller IRQChip driver Grzegorz Jaszczyk
2020-07-28 9:18 ` [PATCH v4 1/5] dt-bindings: irqchip: Add PRU-ICSS interrupt controller bindings Grzegorz Jaszczyk
2020-07-29 17:34 ` David Lechner
2020-07-31 11:48 ` Grzegorz Jaszczyk
2020-07-31 14:09 ` David Lechner
2020-07-31 14:16 ` Grzegorz Jaszczyk
2020-07-31 14:35 ` Suman Anna
2020-07-31 21:09 ` Rob Herring
2020-08-02 21:49 ` Grzegorz Jaszczyk
2020-07-28 9:18 ` [PATCH v4 2/5] irqchip/irq-pruss-intc: Add a PRUSS irqchip driver for PRUSS interrupts Grzegorz Jaszczyk
2020-07-29 18:43 ` David Lechner
2020-07-31 11:57 ` Grzegorz Jaszczyk
2020-07-28 9:18 ` [PATCH v4 3/5] irqchip/irq-pruss-intc: Add logic for handling reserved interrupts Grzegorz Jaszczyk
2020-07-28 16:37 ` Marc Zyngier [this message]
2020-07-28 22:23 ` Grzegorz Jaszczyk
2020-07-29 18:48 ` David Lechner
2020-07-31 14:11 ` Grzegorz Jaszczyk
2020-07-28 9:18 ` [PATCH v4 4/5] irqchip/irq-pruss-intc: Implement irq_{get,set}_irqchip_state ops Grzegorz Jaszczyk
2020-07-29 19:23 ` David Lechner
2020-07-31 12:28 ` Grzegorz Jaszczyk
2020-07-31 15:59 ` David Lechner
2020-07-28 9:18 ` [PATCH v4 5/5] irqchip/irq-pruss-intc: Add support for ICSSG INTC on K3 SoCs Grzegorz Jaszczyk
2020-07-29 19:28 ` David Lechner
2020-07-31 12:32 ` Grzegorz Jaszczyk
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