[PATCH v2] ARM: dts: dra7: Add bus_dma_limit for L3 bus

[PATCH v2] ARM: dts: dra7: Add bus_dma_limit for L3 bus

[Roger Quadros]

The L3 interconnect's memory map is from 0x0 to
0xffffffff. Out of this, System memory (SDRAM) can be
accessed from 0x80000000 to 0xffffffff (2GB)

DRA7 does support 4GB of SDRAM but upper 2GB can only be
accessed by the MPU subsystem.

Add the dma-ranges property to reflect the physical address limit
of the L3 bus.

Issues ere observed only with SATA on DRA7-EVM with 4GB RAM
and CONFIG_ARM_LPAE enabled. This is because the controller
supports 64-bit DMA and its driver sets the dma_mask to 64-bit
thus resulting in DMA accesses beyond L3 limit of 2G.

Setting the correct bus_dma_limit fixes the issue.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Cc: stable@kernel.org
---

Changelog:
v2:
- Revised patch with minimal intrusion. i.e. don't change #size-cells
  of device node.

 arch/arm/boot/dts/dra7.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index d78b684e7fca..058b8cbb8ef3 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -148,6 +148,7 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges = <0x0 0x0 0x0 0xc0000000>;
+		dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
 		ti,hwmods = "l3_main_1", "l3_main_2";
 		reg = <0x0 0x44000000 0x0 0x1000000>,
 		      <0x0 0x45000000 0x0 0x1000>;
-- 
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

Re: [PATCH v2] ARM: dts: dra7: Add bus_dma_limit for L3 bus

[Tony Lindgren]

* Roger Quadros <rogerq@ti.com> [200313 02:48]:
> The L3 interconnect's memory map is from 0x0 to
> 0xffffffff. Out of this, System memory (SDRAM) can be
> accessed from 0x80000000 to 0xffffffff (2GB)
> 
> DRA7 does support 4GB of SDRAM but upper 2GB can only be
> accessed by the MPU subsystem.
> 
> Add the dma-ranges property to reflect the physical address limit
> of the L3 bus.
> 
> Issues ere observed only with SATA on DRA7-EVM with 4GB RAM
> and CONFIG_ARM_LPAE enabled. This is because the controller
> supports 64-bit DMA and its driver sets the dma_mask to 64-bit
> thus resulting in DMA accesses beyond L3 limit of 2G.
> 
> Setting the correct bus_dma_limit fixes the issue.

Thanks applying into fixes.

Tony

Re: [PATCH v2] ARM: dts: dra7: Add bus_dma_limit for L3 bus

[Robin Murphy]

On 2020-03-13 9:47 am, Roger Quadros wrote:
> The L3 interconnect's memory map is from 0x0 to
> 0xffffffff. Out of this, System memory (SDRAM) can be
> accessed from 0x80000000 to 0xffffffff (2GB)
> 
> DRA7 does support 4GB of SDRAM but upper 2GB can only be
> accessed by the MPU subsystem.
> 
> Add the dma-ranges property to reflect the physical address limit
> of the L3 bus.
> 
> Issues ere observed only with SATA on DRA7-EVM with 4GB RAM
> and CONFIG_ARM_LPAE enabled. This is because the controller
> supports 64-bit DMA and its driver sets the dma_mask to 64-bit
> thus resulting in DMA accesses beyond L3 limit of 2G.
> 
> Setting the correct bus_dma_limit fixes the issue.

Neat! In principle you should no longer need the specific dma-ranges on 
the PCIe nodes, since AIUI those really only represent a subset of this 
general limitation, but given the other inheritance issue you saw it's 
probably safer to leave them as-is for now.

FWIW,

Reviewed-by: Robin Murphy <robin.murphy@arm.com>

> Signed-off-by: Roger Quadros <rogerq@ti.com>
> Cc: stable@kernel.org
> ---
> 
> Changelog:
> v2:
> - Revised patch with minimal intrusion. i.e. don't change #size-cells
>    of device node.
> 
>   arch/arm/boot/dts/dra7.dtsi | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
> index d78b684e7fca..058b8cbb8ef3 100644
> --- a/arch/arm/boot/dts/dra7.dtsi
> +++ b/arch/arm/boot/dts/dra7.dtsi
> @@ -148,6 +148,7 @@
>   		#address-cells = <1>;
>   		#size-cells = <1>;
>   		ranges = <0x0 0x0 0x0 0xc0000000>;
> +		dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
>   		ti,hwmods = "l3_main_1", "l3_main_2";
>   		reg = <0x0 0x44000000 0x0 0x1000000>,
>   		      <0x0 0x45000000 0x0 0x1000>;
> 

Re: [PATCH v2] ARM: dts: dra7: Add bus_dma_limit for L3 bus

[Tony Lindgren]

* Robin Murphy <robin.murphy@arm.com> [200313 15:06]:
> On 2020-03-13 9:47 am, Roger Quadros wrote:
> > The L3 interconnect's memory map is from 0x0 to
> > 0xffffffff. Out of this, System memory (SDRAM) can be
> > accessed from 0x80000000 to 0xffffffff (2GB)
> > 
> > DRA7 does support 4GB of SDRAM but upper 2GB can only be
> > accessed by the MPU subsystem.
> > 
> > Add the dma-ranges property to reflect the physical address limit
> > of the L3 bus.
> > 
> > Issues ere observed only with SATA on DRA7-EVM with 4GB RAM
> > and CONFIG_ARM_LPAE enabled. This is because the controller
> > supports 64-bit DMA and its driver sets the dma_mask to 64-bit
> > thus resulting in DMA accesses beyond L3 limit of 2G.
> > 
> > Setting the correct bus_dma_limit fixes the issue.
> 
> Neat! In principle you should no longer need the specific dma-ranges on the
> PCIe nodes, since AIUI those really only represent a subset of this general
> limitation, but given the other inheritance issue you saw it's probably
> safer to leave them as-is for now.

Also, Roger, I think omap5 needs a similar patch too, right?
At least pyra has omap5 with 4GB and SATA connector.

> FWIW,
> 
> Reviewed-by: Robin Murphy <robin.murphy@arm.com>

Sorry missed that as I just pushed out the fix.

Regards,

Tony

Re: [PATCH v2] ARM: dts: dra7: Add bus_dma_limit for L3 bus

[Roger Quadros]

On 13/03/2020 17:15, Tony Lindgren wrote:
> * Robin Murphy <robin.murphy@arm.com> [200313 15:06]:
>> On 2020-03-13 9:47 am, Roger Quadros wrote:
>>> The L3 interconnect's memory map is from 0x0 to
>>> 0xffffffff. Out of this, System memory (SDRAM) can be
>>> accessed from 0x80000000 to 0xffffffff (2GB)
>>>
>>> DRA7 does support 4GB of SDRAM but upper 2GB can only be
>>> accessed by the MPU subsystem.
>>>
>>> Add the dma-ranges property to reflect the physical address limit
>>> of the L3 bus.
>>>
>>> Issues ere observed only with SATA on DRA7-EVM with 4GB RAM
>>> and CONFIG_ARM_LPAE enabled. This is because the controller
>>> supports 64-bit DMA and its driver sets the dma_mask to 64-bit
>>> thus resulting in DMA accesses beyond L3 limit of 2G.
>>>
>>> Setting the correct bus_dma_limit fixes the issue.
>>
>> Neat! In principle you should no longer need the specific dma-ranges on the
>> PCIe nodes, since AIUI those really only represent a subset of this general
>> limitation, but given the other inheritance issue you saw it's probably
>> safer to leave them as-is for now.
> 
> Also, Roger, I think omap5 needs a similar patch too, right?
> At least pyra has omap5 with 4GB and SATA connector.

Yes Tony, I'll send a patch for omap5 as well.

> 
>> FWIW,
>>
>> Reviewed-by: Robin Murphy <robin.murphy@arm.com>
> 
> Sorry missed that as I just pushed out the fix.
> 
> Regards,
> 
> Tony
> 

-- 
cheers,
-roger
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki