From: Tero Kristo <t-kristo@ti.com>
To: <linux-clk@vger.kernel.org>, <sboyd@kernel.org>,
<mturquette@baylibre.com>
Cc: <tony@atomide.com>, <linux-omap@vger.kernel.org>
Subject: [PATCH 2/3] clk: ti: dra7xx: mark MCAN clock as DRA76x only
Date: Thu, 30 Apr 2020 11:36:39 +0300 [thread overview]
Message-ID: <20200430083640.8621-3-t-kristo@ti.com> (raw)
In-Reply-To: <20200430083640.8621-1-t-kristo@ti.com>
This clock entry does not exist on any other devices except DRA76,
so mark it as specific to that SoC only.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
---
drivers/clk/ti/clk-7xx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
index 366cb75378cb..146d1d67c732 100644
--- a/drivers/clk/ti/clk-7xx.c
+++ b/drivers/clk/ti/clk-7xx.c
@@ -815,7 +815,7 @@ static const struct omap_clkctrl_reg_data dra7_wkupaon_clkctrl_regs[] __initcons
{ DRA7_WKUPAON_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
{ DRA7_WKUPAON_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0060:24" },
{ DRA7_WKUPAON_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0068:24" },
- { DRA7_WKUPAON_ADC_CLKCTRL, NULL, CLKF_SW_SUP, "mcan_clk" },
+ { DRA7_WKUPAON_ADC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SOC_DRA76, "mcan_clk" },
{ 0 },
};
--
2.17.1
--
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next prev parent reply other threads:[~2020-04-30 8:36 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-30 8:36 [PATCH 0/3] clk: ti: dra7xx: clkctrl data fixes Tero Kristo
2020-04-30 8:36 ` [PATCH 1/3] clk: ti: dra7xx: fix gpu clkctrl parent Tero Kristo
2020-05-14 19:55 ` Stephen Boyd
2020-04-30 8:36 ` Tero Kristo [this message]
2020-05-14 19:55 ` [PATCH 2/3] clk: ti: dra7xx: mark MCAN clock as DRA76x only Stephen Boyd
2020-04-30 8:36 ` [PATCH 3/3] clk: ti: dra7xx: fix RNG clock parent Tero Kristo
2020-05-14 19:55 ` Stephen Boyd
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