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From: Kishon Vijay Abraham I <kishon@ti.com>
To: Tom Joseph <tjoseph@cadence.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Rob Herring <robh@kernel.org>,
	Bjorn Helgaas <bhelgaas@google.com>
Cc: <linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	Arnd Bergmann <arnd@arndb.de>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	<devicetree@vger.kernel.org>, <linux-omap@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	Kishon Vijay Abraham I <kishon@ti.com>
Subject: [PATCH v5 05/14] PCI: cadence: Allow pci_host_bridge to have custom pci_ops
Date: Fri, 22 May 2020 09:06:22 +0530	[thread overview]
Message-ID: <20200522033631.32574-6-kishon@ti.com> (raw)
In-Reply-To: <20200522033631.32574-1-kishon@ti.com>

Certain platforms like TI's J721E allows only 32-bit configuration
space access. In such cases pci_generic_config_read and
pci_generic_config_write cannot be used. Add support in Cadence core
to let pci_host_bridge have custom pci_ops.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 drivers/pci/controller/cadence/pcie-cadence-host.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
index 93a9414932a9..62796791f02c 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-host.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
@@ -508,7 +508,8 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
 	list_splice_init(&resources, &bridge->windows);
 	bridge->dev.parent = dev;
 	bridge->busnr = pcie->bus;
-	bridge->ops = &cdns_pcie_host_ops;
+	if (!bridge->ops)
+		bridge->ops = &cdns_pcie_host_ops;
 	bridge->map_irq = of_irq_parse_and_map_pci;
 	bridge->swizzle_irq = pci_common_swizzle;
 
-- 
2.17.1


  parent reply	other threads:[~2020-05-22  3:37 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-22  3:36 [PATCH v5 00/14] Add PCIe support to TI's J721E SoC Kishon Vijay Abraham I
2020-05-22  3:36 ` [PATCH v5 01/14] PCI: cadence: Fix cdns_pcie_{host|ep}_setup() error path Kishon Vijay Abraham I
2020-05-22  3:36 ` [PATCH v5 02/14] linux/kernel.h: Add PTR_ALIGN_DOWN macro Kishon Vijay Abraham I
2020-05-22  3:36 ` [PATCH v5 03/14] PCI: cadence: Convert all r/w accessors to perform only 32-bit accesses Kishon Vijay Abraham I
2020-05-22 15:54   ` Rob Herring
2020-05-25  3:30     ` Kishon Vijay Abraham I
2020-05-26 15:12       ` Rob Herring
2020-05-27 10:49         ` Kishon Vijay Abraham I
2020-05-27 16:37           ` Rob Herring
2020-05-27 22:06             ` Kishon Vijay Abraham I
2020-06-01  1:16               ` Kishon Vijay Abraham I
2020-06-08 15:58                 ` Kishon Vijay Abraham I
2020-05-22  3:36 ` [PATCH v5 04/14] PCI: cadence: Add support to start link and verify link status Kishon Vijay Abraham I
2020-05-22  3:36 ` Kishon Vijay Abraham I [this message]
2020-05-22  3:36 ` [PATCH v5 06/14] dt-bindings: PCI: cadence: Remove "mem" from reg binding Kishon Vijay Abraham I
2020-05-26 22:53   ` Rob Herring
2020-05-22  3:36 ` [PATCH v5 07/14] PCI: cadence: Add new *ops* for CPU addr fixup Kishon Vijay Abraham I
2020-05-22  3:36 ` [PATCH v5 08/14] PCI: cadence: Fix updating Vendor ID and Subsystem Vendor ID register Kishon Vijay Abraham I
2020-05-22  3:36 ` [PATCH v5 09/14] PCI: cadence: Add MSI-X support to Endpoint driver Kishon Vijay Abraham I
2020-05-22  3:36 ` [PATCH v5 10/14] dt-bindings: PCI: Add host mode dt-bindings for TI's J721E SoC Kishon Vijay Abraham I
2020-05-22  3:36 ` [PATCH v5 11/14] dt-bindings: PCI: Add EP " Kishon Vijay Abraham I
2020-05-22  3:36 ` [PATCH v5 12/14] PCI: j721e: Add TI J721E PCIe driver Kishon Vijay Abraham I
2020-05-22  3:36 ` [PATCH v5 13/14] misc: pci_endpoint_test: Add J721E in pci_device_id table Kishon Vijay Abraham I
2020-05-22  3:36 ` [PATCH v5 14/14] MAINTAINERS: Add Kishon Vijay Abraham I for TI J721E SoC PCIe Kishon Vijay Abraham I

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