From: Rob Herring <robh@kernel.org>
To: Bjorn Helgaas <bhelgaas@google.com>,
Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
Jingoo Han <jingoohan1@gmail.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Binghui Wang <wangbinghui@hisilicon.com>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Fabio Estevam <festevam@gmail.com>,
Jesper Nilsson <jesper.nilsson@axis.com>,
Jonathan Chocron <jonnyc@amazon.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Kevin Hilman <khilman@baylibre.com>,
Kishon Vijay Abraham I <kishon@ti.com>,
Krzysztof Kozlowski <krzk@kernel.org>,
Kukjin Kim <kgene@kernel.org>,
Kunihiko Hayashi <hayashi.kunihiko@socionext.com>,
linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com,
linux-arm-kernel@lists.infradead.org,
linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org,
linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org,
linux-tegra@vger.kernel.org, Lucas Stach <l.stach@pengutronix.de>,
Masahiro Yamada <yamada.masahiro@socionext.com>,
Murali Karicheri <m-karicheri2@ti.com>,
NXP Linux Team <linux-imx@nxp.com>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Pratyush Anand <pratyush.anand@gmail.com>,
Richard Zhu <hongxing.zhu@nxp.com>,
Sascha Hauer <s.hauer@pengutronix.de>,
Shawn Guo <shawnguo@kernel.org>,
Stanimir Varbanov <svarbanov@mm-sol.com>,
Thierry Reding <thierry.reding@gmail.com>,
Xiaowei Song <songxiaowei@hisilicon.com>,
Yue Wang <yue.wang@Amlogic.com>
Subject: [RFC 26/27] PCI: dwc: Remove hardcoded PCI_CAP_ID_EXP offset
Date: Mon, 3 Aug 2020 15:01:15 -0600 [thread overview]
Message-ID: <20200803210116.3132633-27-robh@kernel.org> (raw)
In-Reply-To: <20200803210116.3132633-1-robh@kernel.org>
While the Designware controller appears to hard code the PCI_CAP_ID_EXP
capability register at 0x70, there's no need to hard code this in the
driver as it is discoverable.
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Cc: Pratyush Anand <pratyush.anand@gmail.com>
Cc: linux-omap@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Rob Herring <robh@kernel.org>
---
drivers/pci/controller/dwc/pci-dra7xx.c | 4 +---
drivers/pci/controller/dwc/pci-keystone.c | 11 +++++------
drivers/pci/controller/dwc/pcie-spear13xx.c | 4 +---
3 files changed, 7 insertions(+), 12 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c
index 6184ebc9392d..b4508c3ffe96 100644
--- a/drivers/pci/controller/dwc/pci-dra7xx.c
+++ b/drivers/pci/controller/dwc/pci-dra7xx.c
@@ -73,8 +73,6 @@
#define LINK_UP BIT(16)
#define DRA7XX_CPU_TO_BUS_ADDR 0x0FFFFFFF
-#define EXP_CAP_ID_OFFSET 0x70
-
#define PCIECTRL_TI_CONF_INTX_ASSERT 0x0124
#define PCIECTRL_TI_CONF_INTX_DEASSERT 0x0128
@@ -142,7 +140,7 @@ static int dra7xx_pcie_establish_link(struct dw_pcie *pci)
struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
struct device *dev = pci->dev;
u32 reg;
- u32 exp_cap_off = EXP_CAP_ID_OFFSET;
+ u32 exp_cap_off = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
if (dw_pcie_link_up(pci)) {
dev_err(dev, "link is already up\n");
diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
index 205754a6bc3c..d2eca3afebdb 100644
--- a/drivers/pci/controller/dwc/pci-keystone.c
+++ b/drivers/pci/controller/dwc/pci-keystone.c
@@ -96,8 +96,6 @@
#define LEG_EP 0x1
#define RC 0x2
-#define EXP_CAP_ID_OFFSET 0x70
-
#define KS_PCIE_SYSCLOCKOUTEN BIT(0)
#define AM654_PCIE_DEV_TYPE_MASK 0x3
@@ -1125,22 +1123,23 @@ static int ks_pcie_am654_set_mode(struct device *dev,
static void ks_pcie_set_link_speed(struct dw_pcie *pci, int link_speed)
{
u32 val;
+ u32 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
dw_pcie_dbi_ro_wr_en(pci);
- val = dw_pcie_readl_dbi(pci, EXP_CAP_ID_OFFSET + PCI_EXP_LNKCAP);
+ val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
if ((val & PCI_EXP_LNKCAP_SLS) != link_speed) {
val &= ~((u32)PCI_EXP_LNKCAP_SLS);
val |= link_speed;
- dw_pcie_writel_dbi(pci, EXP_CAP_ID_OFFSET + PCI_EXP_LNKCAP,
+ dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP,
val);
}
- val = dw_pcie_readl_dbi(pci, EXP_CAP_ID_OFFSET + PCI_EXP_LNKCTL2);
+ val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2);
if ((val & PCI_EXP_LNKCAP_SLS) != link_speed) {
val &= ~((u32)PCI_EXP_LNKCAP_SLS);
val |= link_speed;
- dw_pcie_writel_dbi(pci, EXP_CAP_ID_OFFSET + PCI_EXP_LNKCTL2,
+ dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCTL2,
val);
}
diff --git a/drivers/pci/controller/dwc/pcie-spear13xx.c b/drivers/pci/controller/dwc/pcie-spear13xx.c
index 7d0cdfd8138b..a4303148e8b1 100644
--- a/drivers/pci/controller/dwc/pcie-spear13xx.c
+++ b/drivers/pci/controller/dwc/pcie-spear13xx.c
@@ -65,8 +65,6 @@ struct pcie_app_reg {
/* CR6 */
#define MSI_CTRL_INT (1 << 26)
-#define EXP_CAP_ID_OFFSET 0x70
-
#define to_spear13xx_pcie(x) dev_get_drvdata((x)->dev)
static int spear13xx_pcie_establish_link(struct spear13xx_pcie *spear13xx_pcie)
@@ -75,7 +73,7 @@ static int spear13xx_pcie_establish_link(struct spear13xx_pcie *spear13xx_pcie)
struct pcie_port *pp = &pci->pp;
struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
u32 val;
- u32 exp_cap_off = EXP_CAP_ID_OFFSET;
+ u32 exp_cap_off = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
if (dw_pcie_link_up(pci)) {
dev_err(pci->dev, "link already up\n");
--
2.25.1
next prev parent reply other threads:[~2020-08-03 21:02 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-03 21:00 [RFC 00/27] PCI: dwc: Driver clean-ups Rob Herring
2020-08-03 21:00 ` [RFC 01/27] PCI: Allow root and child buses to have different pci_ops Rob Herring
2020-08-03 21:00 ` [RFC 02/27] PCI: dwc: Use DBI accessors instead of own config accessors Rob Herring
2020-08-03 21:00 ` [RFC 03/27] PCI: dwc: Allow overriding bridge pci_ops Rob Herring
2020-08-03 21:00 ` [RFC 04/27] PCI: dwc: Add a default pci_ops.map_bus for root port Rob Herring
2020-08-03 21:00 ` [RFC 05/27] PCI: dwc: al: Use pci_ops for child config space accessors Rob Herring
2020-08-03 21:00 ` [RFC 06/27] PCI: dwc: keystone: Use pci_ops for " Rob Herring
2020-08-03 21:00 ` [RFC 07/27] PCI: dwc: tegra: Use pci_ops for root " Rob Herring
2020-08-03 21:00 ` [RFC 08/27] PCI: dwc: meson: " Rob Herring
2020-08-03 21:00 ` [RFC 09/27] PCI: dwc: kirin: " Rob Herring
2020-08-03 21:00 ` [RFC 10/27] PCI: dwc: exynos: " Rob Herring
2020-08-03 21:01 ` [RFC 11/27] PCI: dwc: histb: " Rob Herring
2020-08-03 21:01 ` [RFC 12/27] PCI: dwc: Remove dwc specific config accessor ops Rob Herring
2020-08-03 21:01 ` [RFC 13/27] PCI: dwc: Use generic config accessors Rob Herring
2020-08-03 21:01 ` [RFC 14/27] PCI: Also call .add_bus() callback for root bus Rob Herring
2020-08-03 21:01 ` [RFC 15/27] PCI: dwc: keystone: Convert .scan_bus() callback to use add_bus Rob Herring
2020-08-03 21:01 ` [RFC 16/27] PCI: dwc: Convert to use pci_host_probe() Rob Herring
2020-08-03 21:01 ` [RFC 17/27] PCI: dwc: Remove root_bus pointer Rob Herring
2020-08-03 21:01 ` [RFC 18/27] PCI: dwc: Remove storing of PCI resources Rob Herring
2020-08-03 21:01 ` [RFC 19/27] PCI: dwc: Simplify config space handling Rob Herring
2020-08-03 21:01 ` [RFC 20/27] PCI: dwc/keystone: Drop duplicated 'num-viewport' Rob Herring
2020-08-03 21:01 ` [RFC 21/27] PCI: dwc: Check CONFIG_PCI_MSI inside dw_pcie_msi_init() Rob Herring
2020-08-03 21:01 ` [RFC 22/27] PCI: dwc/imx6: Remove duplicate define PCIE_LINK_WIDTH_SPEED_CONTROL Rob Herring
2020-08-03 21:01 ` [RFC 23/27] PCI: dwc/meson: Drop unnecessary RC config space initialization Rob Herring
2020-08-03 21:01 ` [RFC 24/27] PCI: dwc/meson: Rework PCI config and DW port logic register accesses Rob Herring
2020-08-03 21:01 ` [RFC 25/27] PCI: dwc/qcom: Use common PCI register definitions Rob Herring
2020-08-03 21:01 ` Rob Herring [this message]
2020-08-03 21:01 ` [RFC 27/27] PCI: dwc/tegra: Use common Designware port logic " Rob Herring
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