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Fri, 25 Sep 2020 08:59:10 +0000 Date: Fri, 25 Sep 2020 16:56:44 +0800 From: Jisheng Zhang To: Rob Herring , Niklas Cassel Cc: Ard Biesheuvel , Kishon Vijay Abraham I , Lorenzo Pieralisi , Bjorn Helgaas , Jingoo Han , Gustavo Pimentel , Thierry Reding , Vidya Sagar , PCI , linux-omap , Linux Kernel Mailing List , Linux ARM Subject: Re: [PATCH] PCI: dwc: Move allocate and map page for msi out of dw_pcie_msi_init() Message-ID: <20200925165644.312f76a4@xhacker.debian> In-Reply-To: References: <20200923142607.10c89bd2@xhacker.debian> X-Mailer: Claws Mail 3.17.6 (GTK+ 2.24.32; x86_64-pc-linux-gnu) Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-ClientProxiedBy: TYAPR01CA0160.jpnprd01.prod.outlook.com (2603:1096:404:7e::28) To DM6PR03MB4555.namprd03.prod.outlook.com (2603:10b6:5:102::17) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from xhacker.debian (124.74.246.114) by TYAPR01CA0160.jpnprd01.prod.outlook.com (2603:1096:404:7e::28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3412.20 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: BdPrT0Yh4rmvEI6YYpkXg3kLOxLHCGSZGcp9oO9vgWeX8Rkvk0G8XjnDz8X1nqgWQkxkRBoqA9zxIcrqJ0NVDVBSU8Q52YCZfdBdObPZm9H/2HT8yXPX5QGDo0/YyOmc/qCh0AVrDOJg6/INwRhh2yZPOqNYw1WIqYGBFhmNmTbka+xBelVDtMSYLXRuVNB3r8EXwfKTNeHOnI050VHg0ZYaCPqoCqv8CMTcNjAle0m9YVOmK3mA8tK30RgEdgMG/M9d74CZkz7aaO/8FtC2VJJzn0xRLagjJvWkGLFUYmpvUC5qM65Xj87jPm24hBmhrkd7XGEgVzlZgh1KEm4NVM+eMpGDh57y9ApuzT1/bGG/N8Xn8QvryeMK4rYvhmEqHYynjLQn+jVH3Dd2wHMDFYqCuksbz95BFsPrxVLSBWI+rg+hxhl6sCYzEZF0aJsK4suLzZQFdFK3gmi7k+NTh6hNIQWRvwJ/+4MzF1DmeHxmX2LOTxxQRNvAjLBmfeJZTbjakfJGJaVBQBNpN8MNX4+TzUSPIQb70bHQsiuOR9h3bxQoqTAeuvh0ngUG00+vwsUhtOae8ZIyQArX0XlkwFkafpNGVgShwsblIFEpmD1uWOqOXXdi+tJ6/6TJJyFIInzHUjAuL+jkBYTTo11rPA== X-OriginatorOrg: synaptics.com X-MS-Exchange-CrossTenant-Network-Message-Id: bc6b7ce1-1805-4d68-1135-08d861314461 X-MS-Exchange-CrossTenant-AuthSource: DM6PR03MB4555.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Sep 2020 08:59:10.3068 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 335d1fbc-2124-4173-9863-17e7051a2a0e X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: WVoef3eU/5pi49sVBxYtkF4NbCqwEsgTDrne5wuKAu0ijhABimEccEGN3it9utnmXlZH207zycXv8nVWfhQCsw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR03MB2682 Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org On Thu, 24 Sep 2020 07:28:25 -0600 Rob Herring wrote: > CAUTION: Email originated externally, do not click links or open attachments unless you recognize the sender and know the content is safe. > > > On Thu, Sep 24, 2020 at 5:00 AM Ard Biesheuvel wrote: > > > > On Wed, 23 Sep 2020 at 08:28, Jisheng Zhang wrote: > > > > > > Currently, dw_pcie_msi_init() allocates and maps page for msi, then > > > program the PCIE_MSI_ADDR_LO and PCIE_MSI_ADDR_HI. The Root Complex > > > may lose power during suspend-to-RAM, so when we resume, we want to > > > redo the latter but not the former. If designware based driver (for > > > example, pcie-tegra194.c) calls dw_pcie_msi_init() in resume path, the > > > previous msi page will be leaked. > > > > > > Move the allocate and map msi page from dw_pcie_msi_init() to > > > dw_pcie_host_init() to fix this problem. > > > > > > Fixes: 56e15a238d92 ("PCI: tegra: Add Tegra194 PCIe support") > > > Signed-off-by: Jisheng Zhang > > > > Why do you allocate a page for this in the first place? Isn't > > PCIE_MSI_ADDR_HI:PCIE_MSI_ADDR_LO simply a magic DMA address that > > never gets forwarded across to the CPU side of the host bridge, and > > triggers a SPI instead, which gets handled by reading > > PCIE_MSI_INTR0_STATUS ? > > My question too after digging into this some more. I've asked the > question on the thread that further complicated all this changing from > virt_to_phys() to dma_map_page()[1]. > > > Couldn't you just map the zero page instead? > > Why a page even? You could use PCIE_MSI_ADDR_LO address itself even. > Or just an address in the driver data which is what some other drivers > do. > Thank Ard and Rob. I have sent out V3 (https://lkml.org/lkml/2020/9/25/272) which uses an address in the driver data for MSI address. Hi Niklas, can you please try v3 to see whether it solves your problem as well? Thanks